CN100456463C - Semiconductor device and method of manufacturing a semiconductor device - Google Patents
Semiconductor device and method of manufacturing a semiconductor device Download PDFInfo
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- CN100456463C CN100456463C CNB2006100771739A CN200610077173A CN100456463C CN 100456463 C CN100456463 C CN 100456463C CN B2006100771739 A CNB2006100771739 A CN B2006100771739A CN 200610077173 A CN200610077173 A CN 200610077173A CN 100456463 C CN100456463 C CN 100456463C
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- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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Abstract
Disclosed is a semi-conductor which comprises an insulated film (10) on the semi-conductor, an electric conductor welding plate (11) formed on the insulated film (10), and a first opening pattern (12) formed on the electric conductor welding plate (11). The flowability of the conductor will be absorbed by the first opening pattern (12) with the flow of electric conductors that formed the conductor welding plate (11). When the conductor welding plate (11) is similar to a polygon, the first opening pattern (12) will be formed near to each angle on the conductor welding plate (11), in the case, the first opening pattern (12) forms an L shape gap with the two sides of the angle.
Description
Technical field
The present invention relates to semiconductor device and manufacture method thereof, relate in particular to a kind ofly when wire-bonded etc.,, also can suppress to produce the semiconductor device and the manufacture method thereof of stress even electric conductor flows to periphery from the central portion of electric conductor pad.
Background technology
In recent years, in order to make the semiconductor device miniaturization, (for example with reference to patent documentation 1) carried out in the exploitation of the technology of configured electrodes pad on the significant surface that is formed with transistor etc.
Patent documentation 1: the spy opens 2003-086620 communique (Fig. 1)
Figure 14 is used to illustrate the cutaway view of the structure of semiconductor device in the past.Semiconductor device shown in this figure has the transistor that is formed on the silicon substrate 101.On transistor and element isolation film 102, be formed with the 1st interlayer dielectric 108.On the 1st interlayer dielectric 108, be formed with the wiring of Al alloy 109a, 109b.The wiring of Al alloy 109a, 109b are connected with the extrinsic region 107a, the 107b that become transistorized source electrode and drain electrode respectively.
On the 1st interlayer dielectric 108 and on the wiring of Al alloy 109a, the 109b, be formed with the 2nd interlayer dielectric 110.On the 2nd interlayer dielectric 110, be formed with alloy pad 111.The end of Al alloy pad 111 is positioned at transistorized top.
Be formed with passivating film 113 on the 2nd interlayer dielectric 110 He on the Al alloy pad 111.At the opening portion 113a that is formed with on the passivating film 113 on the central portion that is positioned at Al alloy pad 111.Be positioned at joint leaded (not shown) on the Al alloy pad 111 of opening portion 113a.
When wire-bonded is on the electric conductor pad etc., the central portion to the electric conductor pad applies power sometimes.In this case, the electric conductor that forms pad flows to periphery from central portion, can produce stress in the end of pad.Therefore, sometimes be positioned at the pad end below interlayer dielectric on produce the crack.And, destroy the possibility of elements such as transistor in addition.
In addition, do not producing under the situation in crack etc.,, can change so be positioned at the electrical characteristics of the element (for example transistor) of below, pad end sometimes owing to residual always in the end of pad stress is arranged.
Summary of the invention
The present invention even its purpose is to provide a kind of electric conductor to flow to periphery from the central portion of electric conductor pad, also can suppress semiconductor device and manufacture method thereof that stress produces in order to address the above problem.
In the 1st invention of the present invention, semiconductor device has: be positioned on the semiconductor element or the dielectric film of top; Be formed on the electric conductor pad on the described dielectric film, the flat shape of described electric conductor pad is a polygonal, and has the patterns of openings of the shape of slit of extending from the bight of the described electric conductor pad of the mediad of described electric conductor pad; And diaphragm; it is formed on the described dielectric film and on the described electric conductor pad; and on described electric conductor pad, has peristome; imbed the part of described diaphragm in the part 1 of described patterns of openings, the part 2 of described patterns of openings is formed in the described peristome of described diaphragm.
In the 2nd invention of the present invention, the manufacture method of semiconductor device has: on the semiconductor element or above form the operation of dielectric film; On described dielectric film, form the operation of electric conductor film; Form described electric conductor film by pattern, form the operation of electric conductor pad and patterns of openings, described electric conductor pad is positioned at that the top of described semiconductor element and its are plane to be polygonal, described patterns of openings is positioned at described electric conductor pad, and it is the shape of slit of extending to the bight of described electric conductor pad from the central portion of described electric conductor pad; With; in the operation that forms diaphragm on the described dielectric film and on the described electric conductor pad; in the operation that forms described diaphragm; imbed the part of described diaphragm in the part 1 of described opening figure, and with on the described electric conductor pad and the mode that has peristome on the part 2 of described opening figure form described diaphragm.
In addition, in other schemes that propose in order to address the above problem, semiconductor device of the present invention has:
Be positioned on the semiconductor element or the dielectric film of top; With
Be formed on the electric conductor pad on the described dielectric film; With
Be formed on the 1st patterns of openings on the described electric conductor pad.
According to this semiconductor device, owing on the electric conductor pad, be formed with the 1st patterns of openings, so, flowing even form the electric conductor of electric conductor pad, the flowability of electric conductor also can be absorbed by the 1st patterns of openings.Thereby the stress that can be suppressed at the periphery of electric conductor pad produces.Described electric conductor pad for example is made of the Al alloy.
In the flat shape of described electric conductor pad under polygonal situation roughly, described the 1st patterns of openings be preferably formed in described electric conductor pad each bight near.In this case, described the 1st patterns of openings also can have the roughly slit of L word shape, or has the 1st slit that extends to described bight from the central portion of described electric conductor pad, and the slit of described roughly L word shape disposes along 2 limits that form described bight.In the latter case, described the 1st patterns of openings preferably also has 2 article of the 2nd slit that extends along 2 limits that form described bight respectively.
Flat shape at described electric conductor pad is under the situation of sub-circular or approximate ellipsoidal, and described the 1st patterns of openings preferably has a plurality of slits that dispose along the edge of described electric conductor pad.
The 2nd patterns of openings that also can also have the substantial middle portion that is formed on described electric conductor pad.
In addition, can also have be respectively formed on the described dielectric film and the periphery of described electric conductor pad on diaphragm, and the part of described diaphragm also can be embedded in described the 1st patterns of openings.In this case, the described diaphragm that is embedded in described the 1st patterns of openings of the electric conductor of Liu Donging is blocked.
Another kind of semiconductor device of the present invention has:
Be positioned on the semiconductor element or the 1st dielectric film of top; With
Be formed on the 1st electric conductor pad on described the 1st dielectric film; With
Be formed on the 1st patterns of openings of the periphery of described the 1st electric conductor pad; With
Be formed on the periphery of described the 1st dielectric film and described the 1st electric conductor pad, and on described the 1st electric conductor pad, have the 2nd dielectric film of opening portion; With
Be formed on described the 2nd dielectric film, and be embedded in described opening portion and the 2nd electric conductor pad that is connected with described the 1st electric conductor pad by its part.
Can also have the 2nd patterns of openings that is formed on described the 2nd electric conductor pad.
Another semiconductor device of the present invention has:
Be positioned on the semiconductor element or the 1st dielectric film of top; With
Be formed on the 1st electric conductor pad on described the 1st dielectric film; With
Be formed on described the 1st dielectric film, and on described the 1st electric conductor pad, have the 2nd dielectric film of opening portion; With
Be formed on described the 2nd dielectric film, and be embedded in described opening portion and the 2nd electric conductor pad that is connected with described the 1st electric conductor pad by its part; With
Be formed on described the 2nd electric conductor pad, and be positioned at the patterns of openings of described opening portion.
The manufacture method of semiconductor device of the present invention comprises:
On the semiconductor element or above form the operation of dielectric film; With
On described dielectric film, form the operation of electric conductor film; With
Form described electric conductor film by pattern, and form the electric conductor pad of the top that is positioned at described semiconductor element and the operation that is positioned at the patterns of openings of this electric conductor pad respectively.
Can also comprise: after the operation that forms described electric conductor pad and described patterns of openings, the operation of bonding wire on described electric conductor pad.
Description of drawings
Fig. 1 (A) is the cutaway view of manufacture method that is used to illustrate the semiconductor device of the 1st execution mode, (B) is the cutaway view that is used for the next process of explanation (A).
Fig. 2 (A) is the cutaway view that is used for the next process of key diagram 1 (B), and B is the vertical view of the semiconductor device in the state of (A).
Fig. 3 (A) is the cutaway view that is used for the next process of key diagram 2 (A), (B) is the vertical view of the semiconductor device in the state of (A).
Fig. 4 is the vertical view of structure that is used to illustrate the semiconductor device of the 2nd execution mode.
Fig. 5 is the vertical view of structure that is used to illustrate the semiconductor device of the 3rd execution mode.
Fig. 6 is the vertical view of structure that is used to illustrate the semiconductor device of the 4th execution mode.
Fig. 7 is the vertical view of structure that is used to illustrate the semiconductor device of the 5th execution mode.
Fig. 8 is the vertical view of structure that is used to illustrate the semiconductor device of the 6th execution mode.
Fig. 9 is the vertical view of structure that is used to illustrate the semiconductor device of the 7th execution mode.
Figure 10 (A) is the vertical view of structure that is used to illustrate the semiconductor device of the 8th execution mode, (B) is the vertical view of the semiconductor device shown in Figure 10 (A).
Figure 11 (A) is the cutaway view of manufacture method that is used to illustrate the semiconductor device of the 9th execution mode, (B) is the cutaway view that is used for the next process of explanation (A).
Figure 12 is the cutaway view of structure that is used to illustrate the semiconductor device of the 10th execution mode.
Figure 13 is the cutaway view of structure that is used to illustrate the semiconductor device of the 11st execution mode.
Figure 14 is used to illustrate the cutaway view of the structure of semiconductor device in the past.
Among the figure: 1, the 101-silicon substrate, 2, the 102-element isolation film, 3-grid oxidation film, 4a-gate electrode, the 4b-polysilicon resistance, the 5-sidewall, 6a, 6b-low concentration impurity zone, 7a, 7b, 107a, the 107b-extrinsic region, 8,108-the 1st interlayer dielectric, 8a, the 8b-connecting hole, 9a, 9b, 11b, 109a, the wiring of 109b-Al alloy, 10,110-the 2nd interlayer dielectric, 11,111-Al alloy pad, the 12-patterns of openings, 12a, 12b-slit (slit), 13, the 113-passivating film, 13a, 14a, 20, the 113a-opening portion, 14-the 3rd interlayer dielectric, 15-2Al alloy pad, 16-patterns of openings.
Embodiment
Below, with reference to accompanying drawing embodiments of the present invention are described.Each figure of Fig. 1, Fig. 2 (A) and Fig. 3 (A) are the cutaway views of manufacture method that is used to illustrate the semiconductor device of the present invention's the 1st execution mode.Fig. 2 (B) and Fig. 3 (B) are respectively the vertical views of the semiconductor device under the state of Fig. 2 (A) and Fig. 3 (A).
At first, shown in Fig. 1 (A), on silicon substrate 1, form element isolation film 2, will be formed with transistorized element area and separate from other zones.Element isolation film 2 also can form by the LOCOS oxidizing process, can also be embedded on the silicon substrate 1 by the trench isolation method.
Then, silicon substrate 1 is carried out thermal oxidation.Thus, on the silicon substrate 1 that is positioned at element area, formed grid oxidation film 3.Then, forming polysilicon film on the grid oxidation film 3 He on the element isolation film 2, and pattern forms this polysilicon film.Thus, on grid oxidation film 3, form gate electrode 4a, on element isolation film 2, formed polysilicon resistance 4b.Then, with gate electrode 4a and element isolation film 2 as mask, implanted dopant on silicon substrate 1.Thus, transistorized low concentration impurity zone 6a, 6b on silicon substrate 1, have been formed.
Then, form silicon oxide film comprising on whole of gate electrode 4a, and this silicon oxide film of etching.Thus, each sidewall of gate electrode 4a and polysilicon resistance 4b is covered by sidewall (side wall) 5.Then, with gate electrode 4a, sidewall 5 and element isolation film 2 as mask, implanted dopant on silicon substrate 1.Thus, on silicon substrate 1, form extrinsic region 7a, 7b as transistorized source electrode and drain electrode.
Like this, the element area at silicon substrate 1 has formed transistor.
Then, comprising on transistorized whole that forming with the silica is the 1st interlayer dielectric 8 of principal component.The 1st interlayer dielectric 8 has the 1st layer of forming by the CVD method, as the 2nd layer of sog film and the 3rd layer of forming by the CVD method.The 2nd layer surperficial etched.By being provided with the 2nd layer, improved the surface of the 1st interlayer dielectric 8.
Then, on the 1st interlayer dielectric 8, apply photoresist film (not shown), and the exposure, this photoresist film develops.Thus, on the 1st interlayer dielectric 8, formed corrosion-resisting pattern.Then, this corrosion-resisting pattern is come etching the 1st interlayer dielectric 8 as mask.Thus, on the 1st interlayer dielectric 8, formed connecting hole 8a, the 8b that lays respectively on extrinsic region 7a, the 7b.Then, remove corrosion-resisting pattern.
Then, in each connecting hole 8a, 8b and on the 1st interlayer dielectric 8, form the Al alloy film by sputtering method.Then, on this Al alloy film, apply photoresist film (not shown), and the exposure, this photoresist film develops.Thus, on the Al alloy film, formed corrosion-resisting pattern.Then, this corrosion-resisting pattern is come etching Al alloy film as mask.Thus, the wiring of Al alloy 9a, 9b on the 1st interlayer dielectric 8, have been formed.Al alloy wiring 9a is connected with extrinsic region 7a via connecting hole 8a, and Al alloy wiring 9b is connected with extrinsic region 7b via connecting hole 8b.Then, remove corrosion-resisting pattern.
Then, forming the 2nd interlayer dielectric 10 on the 1st interlayer dielectric 8 and on the wiring of Al alloy 9a, the 9b.The structure of the 2nd interlayer dielectric 10 is identical with the formation method with the structure of the 1st interlayer dielectric 8 with the formation method.Then, on the 2nd interlayer dielectric 10, apply photoresist film (not shown), and the exposure, this photoresist film develops.Thus, on the 2nd interlayer dielectric 10, formed corrosion-resisting pattern.Then, this corrosion-resisting pattern is come etching the 2nd interlayer dielectric 10 as mask.Thus, on the 2nd interlayer dielectric 10, formed connecting hole (not shown).Then, remove corrosion-resisting pattern.
Then, shown in Fig. 1 (B), on the 2nd interlayer dielectric 10 and in the not shown connecting hole, form the Al alloy film by sputtering method.
Then, as Fig. 2 (A) and (B) shown in, on the Al alloy film, apply photoresist film (not shown), and the exposure, this photoresist film develops.Thus, on the Al alloy film, formed corrosion-resisting pattern.Then, this corrosion-resisting pattern is come etching Al alloy film as mask.Thus, on the 2nd interlayer dielectric 10, formed Al alloy pad 11 and Al alloy wiring 11b.The part of Al alloy wiring 11b is embedded in the described connecting hole.Then, remove corrosion-resisting pattern.
Shown in Fig. 2 (B), Al alloy pad 11 roughly is square, and is connected with Al alloy wiring 11b.In addition, a bight of Al alloy pad 11 is positioned at transistorized top, and another bight is positioned at the top of polysilicon resistance 4b.On 4 bights of Al alloy pad 11, be formed with the patterns of openings 12 of slit-shaped respectively.Patterns of openings 12 roughly is the L word shape, is provided on the direction on 2 limits that form the bight.
Then, as Fig. 3 (A) and (B), on each of the 2nd interlayer dielectric 10, Al alloy pad 11 and Al alloy wiring 11b and in the patterns of openings 12, formed the passivating film 13 that stacks gradually silicon oxide film and silicon nitride film by the CVD method.Then, on passivating film 13, apply photoresist film, and the exposure, this photoresist film develops.Thus, on passivating film 13, formed corrosion-resisting pattern.Then, this corrosion-resisting pattern is come etch passivation film 13 as mask.Thus, forming the opening portion 13a that is positioned on the Al alloy pad 11 on the passivating film 13.Inboard at opening portion 13a does not comprise patterns of openings 12, and passivating film 13 is kept the state of the inside that is embedded in patterns of openings 12.
Then, by terminal conjunction method will go between (not shown) be connected with the Al alloy pad 11 that is positioned at opening portion 13a.At this moment, owing to applied power, flow to periphery so form the Al alloy of Al alloy pad 11 to the Al alloy pad 11 that is positioned at opening portion 13a.The Al alloy that has flowed is towards 4 bights of Al alloy pad 11.But owing to imbedded passivating film 13 in the inside of the patterns of openings 12 in bight, so the part of the Al alloy that has flowed is blocked by patterns of openings 12.Therefore, compared with the past, can suppress the Al alloy and concentrate on the bight.
Thereby, according to present embodiment, compared with the past the diminishing of the stress that the bight produced of Al alloy pad 11.Therefore, can be suppressed on the 2nd interlayer dielectric 10 and produce the crack.And, can suppress to be positioned at the transistor of Al alloy pad 11 belows and the destruction of polysilicon resistance 4b.And, can suppress the transistor that produces by stress and the characteristic variations of polysilicon resistance 4b.
Fig. 4 is the vertical view of structure that is used to illustrate the semiconductor device of the present invention's the 2nd execution mode, and it is equivalent to the Fig. 3 (B) in the 1st execution mode.Semiconductor device shown in this figure except the shape of Al alloy pad 11, has and the identical structure of making by the 1st execution mode of semiconductor device.And the manufacturing method for semiconductor device shown in this figure is identical with the manufacturing method for semiconductor device of the 1st execution mode.Below, give identical symbol for the structure identical, and omit its explanation with the 1st execution mode.
In the present embodiment, Al alloy pad 11 is sub-circular.Patterns of openings 12 has a plurality of slits.These a plurality of slits are set by the edge along Al alloy pad 11.Be formed with opening portion 13a on the passivating film 13 that is positioned on the Al alloy pad 11, passivating film 13 keeps being embedded in the state on the patterns of openings 12.In addition, below the periphery of Al alloy pad 11, dispose transistor shown in the 1st execution mode (not shown) and polysilicon resistance (not shown).
In the present embodiment, when wire-bonded had been positioned on the Al alloy pad 11 of opening portion 13a (not shown), identical with the 1st execution mode, the Al alloy that forms Al alloy pad 11 can flow to periphery.But, owing to be embedded with passivating film 13 in the inside of the patterns of openings 12 of the periphery that is positioned at Al alloy pad 11, so, by the effect identical, can suppress the Al alloy and concentrate on periphery with the 1st execution mode.
Therefore, according to present embodiment, can access the effect identical with the 1st execution mode.
Fig. 5 is the vertical view of structure that is used to illustrate the semiconductor device of the 3rd execution mode, and it is equivalent to the Fig. 3 (B) in the 1st execution mode.Semiconductor device shown in this figure except the patterns of openings 12 in the bight that is arranged on Al alloy pad 11 is positioned at the opening portion 13a this point that is set on the passivating film 13, has the structure identical with the 1st execution mode.Therefore, do not imbed passivating film 13 in the inside of patterns of openings 12.In addition, the manufacture method of the semiconductor device shown in this figure is identical with the manufacture method of the semiconductor device of the 1st execution mode.
In the present embodiment, identical with the 1st execution mode when will go between (not shown) is connected on the Al alloy pad 11 that is positioned at opening portion 13a when by terminal conjunction method, the Al alloy that forms Al alloy pad 11 can flow to the bight of Al alloy pad 11.But the flowability of Al alloy is absorbed by the distortion of patterns of openings 12.
Therefore, compared with the past, according to present embodiment, the Al alloy that can suppress to flow concentrates on the bight of Al alloy pad 11.Thereby, can obtain the effect identical with the 1st execution mode.
Fig. 6 is the vertical view of structure that is used to illustrate the semiconductor device of the 4th execution mode, and it is equivalent to the Fig. 3 (B) in the 1st execution mode.Semiconductor device shown in this figure except the shape of the patterns of openings 12 in the bight that is formed on Al alloy pad 11, has the structure identical with the 1st execution mode.And the manufacture method of the semiconductor device shown in this figure is identical with the manufacture method of the semiconductor device of the 1st execution mode.Below, give identical symbol for the structure identical, and omit its explanation with the 1st execution mode.
In the present embodiment, patterns of openings 12 has: the slit 12a that extends towards central part from the angle of Al alloy pad 11 and respectively with 2 road slit 12b of 2 limit configured in parallel that form the angle.In each end of slit 12a, 12b, the end of angle side that is positioned at Al alloy pad 11 is close mutually.
According to present embodiment, also can access effect and the effect identical with the 1st execution mode.
Fig. 7 is the vertical view of structure that is used to illustrate the semiconductor device of the 5th execution mode, and it is equivalent to the Fig. 3 (B) in the 1st execution mode.Semiconductor device shown in this figure except the shape of the patterns of openings 12 in the bight that is formed on Al alloy pad 11, has the structure identical with the 4th execution mode.And the manufacture method of the semiconductor device shown in this figure is identical with the manufacture method of the semiconductor device of the 4th execution mode.Below, give identical symbol for the structure identical, and omit its explanation with the 4th execution mode.
In the present embodiment, among slit 12a, the 12b of patterns of openings 12, the end of center side that is positioned at Al alloy pad 11 is close mutually.
According to present embodiment, also can access effect and the effect identical with the 4th execution mode.
Fig. 8 is the vertical view of structure that is used to illustrate the semiconductor device of the 6th execution mode, and it is equivalent to the Fig. 3 (B) in the 1st execution mode.Semiconductor device shown in this figure, except the patterns of openings 12 of the roughly L word shape in the bight that is formed on Al alloy pad 11, each bight by the multiple configuration this point outside, have the structure identical with the 1st execution mode.It is littler than the patterns of openings 12 that disposes side outside to be configured in inboard patterns of openings 12.And the manufacture method of the semiconductor device in the manufacture method of the semiconductor device shown in this figure and the 1st execution mode is identical.Below, give identical symbol for the structure identical, and omit its explanation with the 1st execution mode.
According to present embodiment, also can access effect and the effect identical with the 1st execution mode.
Fig. 9 is the vertical view of structure that is used to illustrate the semiconductor device of the 7th execution mode, and it is equivalent to the Fig. 3 (B) in the 1st execution mode.Semiconductor device shown in this figure except the shape of the patterns of openings 12 in each bight of being formed on Al alloy pad 11, has the structure identical with the 1st execution mode.And the manufacture method of the semiconductor device in the manufacture method of the semiconductor device shown in this figure and the 1st execution mode is identical.Below, give identical symbol for the structure identical, and omit its explanation with the 1st execution mode.
In the present embodiment, patterns of openings 12 is shape of slit, and extends to the central authorities of Al alloy pad 11 from each of 4 bights of Al alloy pad 11.The inside of the bight side of each patterns of openings 12 is passivated film 13 and imbeds, and its central portion side is exposed in the inside of opening portion 13a.
In the present embodiment, identical with the 1st execution mode when will go between (not shown) joins on the Al alloy pad 11 that is positioned at opening portion 13a, the Al alloy that forms Al alloy pad 11 can flow to the bight of Al alloy pad 11.But the flowability of Al alloy is absorbed by the distortion of the patterns of openings 12 exposed in opening portion 13a inside.And the Al alloy that has flowed is embedded in the passivating film 13 of patterns of openings 12 inside and blocks, and described patterns of openings 12 is positioned at the bight side.
Therefore, according to present embodiment, also can access the effect identical with the 1st execution mode.
Figure 10 (A) is the cutaway view of structure that is used to illustrate the semiconductor device of the 8th execution mode, and Figure 10 (B) is the vertical view of the semiconductor device shown in Figure 10 (A).This figure is equivalent to the Fig. 3 in the 1st execution mode.Semiconductor device shown in this figure except the central portion at Al alloy pad 11 is formed with opening portion 20 this point, has the structure identical with the 1st execution mode.And the manufacture method of the semiconductor device shown in this figure is identical with the manufacture method of the semiconductor device of the 1st execution mode.Below, give identical symbol for the structure identical, and omit its explanation with the 1st execution mode.
According to this semiconductor device, by the effect identical with the 1st execution mode, compared with the past the diminishing of stress that produces in the bight of Al alloy pad 11.And, owing to be formed with opening portion 20 at the central portion of Al alloy pad 11, so, the amount of the Al alloy that when wire-bonded, flows can be reduced.Thereby the stress that produces in the bight of Al alloy pad 11 can further diminish.
Therefore, can be suppressed on the 2nd interlayer dielectric 10 and to produce be full of cracks etc.And, can suppress to be positioned at the transistor of Al alloy pad 11 belows and the destruction of polysilicon resistance 4b.And, can suppress the variation of the characteristic of the transistor that causes by stress and polysilicon resistance 4b.
Each figure of Figure 11 is the cutaway view of manufacture method that is used to illustrate the semiconductor device of the 9th execution mode.According to the semiconductor device that present embodiment is made, Al alloy pad is a double-decker.Below, give identical symbol for the structure identical, and omit its explanation with the 1st execution mode.
At first, shown in Figure 11 (A), on silicon substrate 1, form element isolation film 2.Then, form grid oxidation film 3, gate electrode 4a, polysilicon resistance 4b, sidewall 5, low concentration impurity zone 6a and 6b, extrinsic region 7a and 7b, the 1st interlayer dielectric 8, connecting hole 8a and 8b, Al alloy wiring 9a and 9b, the 2nd interlayer dielectric 10 and Al alloy pad 11.Al alloy pad 11 is provided with patterns of openings 12.These formation method is identical with the 1st execution mode.
Then, shown in Figure 11 (B), forming the 3rd interlayer dielectric 14 on the 2nd interlayer dielectric 10 and on the Al alloy pad 11.At this moment, imbed the 3rd interlayer dielectric 14 in the inside of patterns of openings 12.In addition, the structure of the 3rd interlayer dielectric 14 and formation method are identical with the structure formation method of the 1st interlayer dielectric 8.
Then, on the 3rd interlayer dielectric 14, apply photoresist film (not shown), and the exposure, this photoresist film develops.Thus, on the 3rd interlayer dielectric 14, formed corrosion-resisting pattern.Then, this corrosion-resisting pattern is come etching the 3rd interlayer dielectric 14 as mask.Thus, forming the opening portion 14a that is positioned on the Al alloy pad 11 on the 3rd interlayer dielectric 14.In addition, the patterns of openings 12 that is positioned at the bight of Al alloy pad 11 is kept the state that is covered by the 3rd interlayer dielectric 14.
Then, on the 3rd interlayer dielectric 14 He in the opening portion 14a, formed the Al alloy film by sputtering method.Then, on the Al alloy film, apply photoresist film (not shown), and the exposure, this photoresist film develops.Thus, on the Al alloy film, formed corrosion-resisting pattern.Then, this corrosion-resisting pattern is come etching Al alloy film as mask.Thus, on the 3rd interlayer dielectric 14, formed 2Al alloy pad 15.Be embedded in the opening portion 14a by the bottom, 2Al alloy pad 15 is connected with Al alloy pad 11.
Then, form passivating film 13 on the 3rd interlayer dielectric 14 and on the 2Al alloy pad 15, on 2Al alloy pad 15, forming opening portion 13a.These formation method is identical with the 1st execution mode.
Then, be positioned at bonding wire (not shown) on the 2Al alloy pad 15 of opening portion 13a.At this moment, can apply power, make the Al alloy that forms Al alloy pad 11 flow to 4 bights to Al alloy pad 11.But, owing to imbedded passivating film 13 in the inside of the patterns of openings 12 in bight, so the part of the Al alloy that flows is blocked by patterns of openings 12.Thereby, compared with the past, can suppress the bight that the Al alloy concentrates on Al alloy pad 11.
Therefore, according to present embodiment, diminish in the stress that the bight the produced meeting compared with the past of Al alloy pad 11.Thus, can access the effect identical with the 1st execution mode.And, be placed in the atmosphere owing to can suppress the 2nd interlayer dielectric 10, so, the decline of semiconductor device moisture-proof can be suppressed.
Figure 12 is the cutaway view of structure that is used to illustrate the semiconductor device of the 10th execution mode.The semiconductor device of present embodiment except not forming patterns of openings 12 and do not form the patterns of openings 16 on 2Al alloy pad 15 on Al alloy pad 11, has and the identical structure of semiconductor device that forms by the 9th execution mode.And the manufacture method of the semiconductor device shown in this figure is identical with the 9th execution mode.Patterns of openings 16 forms (patterning) by the pattern that is used to form 2Al alloy pad 15 and forms.Below, give identical symbol for the structure identical, and omit its explanation with the 9th execution mode.
The flat shape of patterns of openings 16 is roughly the L word shape, and the flat shape of the patterns of openings 12 in itself and the 9th execution mode is roughly the same.But patterns of openings 16 is positioned at the opening portion 13a of passivating film 13, and, be positioned at the inboard of the opening portion 14a of the 3rd interlayer dielectric 14.
According to present embodiment, even form the Al alloy flow of 2Al alloy pad 15, its flowability also can be absorbed by patterns of openings 16.Thereby, also can access the effect identical with the 1st execution mode according to present embodiment.
Figure 13 is the cutaway view of structure that is used to illustrate the semiconductor device of the 11st execution mode.The semiconductor device of present embodiment, except being formed with on the Al alloy pad 11 patterns of openings 12, the identical structure of semiconductor device that has and form by the 10th execution mode.And the manufacture method of the semiconductor device shown in this figure is identical with the 10th execution mode.Below, give identical symbol for the structure identical, and omit its explanation with the 9th execution mode.
According to present embodiment, can access the both sides that reach in the effect shown in the 10th execution mode in the effect shown in the 9th execution mode.Thereby, can access the effect identical with the 1st execution mode.
In addition, the present invention is not limited to above-mentioned execution mode, can implement various changes in the scope that does not break away from purport of the present invention.For example, in each above-mentioned execution mode, also a plurality of opening portions of circle or polygon can be configured to slit-shaped and form patterns of openings.And, can also be on whole of Al alloy pad 11 or be arranged to rectangular on the periphery with the opening portion of circle or polygon.
In addition, in each execution mode of the 9th～the 11st, can on the 3rd interlayer dielectric 14, opening portion 14a be set yet, form a plurality of connecting holes that are positioned on the Al alloy pad 11 on the 3rd interlayer dielectric 14.In this case, also can in each hole of a plurality of connecting holes, imbed the tungsten inserting column.
And, in each above-mentioned execution mode,, but forming on the Al alloy pad under the situation of projection when bonding wire not on Al alloy pad, owing to, can make the Al alloy that forms Al alloy pad flow to periphery with the pushing force of projection when being pressed on other substrates.But,,, diminish in the bight of Al alloy pad or the stress meeting compared with the past that periphery produced by the effect identical with above-mentioned execution mode even in this case.Therefore, can access the effect identical with above-mentioned execution mode.
Claims (2)
1, a kind of semiconductor device has:
Be positioned on the semiconductor element or the dielectric film of top;
Be formed on the electric conductor pad on the described dielectric film, the flat shape of described electric conductor pad is a polygonal, and has the patterns of openings of the shape of slit of extending from the bight of the described electric conductor pad of the mediad of described electric conductor pad; With
Diaphragm, it is formed on the described dielectric film and on the described electric conductor pad, and has peristome on described electric conductor pad,
Imbed the part of described diaphragm in the part 1 of described patterns of openings, the part 2 of described patterns of openings is formed in the described peristome of described diaphragm.
2, a kind of manufacture method of semiconductor device has:
On the semiconductor element or above form the operation of dielectric film;
On described dielectric film, form the operation of electric conductor film;
Form described electric conductor film by pattern, form the operation of electric conductor pad and patterns of openings, described electric conductor pad is positioned at that the top of described semiconductor element and its are plane to be polygonal, described patterns of openings is positioned at described electric conductor pad, and it is the shape of slit of extending to the bight of described electric conductor pad from the central portion of described electric conductor pad; With,
In the operation that forms diaphragm on the described dielectric film and on the described electric conductor pad,
In forming the operation of described diaphragm, imbed the part of described diaphragm in the part 1 of described opening figure, and with on the described electric conductor pad and the mode that has peristome on the part 2 of described opening figure form described diaphragm.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005162325A JP4533804B2 (en) | 2005-06-02 | 2005-06-02 | Semiconductor device and manufacturing method thereof |
| JP2005162325 | 2005-06-02 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1873963A CN1873963A (en) | 2006-12-06 |
| CN100456463C true CN100456463C (en) | 2009-01-28 |
Family
ID=37484341
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006100771739A Expired - Fee Related CN100456463C (en) | 2005-06-02 | 2006-04-27 | Semiconductor device and method of manufacturing a semiconductor device |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US7514790B2 (en) |
| JP (1) | JP4533804B2 (en) |
| CN (1) | CN100456463C (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5452064B2 (en) * | 2009-04-16 | 2014-03-26 | ルネサスエレクトロニクス株式会社 | Semiconductor integrated circuit device |
| CN102208387B (en) * | 2010-03-30 | 2013-05-22 | 曹用信 | Circuit board for being connected with ball grid array packaging assembly and method for forming bonding pad structure |
| US8836150B2 (en) * | 2010-11-29 | 2014-09-16 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device |
| US9548280B2 (en) * | 2014-04-02 | 2017-01-17 | Nxp Usa, Inc. | Solder pad for semiconductor device package |
| JP6493665B2 (en) * | 2015-03-13 | 2019-04-03 | セイコーエプソン株式会社 | MEMS device, liquid ejecting head, and liquid ejecting apparatus |
| JP2018026451A (en) * | 2016-08-10 | 2018-02-15 | エスアイアイ・セミコンダクタ株式会社 | Semiconductor device |
| US10304782B2 (en) * | 2017-08-25 | 2019-05-28 | Infineon Technologies Ag | Compressive interlayer having a defined crack-stop edge extension |
| JP7140314B2 (en) * | 2018-09-05 | 2022-09-21 | 住友電工デバイス・イノベーション株式会社 | semiconductor equipment |
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| JPH05226339A (en) * | 1992-01-28 | 1993-09-03 | Nec Corp | Resin sealed semiconductor device |
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- 2006-04-27 CN CNB2006100771739A patent/CN100456463C/en not_active Expired - Fee Related
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| JPH11330121A (en) * | 1998-05-14 | 1999-11-30 | Sanyo Electric Co Ltd | Semiconductor device and its manufacture |
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Also Published As
| Publication number | Publication date |
|---|---|
| US7514790B2 (en) | 2009-04-07 |
| JP2006339408A (en) | 2006-12-14 |
| US20060273464A1 (en) | 2006-12-07 |
| JP4533804B2 (en) | 2010-09-01 |
| CN1873963A (en) | 2006-12-06 |
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