CN100447738C - 含有多级寄存器文件的数字数据处理设备 - Google Patents

含有多级寄存器文件的数字数据处理设备 Download PDF

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Publication number
CN100447738C
CN100447738C CNB2005100794172A CN200510079417A CN100447738C CN 100447738 C CN100447738 C CN 100447738C CN B2005100794172 A CNB2005100794172 A CN B2005100794172A CN 200510079417 A CN200510079417 A CN 200510079417A CN 100447738 C CN100447738 C CN 100447738C
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order
instruction
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CN1713137A (zh
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内森·S·纽纳马克
杰克·C·伦道夫
土屋宪一
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International Business Machines Corp
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30138—Extension of register space, e.g. register cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30123—Organisation of register space, e.g. banked or distributed register file according to context, e.g. thread buffers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/3013—Organisation of register space, e.g. banked or distributed register file according to data content, e.g. floating-point registers, address registers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3888—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple threads [SIMT] in parallel

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Mathematical Physics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
CNB2005100794172A 2004-06-24 2005-06-21 含有多级寄存器文件的数字数据处理设备 Expired - Fee Related CN100447738C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/875,373 2004-06-24
US10/875,373 US7284092B2 (en) 2004-06-24 2004-06-24 Digital data processing apparatus having multi-level register file

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CN1713137A CN1713137A (zh) 2005-12-28
CN100447738C true CN100447738C (zh) 2008-12-31

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JP (1) JP4829541B2 (https=)
CN (1) CN100447738C (https=)
TW (1) TW200609744A (https=)

Families Citing this family (74)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7263593B2 (en) 2002-11-25 2007-08-28 Hitachi, Ltd. Virtualization controller and data transfer control method
US7933405B2 (en) * 2005-04-08 2011-04-26 Icera Inc. Data access and permute unit
US7861060B1 (en) * 2005-12-15 2010-12-28 Nvidia Corporation Parallel data processing systems and methods using cooperative thread arrays and thread identifier values to determine processing behavior
US7788468B1 (en) 2005-12-15 2010-08-31 Nvidia Corporation Synchronization of threads in a cooperative thread array
US8327115B2 (en) 2006-04-12 2012-12-04 Soft Machines, Inc. Plural matrices of execution units for processing matrices of row dependent instructions in single clock cycle in super or separate mode
US9069547B2 (en) 2006-09-22 2015-06-30 Intel Corporation Instruction and logic for processing text strings
WO2008061154A2 (en) 2006-11-14 2008-05-22 Soft Machines, Inc. Apparatus and method for processing instructions in a multi-threaded architecture using context switching
US7797514B2 (en) * 2006-11-16 2010-09-14 Texas Instruments Incorporated Scalable multi-threaded sequencing/synchronizing processor architecture
US20080229062A1 (en) * 2007-03-12 2008-09-18 Lorenzo Di Gregorio Method of sharing registers in a processor and processor
US7937530B2 (en) * 2007-06-28 2011-05-03 International Business Machines Corporation Method and apparatus for accessing a cache with an effective address
US20090006753A1 (en) * 2007-06-28 2009-01-01 David Arnold Luick Design structure for accessing a cache with an effective address
US7877582B2 (en) * 2008-01-31 2011-01-25 International Business Machines Corporation Multi-addressable register file
US7849294B2 (en) * 2008-01-31 2010-12-07 International Business Machines Corporation Sharing data in internal and memory representations with dynamic data-driven conversion
US8176406B2 (en) * 2008-03-19 2012-05-08 International Business Machines Corporation Hard error detection
US8631223B2 (en) 2010-05-12 2014-01-14 International Business Machines Corporation Register file supporting transactional processing
US8914619B2 (en) * 2010-06-22 2014-12-16 International Business Machines Corporation High-word facility for extending the number of general purpose registers available to instructions
CN103250131B (zh) 2010-09-17 2015-12-16 索夫特机械公司 包括用于早期远分支预测的影子缓存的单周期多分支预测
US8661227B2 (en) * 2010-09-17 2014-02-25 International Business Machines Corporation Multi-level register file supporting multiple threads
US8725993B2 (en) * 2011-02-23 2014-05-13 International Business Machines Corporation Thread transition management
CN103562866B (zh) 2011-03-25 2018-03-30 英特尔公司 用于通过使用由可分割引擎实例化的虚拟核来支持代码块执行的寄存器文件段
KR101966712B1 (ko) 2011-03-25 2019-04-09 인텔 코포레이션 분할가능한 엔진에 의해 인스턴스화된 가상 코어를 이용한 코드 블록의 실행을 지원하는 메모리 프래그먼트
WO2012135031A2 (en) 2011-03-25 2012-10-04 Soft Machines, Inc. Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines
EP2710481B1 (en) 2011-05-20 2021-02-17 Intel Corporation Decentralized allocation of resources and interconnect structures to support the execution of instruction sequences by a plurality of engines
WO2012162189A1 (en) 2011-05-20 2012-11-29 Soft Machines, Inc. An interconnect structure to support the execution of instruction sequences by a plurality of engines
US8595460B2 (en) * 2011-08-26 2013-11-26 Vmware, Inc. Configuring object storage system for input/output operations
US9727336B2 (en) 2011-09-16 2017-08-08 International Business Machines Corporation Fine-grained instruction enablement at sub-function granularity based on an indicated subrange of registers
US9411585B2 (en) 2011-09-16 2016-08-09 International Business Machines Corporation Multi-addressable register files and format conversions associated therewith
US10078515B2 (en) 2011-10-03 2018-09-18 International Business Machines Corporation Tracking operand liveness information in a computer system and performing function based on the liveness information
US9697002B2 (en) 2011-10-03 2017-07-04 International Business Machines Corporation Computer instructions for activating and deactivating operands
US8756591B2 (en) 2011-10-03 2014-06-17 International Business Machines Corporation Generating compiled code that indicates register liveness
US9690583B2 (en) 2011-10-03 2017-06-27 International Business Machines Corporation Exploiting an architected list-use operand indication in a computer system operand resource pool
US8615745B2 (en) 2011-10-03 2013-12-24 International Business Machines Corporation Compiling code for an enhanced application binary interface (ABI) with decode time instruction optimization
US9329869B2 (en) 2011-10-03 2016-05-03 International Business Machines Corporation Prefix computer instruction for compatibily extending instruction functionality
US20130086364A1 (en) * 2011-10-03 2013-04-04 International Business Machines Corporation Managing a Register Cache Based on an Architected Computer Instruction Set Having Operand Last-User Information
US8612959B2 (en) 2011-10-03 2013-12-17 International Business Machines Corporation Linking code for an enhanced application binary interface (ABI) with decode time instruction optimization
US9286072B2 (en) 2011-10-03 2016-03-15 International Business Machines Corporation Using register last use infomation to perform decode-time computer instruction optimization
US9354874B2 (en) 2011-10-03 2016-05-31 International Business Machines Corporation Scalable decode-time instruction sequence optimization of dependent instructions
WO2013077876A1 (en) 2011-11-22 2013-05-30 Soft Machines, Inc. A microprocessor accelerated code optimizer
IN2014CN03678A (https=) 2011-11-22 2015-09-25 Soft Machines Inc
WO2013095599A1 (en) * 2011-12-23 2013-06-27 Intel Corporation Systems, apparatuses, and methods for performing a double blocked sum of absolute differences
US9286068B2 (en) 2012-10-31 2016-03-15 International Business Machines Corporation Efficient usage of a multi-level register file utilizing a register file bypass
US10275251B2 (en) 2012-10-31 2019-04-30 International Business Machines Corporation Processor for avoiding reduced performance using instruction metadata to determine not to maintain a mapping of a logical register to a physical register in a first level register file
US9891924B2 (en) 2013-03-15 2018-02-13 Intel Corporation Method for implementing a reduced size register view data structure in a microprocessor
US10140138B2 (en) 2013-03-15 2018-11-27 Intel Corporation Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation
US9886279B2 (en) 2013-03-15 2018-02-06 Intel Corporation Method for populating and instruction view data structure by using register template snapshots
WO2014150806A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for populating register view data structure by using register template snapshots
US9811342B2 (en) 2013-03-15 2017-11-07 Intel Corporation Method for performing dual dispatch of blocks and half blocks
US10275255B2 (en) 2013-03-15 2019-04-30 Intel Corporation Method for dependency broadcasting through a source organized source view data structure
WO2014150991A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for implementing a reduced size register view data structure in a microprocessor
WO2014150971A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for dependency broadcasting through a block organized source view data structure
EP2972836B1 (en) 2013-03-15 2022-11-09 Intel Corporation A method for emulating a guest centralized flag architecture by using a native distributed flag architecture
US9569216B2 (en) 2013-03-15 2017-02-14 Soft Machines, Inc. Method for populating a source view data structure by using register template snapshots
US9904625B2 (en) 2013-03-15 2018-02-27 Intel Corporation Methods, systems and apparatus for predicting the way of a set associative cache
WO2014151018A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for executing multithreaded instructions grouped onto blocks
US9508112B2 (en) * 2013-07-31 2016-11-29 Apple Inc. Multi-threaded GPU pipeline
US9378146B2 (en) * 2013-08-20 2016-06-28 Apple Inc. Operand cache design
US9459869B2 (en) 2013-08-20 2016-10-04 Apple Inc. Intelligent caching for an operand cache
US9652233B2 (en) 2013-08-20 2017-05-16 Apple Inc. Hint values for use with an operand cache
US9870340B2 (en) * 2015-03-30 2018-01-16 International Business Machines Corporation Multithreading in vector processors
US9952865B2 (en) * 2015-04-04 2018-04-24 Texas Instruments Incorporated Low energy accelerator processor architecture with short parallel instruction word and non-orthogonal register data file
US9619394B2 (en) 2015-07-21 2017-04-11 Apple Inc. Operand cache flush, eviction, and clean techniques using hint information and dirty information
US9785567B2 (en) 2015-09-11 2017-10-10 Apple Inc. Operand cache control techniques
US10241790B2 (en) 2015-12-15 2019-03-26 International Business Machines Corporation Operation of a multi-slice processor with reduced flush and restore latency
US20170371654A1 (en) * 2016-06-23 2017-12-28 Advanced Micro Devices, Inc. System and method for using virtual vector register files
GB2552154B (en) * 2016-07-08 2019-03-06 Advanced Risc Mach Ltd Vector register access
US10613987B2 (en) 2016-09-23 2020-04-07 Apple Inc. Operand cache coherence for SIMD processor supporting predication
US10423415B2 (en) * 2017-04-01 2019-09-24 Intel Corporation Hierarchical general register file (GRF) for execution block
CN111951845B (zh) * 2019-05-15 2022-06-03 上海磁宇信息科技有限公司 一种分级管理冗余存储的mram芯片
US11848980B2 (en) * 2020-07-09 2023-12-19 Boray Data Technology Co. Ltd. Distributed pipeline configuration in a distributed computing system
TWI783310B (zh) * 2020-11-26 2022-11-11 華邦電子股份有限公司 計數方法以及計數裝置
CN112817639B (zh) * 2021-01-13 2022-04-08 中国民航大学 Gpu读写单元通过操作数收集器访问寄存器文件的方法
CN116560729B (zh) * 2023-05-11 2024-06-04 北京市合芯数字科技有限公司 一种多线程处理器的寄存器多级管理方法及系统
US20250130799A1 (en) * 2023-10-19 2025-04-24 Ampere Computing Llc Techniques for performing non-vector micro-operations on vector hardware
WO2026050037A1 (en) * 2024-08-29 2026-03-05 Microsemi SoC Corporation Vector processor performance enhancement

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5226142A (en) * 1990-11-21 1993-07-06 Ross Technology, Inc. High performance register file with overlapping windows
US5701507A (en) * 1991-12-26 1997-12-23 Texas Instruments Incorporated Architecture of a chip having multiple processors and multiple memories
US5721868A (en) * 1994-01-21 1998-02-24 Sun Microsystems, Inc. Rapid register file access by limiting access to a selectable register subset
US5974438A (en) * 1996-12-31 1999-10-26 Compaq Computer Corporation Scoreboard for cached multi-thread processes
US20040064680A1 (en) * 2002-09-26 2004-04-01 Sudarshan Kadambi Method and apparatus for reducing register file access times in pipelined processors

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4128880A (en) 1976-06-30 1978-12-05 Cray Research, Inc. Computer vector register processing
US5179681A (en) 1989-11-16 1993-01-12 Sun Microsystems, Inc. Method and apparatus for current window cache with switchable address and out cache registers
JPH06222990A (ja) * 1992-10-16 1994-08-12 Fujitsu Ltd データ処理装置
US5592679A (en) * 1994-11-14 1997-01-07 Sun Microsystems, Inc. Apparatus and method for distributed control in a processor architecture
EP0717359A3 (en) * 1994-12-15 1997-02-05 Sun Microsystems Inc Register cache memory for a computer processor
US6131155A (en) * 1997-11-07 2000-10-10 Pmc Sierra Ltd. Programmer-visible uncached load/store unit having burst capability
US6108770A (en) * 1998-06-24 2000-08-22 Digital Equipment Corporation Method and apparatus for predicting memory dependence using store sets
US6381678B2 (en) * 1998-10-30 2002-04-30 Intel Corporation Processing ordered data requests to a memory
US6282614B1 (en) * 1999-04-15 2001-08-28 National Semiconductor Corporation Apparatus and method for reducing the power consumption of a microprocessor with multiple levels of caches
US6557078B1 (en) * 2000-02-21 2003-04-29 Hewlett Packard Development Company, L.P. Cache chain structure to implement high bandwidth low latency cache memory subsystem
EP1275046B1 (en) * 2000-04-12 2010-10-06 DSP Group Switzerland AG Data processing circuit with a cache memory and apparatus containing such a circuit
JP3659941B2 (ja) * 2002-07-26 2005-06-15 インターナショナル・ビジネス・マシーンズ・コーポレーション マイクロプロセッサおよびその処理方法
US20040222379A1 (en) * 2003-05-09 2004-11-11 Cook Michael Joseph Event counter for an imaging device
US7206923B2 (en) * 2003-12-12 2007-04-17 International Business Machines Corporation Method and apparatus for eliminating the need for register assignment, allocation, spilling and re-filling
US20050138297A1 (en) * 2003-12-23 2005-06-23 Intel Corporation Register file cache
US7694075B1 (en) * 2005-03-09 2010-04-06 Globalfoundries Inc. System for enabling and disabling cache and a method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5226142A (en) * 1990-11-21 1993-07-06 Ross Technology, Inc. High performance register file with overlapping windows
US5701507A (en) * 1991-12-26 1997-12-23 Texas Instruments Incorporated Architecture of a chip having multiple processors and multiple memories
US5721868A (en) * 1994-01-21 1998-02-24 Sun Microsystems, Inc. Rapid register file access by limiting access to a selectable register subset
US5974438A (en) * 1996-12-31 1999-10-26 Compaq Computer Corporation Scoreboard for cached multi-thread processes
US20040064680A1 (en) * 2002-09-26 2004-04-01 Sudarshan Kadambi Method and apparatus for reducing register file access times in pipelined processors

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JP4829541B2 (ja) 2011-12-07
JP2006012163A (ja) 2006-01-12
CN1713137A (zh) 2005-12-28
TW200609744A (en) 2006-03-16
US20050289299A1 (en) 2005-12-29
US8793433B2 (en) 2014-07-29
US20080022044A1 (en) 2008-01-24
US7284092B2 (en) 2007-10-16

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