CN100444355C - Thin film transistor array base plate and its manufacturing method - Google Patents
Thin film transistor array base plate and its manufacturing method Download PDFInfo
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- CN100444355C CN100444355C CNB2006101694852A CN200610169485A CN100444355C CN 100444355 C CN100444355 C CN 100444355C CN B2006101694852 A CNB2006101694852 A CN B2006101694852A CN 200610169485 A CN200610169485 A CN 200610169485A CN 100444355 C CN100444355 C CN 100444355C
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Abstract
This invention provides one film transistor array base board and its process method, wherein, the film transistor array baseboard comprises baseboard, pattern first metal layer, pattern semiconductor layer, pattern transparent conductive layer and insulation layer and second metal layer, wherein, each parts of transistor are distributed by space with high conductive current; in other side, the common align and second metal layers comprises transparent electrode or second metal layer to increase memory capacitor energy to reduce pixel flash due to signal coupling to improve image quality.
Description
Technical field
The invention relates to a kind of thin-film transistor array base-plate and manufacture method thereof, and particularly relevant for a kind of thin-film transistor (thin film transistor, thin-film transistor array base-plate TFT) and manufacture method thereof (THIN FILM TRANSISTOR ARRAYSUBSTRATE AND FABRICATING METHOD THEREOF) with high conducting electric current.
Background technology
Thin-film transistor is widely used in the control circuit signal, also uses input that TFT comes control signal whether in the technical field of flat-panel screens, and the storage capacitors of arranging in pairs or groups simultaneously is promoted to active drive to improve display quality with passive driving.
During the design pixel electrode,, also need avoid coupling mutually between signal except considering effectively to bring into play the component characteristic.Particularly,, to get well, also avoid signal to be coupled mutually during design as far as possible, can promote display quality except assembly discharges and recharges character because the renewal frequency of picture is higher in order to view and admire the display of dynamic program.
Figure 1 shows that the condenser network schematic diagram of existing Thin Film Transistor-LCD.Figure 2 shows that the voltage oscillogram of existing Thin Film Transistor-LCD.
Please be simultaneously with reference to Fig. 1 and Fig. 2, because the change in voltage on the transistor (mainly being that scan wiring voltage 10 changes) can produce feedback via parasitic capacitance (parasitical capacitor) (being mainly gate-to-drain parasitic capacitance Cgd) and wear voltage (feed through voltage), and causes show electrode voltage 20 to offset downward Δ V.Under desirable situation, share voltage (common voltage) 30 can be adjusted Δ V downwards to share voltage 40, can compensate by feedback and wear the pressure reduction that voltage causes, or can increase storage capacitors Cs to improve Δ V because of intercoupling between signal and being caused.
Yet, increases the lifting that TFT discharges and recharges usefulness of also must arranging in pairs or groups of storage capacitors value and just can bring into play its advantage, otherwise storage capacitors can't be charged to the current potential of expectation in special time, and cause each GTG correctly to show.
Summary of the invention
In view of this, purpose of the present invention just provides a kind of thin-film transistor array base-plate, and it has less making area.
Another object of the present invention just provides a kind of thin-film transistor array base-plate, and it has high conducting electric current.
Another purpose of the present invention just provides a kind of manufacture method of thin-film transistor array base-plate, can strengthen the storage capacitors value.
A further object of the present invention just provides a kind of thin-film transistor array base-plate, and it can reduce the pixel that is caused because of the mutual coupling of signal and flash.
The present invention proposes a kind of manufacture method of thin-film transistor array base-plate, and a substrate at first is provided.Then, on substrate, form the patterning the first metal layer, to define many shared wiring, plurality of scanning wirings and many source electrode patterns, wherein scan wiring and source electrode pattern define a plurality of pixel regions on substrate, shared wiring is respectively by pairing pixel region and be parallel to scan wiring, and each source electrode pattern is adjacent to and extends a protuberance on the position of pairing scan wiring respectively to pairing pixel region, with respectively as source electrode.Then, on substrate, form patterned semiconductor layer, define second semiconductor pattern to define on first semiconductor pattern and the shared wiring in each pixel region on the source electrode in each pixel region respectively, and second semiconductor pattern has first opening that exposes shared wiring.Next, on substrate, form patterned transparent conductive layer, to define a pixel electrode in each pixel region, wherein each pixel electrode covers pairing first semiconductor pattern and second semiconductor pattern, and each pixel electrode has second opening corresponding to first opening.Afterwards, on substrate, form patterned insulation layer, above each shared wiring, to define first insulating pattern, and define second insulating pattern at the bearing of trend of each source electrode pattern and the intersection of pairing scan wiring, each first insulating pattern has the 3rd opening corresponding to second opening, and each second insulating pattern extends first semiconductor pattern and the pixel electrode that covers pairing source electrode and source electrode top.Then, on substrate, form patterning second metal level, to define many data wirings, a plurality of grid and a plurality of metal electrode, wherein each data wiring is respectively along the bearing of trend of pairing source electrode pattern and be disposed on the source electrode pattern, each grid is disposed at respectively on second insulating pattern of pairing source electrode top, and extension connects scan wiring, each metal electrode is disposed on the first interior insulating pattern of pairing pixel region, and is electrically connected to pairing shared wiring via the 3rd opening, second opening and first opening.
In one embodiment of this invention, when forming semiconductor layer, more comprise respectively forming ohmic contact layer in the both sides up and down of semiconductor layer.
In one embodiment of this invention, the method for formation ohmic contact layer comprises ion doping.
In one embodiment of this invention, when forming semiconductor layer, more be included on the intersection of the bearing of trend of source electrode pattern and scan wiring and shared wiring and define the 3rd semiconductor pattern respectively, and make second insulating pattern of follow-up formation cover pairing the 3rd semiconductor pattern respectively.
The present invention proposes a kind of thin-film transistor array base-plate, comprises substrate, patterning the first metal layer, patterned semiconductor layer, patterned transparent conductive layer, patterned insulation layer and patterning second metal level.The patterning the first metal layer, it is disposed on the substrate, comprise many shared wiring, plurality of scanning wirings and many source electrode patterns, wherein scan wiring and source electrode pattern define a plurality of pixel regions on substrate, shared wiring is respectively by pairing pixel region and be parallel to scan wiring, and each source electrode pattern is adjacent to and extends a protuberance on the position of pairing scan wiring respectively to pairing pixel region, with respectively as source electrode.Patterned semiconductor layer, it is disposed on patterning the first metal layer and the substrate, comprise a plurality of first semiconductor patterns and many second semiconductor patterns, wherein first semiconductor pattern is disposed on the interior source electrode of each pixel region, and second semiconductor pattern be disposed on the shared wiring in each pixel region, and second semiconductor pattern has first opening that exposes shared wiring.Patterned transparent conductive layer, in order to define pixel electrode in each pixel region, wherein each pixel electrode covers pairing first semiconductor pattern and second semiconductor pattern, and each pixel electrode has second opening corresponding to first opening.Patterned insulation layer, it is disposed on the substrate, comprise a plurality of first insulating patterns and many second insulating patterns, wherein first insulating pattern is disposed at each shared wiring top, and each first insulating pattern has the 3rd opening corresponding to second opening, and second insulating pattern be disposed at the intersection of bearing of trend and pairing this scan wiring of each source electrode pattern, and each second insulating pattern extends first semiconductor pattern and the pixel electrode that covers pairing source electrode and source electrode top.Patterning second metal level, it is disposed on the substrate, comprise many data wirings, a plurality of grid and a plurality of metal electrode, wherein each data wiring is respectively along the bearing of trend of pairing source electrode pattern and be disposed on the source electrode pattern, each grid is disposed at respectively on second insulating pattern of pairing source electrode top, and extension connects scan wiring, each metal electrode is disposed on the first interior insulating pattern of pairing pixel region, and is electrically connected to pairing shared wiring via the 3rd opening, second opening and first opening.
In one embodiment of this invention, the both sides up and down of semiconductor layer have ohmic contact layer respectively.
In one embodiment of this invention, the material of ohmic contact layer comprises doped amorphous silicon.
In one embodiment of this invention, the material of transparency conducting layer is indium tin oxide or indium-zinc oxide.
In one embodiment of this invention, the first metal layer is to be formed by stacking by multiple layer metal.
In one embodiment of this invention, patterned semiconductor layer more comprises the 3rd semiconductor pattern on the intersection of the bearing of trend that is arranged on the source electrode pattern and scan wiring and shared wiring, and second insulating pattern covers pairing the 3rd semiconductor pattern respectively.
The present invention proposes a kind of manufacture method of thin-film transistor array base-plate, and a substrate at first is provided, and then forms a first metal layer, semi-conductor layer and one second metal level on substrate in regular turn.Then, patterning second metal level, semiconductor layer and the first metal layer, the first metal layer is defined as many shared wiring, plurality of scanning wirings and many source electrode patterns, wherein scan wiring and source electrode pattern define a plurality of pixel regions on substrate, shared wiring is respectively by pairing pixel region and be parallel to scan wiring, and each source electrode pattern is adjacent to and extends a protuberance on the position of pairing scan wiring respectively to pairing pixel region, with respectively as source electrode, simultaneously in each pixel region, second metal level and semiconductor layer are defined as the first storehouse pattern that is disposed on the pairing source electrode, be disposed at the second storehouse pattern on the shared wiring, and the second storehouse pattern has first opening that exposes shared wiring, and be disposed on the scan wiring with the bearing of trend intersection of source electrode pattern and the 3rd storehouse pattern on the shared wiring.Next, on substrate, form patterned insulation layer, to define second opening above first opening in each pixel region corresponding to first opening, define the 3rd opening that exposes the part first storehouse pattern above the first storehouse pattern in each pixel region, define a plurality of the 4th openings that expose the part second storehouse pattern above the second storehouse pattern both sides in each pixel region, scan wiring in each pixel region defines the 5th opening that exposes the part scan wiring near above the side of source electrode, and define a plurality of the 6th openings that expose part source electrode pattern and part the 3rd storehouse pattern above above the source electrode pattern both sides in each pixel region and the 3rd storehouse pattern both sides respectively.Afterwards, on patterned insulation layer, form patterned transparent conductive layer, define two pixel electrodes with the shared wiring both sides in each pixel region, pixel electrode is electrically connected to the second storehouse pattern via these the 4th openings, one of them pixel electrode is electrically connected to the first storehouse pattern via the 3rd opening, define first transparency electrode above the second storehouse pattern in each pixel region, first transparency electrode is electrically connected to shared wiring via second opening and first opening, form grid above the source electrode in each pixel region, grid is electrically connected to scan wiring via the 5th opening, and defining a plurality of second transparency electrodes in the bearing of trend of source electrode pattern and shared wiring and scan wiring confluce, second transparency electrode electrically connects source electrode pattern and the 3rd storehouse pattern via the 6th opening.Next, on substrate, form patterning the 3rd metal level, to define many data wirings, wherein each bar data wiring is disposed at above the source electrode pattern along the bearing of trend of pairing source electrode pattern respectively, and electrically connects with pairing second transparency electrode.
The present invention proposes a kind of thin-film transistor array base-plate, comprises substrate, patterning the first metal layer, patterning stack layer, patterned insulation layer, patterned transparent conductive layer and patterning the 3rd metal level.The patterning the first metal layer, be disposed on the substrate, comprise many shared wiring, plurality of scanning wirings and many source electrode patterns, wherein scan wiring and source electrode pattern define a plurality of pixel regions on substrate, shared wiring is respectively by pairing pixel region and be parallel to scan wiring, and each source electrode pattern is adjacent to and extends a protuberance on the position of pairing scan wiring respectively to pairing pixel region, with respectively as source electrode.The patterning stack layer, from bottom to top be the semiconductor layer and second metal level in regular turn, be disposed on patterning the first metal layer and this substrate, comprise a plurality of first storehouse patterns, a plurality of second storehouse pattern and a plurality of the 3rd storehouse pattern, wherein the first storehouse pattern arrangement is in each pixel region on the pairing source electrode, the second storehouse pattern arrangement is on shared wiring, and the second storehouse pattern has first opening that exposes shared wiring, and the 3rd storehouse pattern arrangement in the scan wiring of the bearing of trend intersection of source electrode pattern on and on the shared wiring.Patterned insulation layer, be disposed on the substrate, have a plurality of second openings, a plurality of the 3rd openings, a plurality of the 4th openings, a plurality of the 5th openings, and a plurality of the 6th openings, wherein above first opening of the second opening position in each pixel region and corresponding to first opening, the 3rd opening is arranged in the first storehouse pattern top of each pixel region and exposes the part first storehouse pattern, the 4th opening is arranged in the top, the second storehouse pattern both sides of each pixel region and exposes the part second storehouse pattern, the scan wiring that the 5th opening is arranged in each pixel region is near the side top of source electrode and expose the part scan wiring, and the 6th opening be arranged in the source electrode pattern both sides tops and the top, the 3rd storehouse pattern both sides of each pixel region and expose part source electrode pattern and part the 3rd storehouse pattern.Patterned transparent conductive layer is configured on patterned insulation layer and the substrate, define two pixel electrodes in order to the shared wiring both sides in each pixel region, pixel electrode is electrically connected to the second storehouse pattern via the 4th opening, one of them pixel electrode is electrically connected to the first storehouse pattern via the 3rd opening, has first transparency electrode above the second storehouse pattern in each pixel region, first transparency electrode is electrically connected to shared wiring via second opening and first opening, form grid above the source electrode in each pixel region, grid is electrically connected to scan wiring via the 5th opening, and having a plurality of second transparency electrodes in the bearing of trend of source electrode pattern and shared wiring and scan wiring confluce, second transparency electrode electrically connects source electrode pattern and the 3rd storehouse pattern via the 6th opening.Patterning the 3rd metal level, it is configured on the substrate, comprises many data wirings, and wherein each bar data wiring is disposed at above the source electrode pattern along the bearing of trend of pairing source electrode pattern respectively, and electrically connects with pairing second transparency electrode.
Based on above-mentioned, in the thin-film transistor array base-plate of manufacturing of the present invention, each member of TFT is uprightly arranged, and therefore has less making face machine and high conducting electric current.
On the other hand, in the thin-film transistor array base-plate of manufacturing of the present invention, can increase storage capacitors value energy by shared wiring and the second metal level double team transparency electrode or by shared wiring and transparency electrode double team second metal level, flash to reduce the pixel that is caused because of the mutual coupling of signal, and then promote picture quality.
In addition, the manufacture method of thin-film transistor array base-plate of the present invention can form ohmic contact layer respectively in both sides up and down at semiconductor layer, to avoid producing short channel effect.
Description of drawings
Figure 1 shows that the condenser network schematic diagram of existing Thin Film Transistor-LCD.
Figure 2 shows that the voltage oscillogram of existing Thin Film Transistor-LCD.
Fig. 3 A～Fig. 3 E is depicted as the manufacturing process profile of the thin-film transistor array base-plate of one embodiment of the invention.
Fig. 4 A～Fig. 4 E is depicted as the manufacturing process profile of A-A ' and B-B ' hatching in Fig. 3 A～Fig. 3 E.
Figure 5 shows that the profile of C-C ' hatching in Fig. 3 E.
Fig. 6 A～Fig. 6 C is depicted as the manufacturing process profile of the thin-film transistor array base-plate of another embodiment of the present invention.
Fig. 7 A～Fig. 7 C is depicted as the manufacturing process profile of A-A ' and B-B ' hatching in Fig. 6 A～Fig. 6 C.
The primary clustering symbol description
10: scan wiring voltage 20: show electrode voltage
30,40: share voltage 100,200: substrate
102,202: shared wiring 104,204: scan wiring
106,206: source electrode pattern 108,208: pixel region
110,210: source electrode 112: ohmic contact layer
116: the second semiconductor patterns of 114: the first semiconductor patterns
118,120: the three semiconductor patterns of 216: the first openings
122: ohmic contact layer 124,232: pixel electrode
126,128: the first insulating patterns of 222: the second openings
130: the second insulating patterns 132,224: the three openings
134: data wiring 136,236: grid
138: 212: the first storehouse patterns of metal electrode
218: the three storehouse patterns of 214: the second storehouse patterns
220: 226: the four openings of insulating barrier
230: the six openings of 228: the five openings
238: the second transparency electrodes of 234: the first transparency electrodes
240: data wiring Cgd: the gate-to-drain parasitic capacitance
Cs: storage capacitors
Embodiment
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Fig. 3 A～Fig. 3 E is depicted as the manufacturing process profile of the thin-film transistor array base-plate of one embodiment of the invention.Fig. 4 A～Fig. 4 E is depicted as the manufacturing process profile of A-A ' and B-B ' hatching in Fig. 3 A～Fig. 3 E.
At first, please provide a substrate 100 simultaneously with reference to Fig. 3 A and Fig. 4 A, substrate 100 for example is transparency carriers such as glass substrate.Then, on substrate 100, form the first metal layer (not shown) of patterning, to define many shared wiring 102 (shared wiring 102 only is shown) in Fig. 3 A, plurality of scanning wirings 104 (scan wiring 104 only is shown in Fig. 3 A) and many source electrode patterns 106, wherein scan wiring 104 defines a plurality of pixel regions 108 with source electrode pattern 106 on substrate 100, shared wiring 102 is respectively by pairing pixel region 108 and be parallel to scan wiring 104, and each source electrode pattern 106 is adjacent to and extends a protuberance on the position of pairing scan wiring 104 respectively to pairing pixel region 108, with respectively as source electrode 110.In addition, the first metal layer for example is to be made by the multiple layer metal stack, can avoid the first metal layer and adjacent each layer generation to peel off.The thickness of the first metal layer for example is 0.15 μ m～0.5 μ m, but not in order to limit the present invention, has in this technical field and know that usually the knowledgeable can adjust according to design requirement.
In addition, after forming the first metal layer and before the first metal layer is carried out patterning, can on the first metal layer, form ohmic contact layer 112, and ohmic contact layer 112 carries out the patterning manufacturing process with the first metal layer, so ohmic contact layer 112 can cover on shared wiring 102, scan wiring 104 and the source electrode pattern 106.The material of ohmic contact layer 112 for example is a doped amorphous silicon, and its formation method is for example also carried out ion doping synchronously with the chemical vapour deposition technique deposition of amorphous silicon and formed, and the kenel of ion doping for example is the heavy doping of N type.
Then, please be simultaneously with reference to Fig. 3 B and Fig. 4 B, on substrate 100, form the semiconductor layer (not shown) of patterning, define second semiconductor pattern 116 to define on first semiconductor pattern 114 and the shared wiring 102 in each pixel region 108 on the source electrode 110 in each pixel region 108 respectively, and second semiconductor pattern 116 has first opening 118 that exposes shared wiring 102.The thickness of semiconductor layer for example is 0.2 μ m～2 μ m, but not in order to limit the present invention, has in this technical field and know that usually the knowledgeable can adjust according to design requirement.
What deserves to be mentioned is, when forming semiconductor layer, more can on the intersection of the bearing of trend of source electrode pattern 106 and scan wiring 104 and shared wiring 102, define the 3rd semiconductor pattern 120 respectively.
In addition, after forming semiconductor layer and before semiconductor layer is carried out patterning, can on semiconductor layer, form ohmic contact layer 122.When semiconductor layer is carried out the patterning manufacturing process, while patterning ohmic contact layer 122 and 112.The material of ohmic contact layer 122 for example is a doped amorphous silicon, and its formation method is for example also carried out ion doping synchronously with the chemical vapour deposition technique deposition of amorphous silicon and formed, and the kenel of ion doping for example is the heavy doping of N type.
Next, please be simultaneously with reference to Fig. 3 C and Fig. 4 C, on substrate 100, form the transparency conducting layer of patterning, in each pixel region 108, to define a pixel electrode 124, wherein each pixel electrode 124 covers pairing first semiconductor pattern 114 and second semiconductor pattern 116, and each pixel electrode 124 has second opening 126 corresponding to first opening 118.The material of transparency conducting layer for example be indium tin oxide (indium tin oxide, ITO) or indium-zinc oxide (indium zinc oxide, IZO), its formation method for example is vapour deposition method or sputtering method.The thickness of transparency conducting layer for example is 0.1 μ m～0.5 μ m, but not in order to limit the present invention, has in this technical field and know that usually the knowledgeable can adjust according to design requirement.Transparency conducting layer directly is disposed on the semiconductor layer, can be used as drain electrode in TFT, can form electric capacity on shared wiring 102, and the storage capacitors value is provided.
Afterwards, please be simultaneously with reference to Fig. 3 D and Fig. 4 D, on substrate 100, form insulation layer patterned, above each shared wiring 102, to define first insulating pattern 128, and define second insulating pattern 130 at the bearing of trend of each source electrode pattern 106 and the intersection of pairing scan wiring 104, each first insulating pattern 128 has the 3rd opening 132 corresponding to second opening 126, and each second insulating pattern 130 extends first semiconductor pattern 114 that covers pairing source electrode 110 and source electrode 110 tops, pixel electrode 124 and pairing the 3rd semiconductor pattern 120.The material of this insulating barrier for example is insulating material such as silica or silicon nitride, and its formation method for example is a chemical vapour deposition technique.The thickness of insulating barrier for example is 0.3 μ m～0.6 μ m, but not in order to limit the present invention, has in this technical field and know that usually the knowledgeable can adjust according to design requirement.
Then, please be simultaneously with reference to Fig. 3 E and Fig. 4 E, on substrate 100, form second metal level of patterning, to define many data wirings 134, a plurality of grids 136 and a plurality of metal electrode 138, wherein each data wiring 134 is respectively along the bearing of trend of pairing source electrode pattern 106 and be disposed on the source electrode pattern 106, each grid 136 is disposed at respectively on second insulating pattern 130 of pairing source electrode 110 tops, and extension connects scan wiring 104, each metal electrode 138 is disposed on first insulating pattern 128 in the pairing pixel region 108, and via the 3rd opening 132, second opening 126 and first opening 118 are electrically connected to pairing shared wiring 102.Metal electrode 138 and shared wiring 102 double team pixel electrodes 124 are to form bigger storage capacitors.Second metal layer thickness for example is 0.15 μ m～0.5 μ m, but not in order to limit the present invention, has in this technical field and know that usually the knowledgeable can adjust according to design requirement.
Figure 5 shows that the profile of C-C ' hatching in Fig. 3 E.
Please refer to Fig. 5, source electrode 110 and the both sides up and down that are positioned at first semiconductor pattern 114 as the partial pixel electrode 124 that drains add that the grid 136 that is positioned on second insulating pattern 130 promptly becomes rectilinear TFT.Rectilinear TFT can utilize bilateral conducting to strengthen channel width, utilizes the film thickness monitoring channel length, and improves the ratio of the channel width/channel length of drive thin film transistors than (W/L), therefore has high conducting electric current.Therefore in addition, between first semiconductor pattern 114 and source electrode 110 and pixel electrode 124, dispose ohmic contact layer 112,122 respectively, can significantly reduce the electrons tunnel probability and reduce potential energy, but and then send a telegraph the field, avoid producing short channel effect.
In the thin-film transistor array base-plate of the foregoing description manufacturing, each member of TFT is uprightly arranged, and therefore can promote the conducting electric current.On the other hand, shared wiring 102 and metal electrode 138 double team pixel electrodes 124 can increase the storage capacitors value effectively.
Fig. 6 A～Fig. 6 C is depicted as the manufacturing process profile of the thin-film transistor array base-plate of another embodiment of the present invention.Fig. 7 A～Fig. 7 C is depicted as the manufacturing process profile of A-A ' and B-B ' hatching in Fig. 6 A～Fig. 6 C.
At first, please provide a substrate 200 simultaneously with reference to Fig. 6 A and Fig. 7 A, substrate 200 for example is transparency carriers such as glass substrate.Then, on substrate 200, form the first metal layer (not shown), semiconductor layer (not shown) and second metal level (not shown) in regular turn.It should be noted that when forming semiconductor layer, more can form ohmic contact layer (not shown) in the both sides up and down of semiconductor layer respectively.The material of ohmic contact layer for example is a doped amorphous silicon, and its formation method is for example also carried out ion doping synchronously with the chemical vapour deposition technique deposition of amorphous silicon and formed, and the kenel of ion doping for example is the heavy doping of N type.
Then, patterning second metal level, semiconductor layer and the first metal layer, the first metal layer is defined as many shared wiring 202 (shared wiring 202 only is shown) in Fig. 6 A, plurality of scanning wirings 204 (scan wiring 204 only is shown in Fig. 6 A) and many source electrode patterns 206, wherein scan wiring 204 defines a plurality of pixel regions 208 with source electrode pattern 206 on substrate 200, shared wiring 202 is respectively by pairing pixel region 206 and be parallel to scan wiring 204, and each source electrode pattern 206 is adjacent to and extends a protuberance on the position of pairing scan wiring 204 respectively to pairing pixel region 208, with respectively as source electrode 210.In addition, the first metal layer for example is to be made by the multiple layer metal stack, can avoid the first metal layer and adjacent each layer generation to peel off.
Simultaneously, in each pixel region 208, second metal level and semiconductor layer be defined as the first storehouse pattern 212 that is disposed on the pairing source electrode 210, be disposed at the second storehouse pattern 214 on the shared wiring 202, and the second storehouse pattern 214 has first opening 216 that exposes shared wiring and is disposed on the scan wiring 204 with the bearing of trend intersection of source electrode pattern 206 and the 3rd storehouse pattern 218 on the shared wiring 202.Second metal level in the first storehouse pattern 212 uses as the drain electrode of TFT.
Next, please be simultaneously with reference to Fig. 6 B and Fig. 7 B, on substrate 200, form insulation layer patterned 220, to define second opening 222 above first opening 216 in each pixel region 208 corresponding to first opening 216, define the 3rd opening 224 that exposes the part first storehouse pattern 212 above the first storehouse pattern 212 in each pixel region 208, define a plurality of the 4th openings 226 that expose the part second storehouse pattern 214 above the second storehouse pattern, 214 both sides in each pixel region 208, scan wiring 204 in each pixel region 208 defines the 5th opening 228 that exposes part scan wiring 204 near above the side of source electrode 210, and define a plurality of the 6th openings 230 that expose part source electrode pattern 206 and part the 3rd storehouse pattern 218 above above source electrode pattern 206 both sides in each pixel region 208 and the 3rd storehouse pattern 218 both sides respectively.The material of insulating barrier 220 for example is insulating material such as silica or silicon nitride, and its formation method for example is a chemical vapour deposition technique.
Afterwards, please be simultaneously with reference to Fig. 6 C and Fig. 7 C, on insulation layer patterned 220, form the transparency conducting layer (not shown) of patterning, define two pixel electrodes 232 with shared wiring 202 both sides in each pixel region 208, pixel electrode 232 is electrically connected to the second storehouse pattern 214 via the 4th opening 226, one of them pixel electrode 232 is electrically connected to the first storehouse pattern 212 via the 3rd opening 224, define first transparency electrode 234 above the second storehouse pattern 214 in each pixel region 208, first transparency electrode 234 is electrically connected to shared wiring 202 via second opening 222 and first opening 216, form grid 236 above the source electrode 210 in each pixel region 208, grid 236 is electrically connected to scan wiring 204 via the 5th opening 228, and define a plurality of second transparency electrode, 238, the second transparency electrodes 238 in the bearing of trend of source electrode pattern 216 and shared wiring 202 and scan wiring 204 confluces and electrically connect source electrode patterns 206 and the 3rd storehouse pattern 218 via the 6th opening 230.Second metal level in first transparency electrode 234 and the shared wiring 102 double teams second storehouse pattern 214 is to form bigger storage capacitors.The material of transparency conducting layer for example is indium tin oxide or indium-zinc oxide, and its formation method for example is vapour deposition method or sputtering method.
Next, on substrate 200, form the 3rd metal level (not shown) of patterning, to define many data wirings 240, wherein each bar data wiring 240 is disposed at source electrode pattern 206 tops along the bearing of trend of pairing source electrode pattern 206 respectively, and electrically connects with pairing second transparency electrode 238.
In the thin-film transistor array base-plate of the foregoing description manufacturing, formed TFT is rectilinear TFT, therefore has high conducting electric current.On the other hand, second metal level in first transparency electrode 234 and the shared wiring 102 double teams second storehouse pattern 214 can promote the storage capacitors value.
In sum, the present invention has following advantage at least:
1. in thin-film transistor array base-plate proposed by the invention, have rectilinear TFT, its making area is little and can increase considerably the conducting electric current.
2. thin-film transistor array base-plate proposed by the invention, can increase the storage capacitors value by shared wiring and the second metal level double team transparency electrode or by shared wiring and transparency electrode double team second metal level, can reduce the pixel that is caused because of the mutual coupling of signal and flash, to promote display quality.
3. according to the manufacture method of thin-film transistor array base-plate proposed by the invention, can form ohmic contact layer respectively in both sides up and down, can significantly reduce the electrons tunnel probability, to avoid producing short channel effect at semiconductor layer.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limiting the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, thus protection scope of the present invention when with claim the person of being defined be as the criterion.
Claims (19)
1. the manufacture method of a thin-film transistor array base-plate, this method may further comprise the steps:
One substrate is provided;
On this substrate, form a patterning the first metal layer, to define many shared wiring, plurality of scanning wirings and many source electrode patterns, wherein said scan wiring and described source electrode pattern define a plurality of pixel regions on this substrate, described shared wiring is respectively by pairing this pixel region and be parallel to this scan wiring, and each source electrode pattern is adjacent to and extends a protuberance on the position of pairing described scan wiring respectively to pairing described pixel region, with respectively as one source pole;
On this substrate, form a patterned semiconductor layer, define one second semiconductor pattern to define on one first semiconductor pattern and this shared wiring in each pixel region on this source electrode in each pixel region respectively, and this second semiconductor pattern has one first opening that exposes this shared wiring;
On this substrate, form a patterned transparent conductive layer, in each pixel region, to define a pixel electrode, wherein each pixel electrode covers pairing this first semiconductor pattern and this second semiconductor pattern, and each pixel electrode has one second opening corresponding to this first opening;
On this substrate, form a patterned insulation layer, above each shared wiring, to define one first insulating pattern, and define one second insulating pattern at the bearing of trend of each source electrode pattern and the intersection of pairing this scan wiring, each first insulating pattern has one the 3rd opening corresponding to this second opening, and each second insulating pattern extends this first semiconductor pattern and this pixel electrode that covers pairing this source electrode and this source electrode top; And
On this substrate, form a patterning second metal level, to define many data wirings, a plurality of grids and a plurality of metal electrode, wherein each data wiring is respectively along the bearing of trend of pairing this source electrode pattern and be disposed on this source electrode pattern, each grid is disposed at respectively on this second insulating pattern of pairing this source electrode top, and extension connects this scan wiring, each metal electrode is disposed on this interior first insulating pattern of pairing this pixel region, and via the 3rd opening, this second opening and this first opening are electrically connected to pairing this shared wiring.
2. the manufacture method of thin-film transistor array base-plate as claimed in claim 1 is characterized in that, when forming this semiconductor layer, more comprises respectively forming an ohmic contact layer in the both sides up and down of this semiconductor layer.
3. the manufacture method of thin-film transistor array base-plate as claimed in claim 2 is characterized in that, the formation method of described ohmic contact layer comprises ion doping.
4. the manufacture method of thin-film transistor array base-plate as claimed in claim 1, it is characterized in that, when forming this semiconductor layer, more be included on the intersection of the bearing of trend of described source electrode pattern and described scan wiring and described shared wiring and define one the 3rd semiconductor pattern respectively, and make described second insulating pattern of follow-up formation cover pairing the 3rd semiconductor pattern respectively.
5. thin-film transistor array base-plate, this thin-film transistor array base-plate comprises:
One substrate;
One patterning the first metal layer, be disposed on this substrate, comprise many shared wiring, plurality of scanning wirings and many source electrode patterns, wherein said scan wiring and described source electrode pattern define a plurality of pixel regions on this substrate, described shared wiring is respectively by pairing this pixel region and be parallel to this scan wiring, and each source electrode pattern is adjacent to and extends a protuberance on the position of pairing described scan wiring respectively to pairing described pixel region, with respectively as one source pole;
One patterned semiconductor layer, be disposed on this patterning the first metal layer and this substrate, comprise a plurality of first semiconductor patterns and a plurality of second semiconductor pattern, wherein this first semiconductor pattern is disposed on this interior source electrode of each pixel region, and this second semiconductor pattern is disposed on this shared wiring in each pixel region, and this second semiconductor pattern has one first opening that exposes this shared wiring;
One patterned transparent conductive layer, be disposed on this patterned semiconductor layer and this substrate, in order in each pixel region, to define a pixel electrode, wherein each pixel electrode covers pairing this first semiconductor pattern and this second semiconductor pattern, and each pixel electrode has one second opening corresponding to this first opening;
One patterned insulation layer, be disposed on this substrate, comprise a plurality of first insulating patterns and a plurality of second insulating pattern, wherein this first insulating pattern is disposed at each shared wiring top, and each first insulating pattern has one the 3rd opening corresponding to this second opening, and this second insulating pattern is disposed at the intersection of bearing of trend and pairing this scan wiring of each source electrode pattern, and each second insulating pattern extends this first semiconductor pattern and this pixel electrode that covers pairing this source electrode and this source electrode top; And
One patterning, second metal level, be disposed on this substrate, comprise many data wirings, a plurality of grids and a plurality of metal electrode, wherein each data wiring is respectively along the bearing of trend of pairing this source electrode pattern and be disposed on this source electrode pattern, each grid is disposed at respectively on this second insulating pattern of pairing this source electrode top, and extension connects this scan wiring, each metal electrode is disposed on this interior first insulating pattern of pairing this pixel region, and via the 3rd opening, this second opening and this first opening are electrically connected to pairing this shared wiring.
6. thin-film transistor array base-plate as claimed in claim 5 is characterized in that, the both sides up and down of this semiconductor layer have an ohmic contact layer respectively.
7. thin-film transistor array base-plate as claimed in claim 6 is characterized in that the material of described ohmic contact layer comprises doped amorphous silicon.
8. thin-film transistor array base-plate as claimed in claim 5 is characterized in that, the material of described transparency conducting layer is indium tin oxide or indium-zinc oxide.
9. thin-film transistor array base-plate as claimed in claim 5 is characterized in that described the first metal layer is to be formed by stacking by multiple layer metal.
10. thin-film transistor array base-plate as claimed in claim 5, it is characterized in that, described patterned semiconductor layer more comprises one the 3rd semiconductor pattern on the intersection of the bearing of trend that is configured in described source electrode pattern and described scan wiring and described shared wiring, and described second insulating pattern covers pairing the 3rd semiconductor pattern respectively.
11. the manufacture method of a thin-film transistor array base-plate, this method comprises:
One substrate is provided;
On this substrate, form a first metal layer, semi-conductor layer and one second metal level in regular turn;
This second metal level of patterning, this semiconductor layer and this first metal layer, so that this first metal layer is defined as many shared wiring, plurality of scanning wirings and many source electrode patterns, wherein said scan wiring and described source electrode pattern define a plurality of pixel regions on this substrate, described shared wiring is respectively by pairing this pixel region and be parallel to this scan wiring, and each source electrode pattern is adjacent to and extends a protuberance on the position of pairing described scan wiring respectively to pairing described pixel region, with respectively as one source pole, simultaneously in each pixel region, this second metal level and this semiconductor layer are defined as the one first storehouse pattern that is disposed on pairing this source electrode, be disposed at one second storehouse pattern on this shared wiring, and this second storehouse pattern has one first opening that exposes this shared wiring, and be disposed on this scan wiring with the bearing of trend intersection of this source electrode pattern and one the 3rd storehouse pattern on this shared wiring;
On this substrate, form a patterned insulation layer, to define one second opening above this first opening in each pixel region corresponding to this first opening, define one the 3rd opening that exposes this first storehouse pattern of part above this first storehouse pattern in each pixel region, define a plurality of the 4th openings that expose this second storehouse pattern of part above these second storehouse pattern both sides in each pixel region, this scan wiring in each pixel region is near defining one the 5th opening that exposes this scan wiring of part above the side of this source electrode, and define a plurality of the 6th openings that expose this source electrode pattern of part and part the 3rd storehouse pattern above above these source electrode pattern both sides in each pixel region and the 3rd storehouse pattern both sides respectively;
On this patterned insulation layer, form a patterned transparent conductive layer, define two pixel electrodes with these shared wiring both sides in each pixel region, described pixel electrode is electrically connected to this second storehouse pattern via described the 4th opening, one of them pixel electrode is electrically connected to this first storehouse pattern via the 3rd opening, define one first transparency electrode above this second storehouse pattern in each pixel region, this first transparency electrode is electrically connected to this shared wiring via this second opening and this first opening, form a grid above this source electrode in each pixel region, this grid is electrically connected to this scan wiring via the 5th opening, and defining a plurality of second transparency electrodes in the bearing of trend of this source electrode pattern and this shared wiring and this scan wiring confluce, described second transparency electrode electrically connects this source electrode pattern and the 3rd storehouse pattern via described the 6th opening; And
On this substrate, form a patterning the 3rd metal level, to define many data wirings, wherein each data wiring is disposed at this source electrode pattern top respectively along the bearing of trend of pairing this source electrode pattern, and electrically connects with pairing described second transparency electrode.
12. the manufacture method of thin-film transistor array base-plate as claimed in claim 11 is characterized in that, when forming this semiconductor layer, more comprises respectively forming an ohmic contact layer in the both sides up and down of this semiconductor layer.
13. the manufacture method of thin-film transistor array base-plate as claimed in claim 12 is characterized in that, the formation method of described ohmic contact layer comprises ion doping.
14. the manufacture method of thin-film transistor array base-plate as claimed in claim 11 is characterized in that, the formation method of described patterned transparent conductive layer is vapour deposition method or sputtering method.
15. a thin-film transistor array base-plate, this thin-film transistor array base-plate comprises:
One substrate;
One patterning the first metal layer, be disposed on this substrate, comprise many shared wiring, plurality of scanning wirings and many source electrode patterns, wherein said scan wiring and described source electrode pattern define a plurality of pixel regions on this substrate, described shared wiring is respectively by pairing this pixel region and be parallel to this scan wiring, and each source electrode pattern is adjacent to and extends a protuberance on the position of pairing described scan wiring respectively to pairing described pixel region, with respectively as one source pole;
One patterning stack layer, from bottom to top be semi-conductor layer and one second metal level in regular turn, be disposed on this patterning the first metal layer and this substrate, comprise a plurality of first storehouse patterns, a plurality of second storehouse patterns and a plurality of the 3rd storehouse pattern, wherein this first storehouse pattern arrangement is in each pixel region on pairing this source electrode, this second storehouse pattern arrangement is on this shared wiring, and this second storehouse pattern has one first opening that exposes this shared wiring, and the 3rd storehouse pattern arrangement in this scan wiring of the bearing of trend intersection of this source electrode pattern on and on this shared wiring;
One patterned insulation layer, be disposed on this substrate, have a plurality of second openings, a plurality of the 3rd openings, a plurality of the 4th openings, a plurality of the 5th openings, and a plurality of the 6th openings, wherein above this first opening in each pixel region of this second opening position and corresponding to this first opening, above this first storehouse pattern in each pixel region of the 3rd opening position and expose the part this first storehouse pattern, above these second storehouse pattern both sides in each pixel region, the 4th opening position and expose the part this second storehouse pattern, the 5th opening position this scan wiring in each pixel region is near above the side of this source electrode and expose this scan wiring of part, and above these source electrode pattern both sides in each pixel region, the 6th opening position and the 3rd storehouse pattern both sides above and expose the part this source electrode pattern and the part the 3rd storehouse pattern;
One patterned transparent conductive layer, be configured on this patterned insulation layer and this substrate, define two pixel electrodes in order to these shared wiring both sides in each pixel region, described pixel electrode is electrically connected to this second storehouse pattern via described the 4th opening, one of them pixel electrode is electrically connected to this first storehouse pattern via the 3rd opening, has one first transparency electrode above this second storehouse pattern in each pixel region, this first transparency electrode is electrically connected to this shared wiring via this second opening and this first opening, form a grid above this source electrode in each pixel region, this grid is electrically connected to this scan wiring via the 5th opening, and having a plurality of second transparency electrodes in the bearing of trend of this source electrode pattern and this shared wiring and this scan wiring confluce, described second transparency electrode electrically connects this source electrode pattern and the 3rd storehouse pattern via the described the 6th this opening; And
One patterning the 3rd metal level, be configured on this substrate, comprise many data wirings, wherein each data wiring is disposed at this source electrode pattern top respectively along the bearing of trend of pairing this source electrode pattern, and electrically connects with pairing described second transparency electrode.
16. thin-film transistor array base-plate as claimed in claim 15 is characterized in that, the both sides up and down of described semiconductor layer have an ohmic contact layer respectively.
17. thin-film transistor array base-plate as claimed in claim 16 is characterized in that, the material of described ohmic contact layer comprises doped amorphous silicon.
18. thin-film transistor array base-plate as claimed in claim 15 is characterized in that, the material of described transparency conducting layer is indium tin oxide or indium-zinc oxide.
19. thin-film transistor array base-plate as claimed in claim 15 is characterized in that, this first metal layer is to be formed by stacking by multiple layer metal.
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|---|---|---|---|---|
| CN1580913A (en) * | 2004-05-14 | 2005-02-16 | 友达光电股份有限公司 | Thin film transistor array base board |
| CN1598675A (en) * | 2004-08-18 | 2005-03-23 | 友达光电股份有限公司 | Thin film transistor array |
| US20050200800A1 (en) * | 2004-03-11 | 2005-09-15 | Fujitsu Display Technologies Corporation | Method of manufacturing liquid crystal display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050200800A1 (en) * | 2004-03-11 | 2005-09-15 | Fujitsu Display Technologies Corporation | Method of manufacturing liquid crystal display device |
| CN1580913A (en) * | 2004-05-14 | 2005-02-16 | 友达光电股份有限公司 | Thin film transistor array base board |
| CN1598675A (en) * | 2004-08-18 | 2005-03-23 | 友达光电股份有限公司 | Thin film transistor array |
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