CN100442542C - Method of manufacturing variable capacitance diode and variable capacitance diode - Google Patents
Method of manufacturing variable capacitance diode and variable capacitance diode Download PDFInfo
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- CN100442542C CN100442542C CNB2004101011103A CN200410101110A CN100442542C CN 100442542 C CN100442542 C CN 100442542C CN B2004101011103 A CNB2004101011103 A CN B2004101011103A CN 200410101110 A CN200410101110 A CN 200410101110A CN 100442542 C CN100442542 C CN 100442542C
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- H—ELECTRICITY
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- H—ELECTRICITY
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Abstract
In a method of manufacturing a variable capacitance diode according to the present invention, a mask is formed on a semiconductor substrate of a first conductive type having a low impurity concentration, a semiconductor region of the first conductive type having an intermediate impurity concentration is formed on the semiconductor substrate by means of ion implantation via an opening portion of the mask, a semiconductor region of a second conductive type having a high impurity concentration is formed in the semiconductor substrate on a surface side thereof relative to the semiconductor region of the first conductive type having the intermediate impurity concentration via the same opening portion of the mask, and the semiconductor region of the first conductive type having the intermediate impurity concentration and the semiconductor region of the second conductive type having the high impurity concentration are activated by applying a heat treatment to the semiconductor substrate. In a variable capacitance diode according to the present invention, a structure in which an annular contact layer of a first conductive type is formed in a periphery of a semiconductor region of a second conductive type having a high impurity concentration constitutes each of a plurality of units and the plurality of units is disposed in an array.
Description
Technical field
The present invention relates to a kind of method and a kind of varicap of making varicap, more specifically, relate to have MOS (metal-oxide semiconductor (MOS)) or bipolar transistor and make the varicap of integrated circuit.
Background technology
Along with reducing of the mobile communication equipment size of for example mobile phone, the single-chip technology has been used to comprise the circuit of peripheral components, for example frequency synthesizer (PLL) and voltage controlled oscillator.The varicap of forming the VCO on the Semiconductor substrate is used to utilize the depletion-layer capacitance of pn knot, by applying reverse biased, comes the control capacitance value.Need integrated varicap, so that obtain big rate of change of capacitance with respect to given change in voltage.
With reference to the reference number among the Figure 10 that shows conventional variable di-cap example, 41 expression n N-type semiconductor N substrates, 42 expression n
-The zone, 43 expression n zones, 44 expression n ' zones, 45 expression cathode layers, 46 expression pn knots, 47 expression anode layer (p
-Regional), and 48 expression interlayer dielectrics.Apply reverse biased to pn knot 46, so that utilize the depletion layer that mainly is distributed in the cathode layer 45 to form varicap.Figure 11 shows the curve chart of the impurities concentration distribution in the section that obtains along the D-D line of Figure 10.
As the requirement of the configuration aspects of catching up with the circuit element miniaturization, need form anode layer 47 with size greater than cathode layer 45.Have at varicap under the situation of big rate of change of capacitance, the concentration gradient in the n ' zone of pn knot part is very steep.Therefore, relevant with the fluctuation in manufacture process change in concentration trends towards becoming big.As a result, the variable capacitance rate has caused significant fluctuation.
The key factor that obtains big rate of change of capacitance is to make the pn knot form optimizations such as regional surface impurity concentration and impurities concentration distribution figure.
With reference to the reference number among the Figure 12 that shows another varicap example, 51 expression n N-type semiconductor N substrates, 52 expression p
-The zone, 53 expression p zones, 54 expression anode layers, 55 expression pn knots, 56 expression cathode layer (n
-The zone), 57 expression interlayer dielectrics, 58 expression anode contact layers, 59 expression anode electrodes, and 60 expression cathode electrodes.Apply reverse biased to pn knot 55, so that use the depletion layer that mainly is distributed in the anode layer 54 to form varicap.Figure 13 shows the curve chart of the impurities concentration distribution in the section that obtains along the E-E line of Figure 12.The miniaturization of circuit element causes the generation of the misalignment between anode layer 54 (p zone) and the cathode layer 56, and this makes and improves very difficulty of precision.Because the concentration gradient in the p zone of pn knot part is very steep, so the variable capacitance rate has caused significant fluctuation.
With reference to the reference number among the Figure 14 that shows another conventional variable di-cap example, 61 expression p N-type semiconductor N substrates, 62 expression anode layer (p
-The type layer), 63 expression cathode layer (n
+The type layer), 64 expression anode contact layer (p
+The type layer), and 65 expressions separate dielectric films.Appear at n because separate dielectric film 65
+Type layer (cathode layer 63) and p
+Between the type layer (anode contact layer 64), when applying reverse biased, can't effectively utilize the capacitive component of horizontal direction.As a result, the integrated absolute capacitance values of varicap has caused low electric capacity, especially in low voltage range, therefore can't obtain enough rate of change of capacitance.On the contrary, need to make great efforts to increase the absolute capacitance of area to obtain wishing of varicap, this makes that the miniaturization of circuit element is very difficult.
Summary of the invention
Therefore, main purpose of the present invention is to reduce to be used to constitute the additional step of varicap, and the method for bearing the fluctuation of minimizing and realizing high-precision varicap of making is provided.With reference to semi-conductive conduction type hereinafter described, first conduction type and second conduction type relate separately to one of semi-conductive p and n type.When first conduction type was the p type, second conduction type was the n type.On the contrary, when first conduction type was the n type, then second conduction type was the p type.
Method according to manufacturing varicap of the present invention comprises:
Step forms mask so that opening with lower area, in described location, forms varicap on the Semiconductor substrate of first conduction type with low impurity concentration;
Step by the opening portion of mask, utilizes ion to inject, and forms the semiconductor regions of first conduction type with interstitial impurity concentration on Semiconductor substrate;
Step by the opening portion of mask, in the Semiconductor substrate with respect to the face side of the semiconductor regions of first conduction type with interstitial impurity concentration, forms the semiconductor regions of second conduction type with high impurity concentration; And
Step by Semiconductor substrate is heat-treated, excites the semiconductor regions and the semiconductor regions with second conduction type of high impurity concentration of first conduction type with interstitial impurity concentration.
As first advantage of aforementioned manufacture method, utilize the anode layer and the cathode layer of identical mask formation varicap, so that form anode and cathode layer according to self aligned mode.As a result, anode and cathode layer can not suffer any misalignment, and this precision that has prevented that the miniaturization owing to circuit element from causing reduces.As another advantage,, can reduce the step that increases in order to form varicap in the LSI technology because only carried out a step about mask.
Another method according to manufacturing varicap of the present invention comprises:
Step in the Semiconductor substrate of second conduction type with low impurity concentration, forms the semiconductor regions of first conduction type with low impurity concentration;
Step forms mask so that opening with lower area, in described location, forms varicap on the semiconductor regions of first conduction type with low impurity concentration;
Step by the opening portion of mask, utilizes ion to inject, and in the semiconductor regions of first conduction type with low impurity concentration, forms the semiconductor regions of first conduction type with interstitial impurity concentration;
Step, opening portion by mask, in the Semiconductor substrate, form the semiconductor regions of second conduction type with high impurity concentration with respect to the face side of the semiconductor regions of first conduction type in the semiconductor regions that is formed on first conduction type, that have interstitial impurity concentration with low impurity concentration; And
Step by Semiconductor substrate is heat-treated, excites the semiconductor regions and the semiconductor regions with second conduction type of high impurity concentration of first conduction type with interstitial impurity concentration.
The technical characterictic of previous constructions is: not in Semiconductor substrate from one's body but be formed on the semiconductor regions that forms the semiconductor regions of first conduction type in second half conductive region in the Semiconductor substrate and have second conduction type of high impurity concentration with interstitial impurity concentration.More specifically, in the semiconductor regions of second conduction type, form the semiconductor regions of conduction type, and in the semiconductor regions of first conduction type, form anode and cathode layer with low impurity concentration with low impurity concentration with low impurity concentration.
In preceding method, except operating effect described above, anode and cathode potential can also be set arbitrarily, without any restriction, this is because anode and cathode layer are in electric floating state with respect to Semiconductor substrate to the current potential of Semiconductor substrate to it.
In any in making two kinds of methods of varicap, formation have interstitial impurity concentration first conduction type semiconductor regions step and form in the step of semiconductor regions of second conduction type with high impurity concentration, the formation of semiconductor regions with first conduction type of interstitial impurity concentration can be prior to the formation of the semiconductor regions of second conduction type with high impurity concentration, perhaps can form the semiconductor regions of second conduction type earlier, form the semiconductor regions of first conduction type afterwards with interstitial impurity concentration with high impurity concentration.
In the transistorized LSI technology of CMOS was installed, forming the step of semiconductor regions of first conduction type with interstitial impurity concentration and the step that forms the semiconductor regions of second conduction type with high impurity concentration can carry out simultaneously with the source electrode in the CMOS transistor and the formation of drain region.When forming these zones with source electrode and drain region simultaneously, do not need to add any step about mask.Can be only form varicap, promptly at the ion implantation step of anode and cathode layer with an additional step.
In addition, with reference to the step of the semiconductor regions that forms first conduction type with low impurity concentration, the formation in aforesaid semiconductor zone can be carried out simultaneously with the formation of the transistorized well region of CMOS.
In addition, preferably, utilize ion to inject to finish the formation of the semiconductor regions of first conduction type with interstitial impurity concentration, thereby after heat treatment, the position of the peak concentration in aforesaid semiconductor zone drops to the position that the pn between the semiconductor regions of aforesaid semiconductor zone and second conduction type with high impurity concentration ties.Therefore, the concentration gradient of semiconductor regions that has first conduction type of interstitial impurity concentration in the pn knot part begins moderately to reduce owing to make pn knot that the influence of fluctuation the causes change in concentration in partly.The result can suppress the fluctuation of variable capacitance rate.
In addition, according to the present invention, the capacitive component of varicap that can be by effectively utilizing horizontal direction and each diffusion layer that varicap is formed in definition provide to have with respect to the fully big rate of change of capacitance of the absolute capacitance of hope and can control the high-performance varicap of its Area Growth.
In variable capacitance according to the present invention, as mentioned above, the unit is set in array, and each unit all has following structure: the contact layer that forms first conduction type with annular shape around the semiconductor regions of second conduction type with high impurity concentration.
In addition, spacing between the contact layer of the semiconductor regions of second conduction type with high impurity concentration and first conduction type is equal to or greater than the width with the formed depletion layer of minimum voltage of employed reverse biased, and is equal to or less than the width with the formed depletion layer of its maximum voltage.
The capacitive component of varicap is decomposed into the component of horizontal direction and the component of vertical direction.For horizontal component, when applying reverse biased, the width of depletion layer is subjected to having the restriction of the spacing between the annular contact layer of the semiconductor regions of second conduction type of high impurity concentration and first conduction type.Therefore, when the circuit element miniaturization, horizontal component produces higher relatively absolute capacitance values.On the contrary, with respect to horizontal component, when when vertical component applies reverse biased, it is not subjected to any restriction of depletion width, therefore produces relatively low absolute capacitance values.
Account in horizontal component under the situation of too much ratio, because absolute capacitance values increases the rate of change of capacitance variation in high voltage range.Accounted in horizontal component under the situation of small scale, because absolute capacitance values descends the rate of change of capacitance variation in low voltage range.Exist high impurity concentration second conduction type semiconductor regions area than (ratio of lateral area/floor space) and have the semiconductor regions of second conduction type of high impurity concentration and the annular contact layer of first conduction type between spacing, make rate of change of capacitance reach its maximum.Therefore, will form in this manner so that each unit of raising rate of change of capacitance is arranged in the array.Therefore, can be accomplished the varicap of the rate of change of capacitance fully big with respect to desirable absolute capacitance values.As a result, can not revise diffusion layer and provide varicap with desirable feature with the formation step.
By following description to the preferred embodiments of the present invention, can be well understood to other purposes of the present invention and advantage, can understand better with reference to the accompanying drawings.
Description of drawings
Figure 1A-1F shows the profile according to the key step of the method for the manufacturing varicap of the embodiment of the invention 1.
Fig. 2 shows the curve chart of the impurities concentration distribution in the section that obtains along the A-A line of Fig. 1 F.
Fig. 3 A-3F shows the profile according to the key step of the method for the manufacturing varicap of the embodiment of the invention 2.
Fig. 4 shows the curve chart of the impurities concentration distribution in the section that obtains along the B-B line of Fig. 3 F.
Fig. 5 A is the plane graph according to the single cell mesh of the varicap of the embodiment of the invention 3.
Fig. 5 B is the profile that the C-C line along Fig. 5 A obtains.
Fig. 6 shows the integrally-built plane graph according to the varicap of embodiment 3.
Fig. 7 is the electric capacity of varicap and the correlation curve chart of reverse biased.
Fig. 8 is the rate of change of capacitance of varicap and the correlation curve chart of the ratio of lateral area/floor space.
Fig. 9 is the correlation curve chart of the rate of change of capacitance and the distance between anode and the cathode contact layer of varicap.
Figure 10 is the schematic diagram according to the structure of the varicap of first conventional example.
Figure 11 shows the curve chart of the impurities concentration distribution in the section that obtains along the D-D line of Figure 10.
Figure 12 is the schematic diagram according to the structure of the varicap of second conventional example.
Figure 13 shows the curve chart of the impurities concentration distribution in the section that obtains along the E-E line of Figure 12.
Figure 14 is the schematic diagram according to the structure of the varicap of the 3rd conventional example.
Embodiment
Hereinafter, with reference to the accompanying drawings, the method according to the manufacturing varicap of the embodiment of the invention 1 is described.
With reference to the reference number among the figure 1A-1F, 3 expression p
-The N-type semiconductor N substrate, 4 expression mask materials, 5 expression B
+Ion implanted layer, 6 expression p zones, 7 expression anode layers, 8 expression pn knots, 9 expression As
+Ion implanted layer, 10 expression cathode layer (n
+The zone), 11 expression anode contact layers, insulation film between 12 presentation layers, 13 expression cathode electrodes, and 14 expression anode electrodes.
Below will describe make have aforementioned structure, according to the method for the varicap of embodiment 1.
At first, shown in Figure 1A, on Semiconductor substrate 3, form mask material 4, so that opening forms the zone of varicap therein.
Next, shown in Figure 1B, at the opening portion injection B of mask material 4
+Ion is so that form B in substrate 3
+Ion implanted layer 5.B
+The formation of ion implanted layer 5 makes the peak concentration (will describe afterwards) in the p zone 6 finally drop in p zone 6 to tie with pn between the cathode layer 10 8 position.
Next, shown in Fig. 1 C, as previously mentioned, at the opening portion injection As of mask material 4
+Ion is so that the B in substrate 3
+Form As on the ion implanted layer 5
+Ion implanted layer 9.As
+The formation of ion implanted layer 9 makes the peak concentration (will describe afterwards) in the cathode layer 10 drop to the near surface of substrate 3.
Next, shown in Fig. 1 D, remove mask material 4, thereby obtain the B in the substrate 3
+Ion implanted layer 5 and As
+Ion implanted layer 9.
Next, shown in Fig. 1 E, utilize heat treatment, excite B
+Ion implanted layer 5 and As
+Ion implanted layer 9, thus anode layer 7 and cathode layer (n formed
+The zone) equivalent layer in 10.
At last, shown in Fig. 1 F, form anode contact layer 11 in order, layer insulation film 12, cathode electrode 13, and anode electrode 14.Therefore, can have been formed the semiconductor device of varicap therein.
Present embodiment has the following advantages.
At first, utilize ion injection method, use identical mask to form anode layer and cathode layer, this makes it form anode layer and cathode layer according to self aligned mode.
In addition, installed therein in the transistorized LSI technology of COMS, cathode layer and the transistorized source electrode of nMOS and the drain region of varicap can be formed simultaneously, and anode contact layer and the transistorized source electrode of pMOS and the drain region of varicap can be formed simultaneously.So, do not need to increase step about mask.Varicap can only form with an additional step, has wherein realized the ion injection for the p zone of anode layer.
Next, as shown in Figure 2, B
+The formation of ion implanted layer makes the peak concentration in p zone finally drop to be positioned at p zone and regional n
+Between pn knot part.In this manner, the concentration gradient in the p zone in the pn knot part becomes moderate.Therefore, can reduce consequently can control to the fluctuation of variable capacitance rate owing to the change in concentration of making in the pn knot part that causes that fluctuates.
In above-mentioned technology, preferably, the concentration maximum in the substrate 3 equals 1 * 10
17Cm
-3, preferably, the peak concentration minimum in the p zone 6 equals 5 * 10
16Cm
-3And maximum equals 1 * 10
18Cm
-3, and preferably, cathode layer (n
+The zone) the peak concentration minimum in 10 equals 1 * 10
20Cm
-3
Next, with reference to the accompanying drawings, the method according to the manufacturing varicap of the embodiment of the invention 2 is described.
With reference to the reference number among the figure 3A-3F, 1 expression n N-type semiconductor N substrate, and 2 expression p
-The zone.Identical among other parts and the embodiment 1, and any same section between two embodiment has identical reference number.
The p that uses n N-type semiconductor N substrate 1 to replace among the embodiment 1
-N-type semiconductor N substrate 3.On Semiconductor substrate 1, form p
-Zone 2, thus identical with embodiment 1, be provided with the substrate that forms varicap thereon.
Describe below have aforementioned structure, according to the method for the manufacturing varicap of embodiment 2.
At first, as described in Fig. 3 A, on Semiconductor substrate 1, form p
-Zone 2 then, forms mask material 4, so that opening forms the zone of varicap.
Next, shown in Fig. 3 B, at the opening portion injection B of mask material 4
+Ion is so that at p
-Form B in the zone 2
+Ion implanted layer 5.B
+The formation of ion implanted layer 5 makes peak concentration (will describe afterwards) in the p zone 6 finally drop to the position of tying with pn between the cathode layer 10 in p zone 6.
Next, shown in Fig. 3 C, as described above, at the opening portion injection As of mask material 4
+Ion, thereby at p
-B in the zone 2
-Form As on the ion implanted layer 5
+Ion implanted layer 9.As
+The formation of ion implanted layer 9 makes the peak concentration (will describe afterwards) in the cathode layer 10 drop to p
-The near surface in zone 2.
Next, shown in Fig. 3 D, remove mask material 4, so that obtain p
-B in the zone 2
+Ion implanted layer 5 and As
+Ion implanted layer 9.
Next, shown in Fig. 3 E, utilize heat treatment, excite B
+Ion implanted layer 5 and As
+Ion implanted layer 9, thus anode layer 7 and cathode layer (n formed
+The zone) equivalent layer in 10.
At last, shown in Fig. 3 F, form anode contact layer 11 in order, layer insulation film 12, cathode electrode 13, and anode electrode 14.Therefore, can have been formed the semiconductor device of varicap therein.
Except the advantage of describing among the embodiment 1, present embodiment also provides following advantage.
At first, p
-The zone is formed on the n N-type semiconductor N substrate, and thereafter at p
-Form varicap in the zone.According to this mode, anode and cathode layer are in electric floating state with respect to substrate.More specifically, though be subjected to the restriction that anode electrode has the current potential identical with substrate always according to embodiment 1 described structure, according to embodiment 2, when using anode and cathode layer, can anode and cathode potential be set to optional current potential because these layers all are in electric floating state with respect to substrate electric potential.
In addition, under the situation that the transistorized LSI technology of CMOS is installed, can form the p of the anode layer of varicap simultaneously
-Zone and the transistorized p well region of nMOS, this makes the formation of varicap need not increase extra step.
Next, as shown in Figure 4, B
+The formation of ion implanted layer makes the peak concentration in p zone finally drop to be positioned at p zone and n
+Pn knot part between the zone.In this manner, the concentration gradient in the p zone in the pn knot part becomes moderate.Therefore, can reduce consequently can control the fluctuation of variable capacitance rate owing to the change in concentration of making in the pn knot that causes that fluctuates.
In aforesaid example, preferably, p
-Peak concentration minimum in the zone 2 equals 1 * 10
16Cm
-3And maximum equals 1 * 10
17Cm
-3, and p zone 6 and cathode layer (n
+The zone) identical among the peak concentration in 10 and the embodiment 1.
Compare with 2 with embodiment 1, following modified example also is effective.
In the method that forms cathode layer 10, adopt and use As
+The ion injection method of ion still, also can use vapour deposition method of diffusion or similar approach.The present invention is for not any restriction in addition of formation method of cathode layer 10.
In addition, can form B in reverse order
+Ion implanted layer 5 and As
+Ion implanted layer 9 this means at B
-Before forming, ion implanted layer 5 forms As
+Ion implanted layer 9 so also can obtain same effect.
As long as satisfy conduction type separately, to B
+Ion implanted layer 5 and As
+Ionic species in the ion implanted layer 9 without limits.
In addition, suppose that first conduction type is that the p type and second conduction type are that the n type comes present embodiment is described.But, also n type and p type can be used separately as first conduction type and second conduction type, can obtain identical effect like this.
The type, thickness etc. that are with or without surface protective film and mask material and layer insulation film when in addition, ion being injected are without limits.
Hereinafter, with reference to the accompanying drawings, the method according to the manufacturing varicap of the embodiment of the invention 3 is described.
Fig. 5 A is the plane graph of single unit among Fig. 6.Fig. 5 B is the profile that the C-C line along Fig. 5 A obtains.
With reference to the reference number among figure 5 and Fig. 6, the cathode layer that 21 expressions are made up of the semiconductor regions of second conductive area with high impurity concentration, 22 expressions have the anode contact layer of first conduction type of annular shape, 23 expression anode layers (diffusion layer of first conduction type), 24 expression p zones, 25 expression p
-The zone, insulation film between 26 presentation layers, 27 expression negative electrode contacts, 28 expression anode contacts, 29 expression cathode electrodes, 30 expression anode electrodes, the side surface portion (area Sl) of 31 expression cathode layers, the basal surface part (area Sv) of 32 expression cathode layers, d represents the spacing between cathode layer 21 and the circular anode contact layer 22.
Operation according to the varicap of present embodiment is described below.
The capacitive component of varicap is decomposed into the component and vertical side component together of horizontal direction.
At first, because when applying reverse biased, the width of depletion layer is subjected to the restriction of the spacing d between cathode layer 21 and the circular anode contact layer 22, and horizontal component produces higher relatively absolute capacitance values.On the contrary, with respect to horizontal component, when applying reverse biased, vertical component is not subjected to any restriction of depletion layer, therefore, produces relatively low absolute capacitance values.
Account in horizontal component under the situation of too much ratio, because absolute capacitance values increases in the high voltage range V2 of Fig. 7, rate of change of capacitance descends.When included horizontal component accounted for too small scale, because absolute capacitance values reduces in low voltage range Vl, rate of change of capacitance descended.The area that has cathode layer 21 is than (ratio of lateral area/floor space: Sl/Sv) the spacing d (see figure 9) between (see figure 8) and cathode layer 21 and the circular anode contact layer 22 makes rate of change of capacitance reach its maximum.According to present embodiment, with unit cell arrangement in array, in described unit, circular anode contact layer 22 be formed at cathode layer 21 around.Therefore, can be accomplished the varicap of the rate of change of capacitance fully big with respect to the absolute capacitance values of hope.As a result, not needing to revise diffusion layer and step can provide and have the varicap of wishing feature.
Next, cathode layer 21 is set to equate with spacing between the circular anode contact layer 22.Therefore, can be accomplished the varicap of the rate of change of capacitance fully big with respect to the absolute capacitance values of hope.As a result, can provide control its Area Growth and can bring into play high performance varicap.
Next, have nothing in common with each other a plurality of unit of the spacing between the cathode layer 21 and circular anode contact layer 22 have been formed wherein, thereby in the time of in the working voltage with varicap is arranged on different scopes, in each scope of working voltage, can obtain having varicap with respect to the required rate of change of capacitance of the absolute capacitance values of hope.As a result, a plurality of varicaps can be provided, and need not increase other diffusion layer or step.
In addition, when with the area of cathode layer 21 than the scope that is arranged on lateral area/floor space=0.08-0.18 in the time, can obtain having varicap with respect to the big rate of change of capacitance of the absolute capacitance values of hope.As a result, can provide to have the varicap of wishing feature, and needn't increase other diffusion layer or step.
In addition, the area ratio when cathode layer 21 is set to
When (the 0.13rd, the median in the 0.08-0.18 scope), the varicap that can obtain having the rate of change of capacitance fully big with respect to the absolute capacitance values of hope.As a result, can provide control its Area Growth and can bring into play high performance varicap.
In addition, spacing between cathode layer 21 and circular anode contact layer 22 is equal to or greater than the width of the formed depletion layer of minimum voltage of employed reverse biased, and when being equal to or less than the width with the formed depletion layer of its maximum voltage, can effectively utilize the capacitive component of the horizontal direction of varicap.As a result, can provide control its Area Growth and can bring into play high performance varicap.
Utilization comprises p zone 24 and the p that has formed anode layer 23
-So-called super abrupt junction (the super abrupt junction) structure in zone 25 is described present embodiment.But as long as varicap uses the pn knot, varicap in the structure of its depth direction without limits.
In addition, suppose that first conduction type is that the p type and second conduction type are that the n type is described present embodiment.Yet, p type and n type can be used separately as first conduction type and second conduction type, can obtain identical effect.
In addition, only on the direction of the y direction that is parallel to circular anode contact layer 22, forming anode contact layer 28, yet, also can on the direction that is parallel to its x direction, form.The position of anode contact layer 28, shape and formation method are without limits.When the same, when only on the direction that is parallel to the y direction, forming anode contact layer 28, can form cathode electrode 29 and anode electrode 30 by identical wiring layer with present embodiment.As a result, advantage is to need not to increase the additional step at the new route layer.
In addition, form negative electrode contact 27 according to array and contact 28 with anode, yet, as long as be connected respectively to cathode layer 21 and circular anode contact layer 22, to the not in addition any restriction of position contacting, shape and formation method.
In addition, be the convenient present embodiment of describing, used layer insulation film 26, negative electrode contact 27, anode contact 28, cathode electrode 29 and anode electrode 30.Significantly, these elements are not subjected to any restrictions such as film type, film thickness, position, shape, formation method, formation condition.
Claims (15)
1. method of making varicap comprises:
Step forms mask so that opening with lower area, in described location, forms varicap on the Semiconductor substrate of first conduction type with low impurity concentration;
Step, opening portion by described mask, utilize ion to inject, in described Semiconductor substrate, form the semiconductor regions of first conduction type, and make the peak value of described interstitial impurity concentration be positioned at the inside of the Semiconductor substrate of described first conduction type with low impurity concentration with interstitial impurity concentration;
Step, opening portion by described mask, in described Semiconductor substrate, form the semiconductor regions of second conduction type, and make the peak value of described high impurity concentration be positioned at the surface portion of the Semiconductor substrate of described first conduction type with low impurity concentration with high impurity concentration; And
Step by Semiconductor substrate is heat-treated, excites the semiconductor regions and the semiconductor regions with second conduction type of high impurity concentration of first conduction type with interstitial impurity concentration,
After described exciting step, the lateral parts of the semiconductor regions of described second conduction type with high impurity concentration links to each other with described Semiconductor substrate with first conduction type of low impurity concentration, and the bottom surface portions of the semiconductor regions of described second conduction type with high impurity concentration links to each other with described semiconductor regions with first conduction type of interstitial impurity concentration.
2. the method for manufacturing varicap according to claim 1 is characterized in that:
Have in the step of semiconductor regions of the step of semiconductor regions of first conduction type of interstitial impurity concentration and second conduction type that formation has high impurity concentration in formation, at first form the semiconductor regions of second conduction type, form the semiconductor regions of first conduction type afterwards with interstitial impurity concentration with high impurity concentration.
3. the method for manufacturing varicap according to claim 1 is characterized in that:
The step of semiconductor regions that has second conduction type of high impurity concentration for formation when forming transistorized source electrode of CMOS and drain region, forms the semiconductor regions of second conduction type with high impurity concentration.
4. the method for manufacturing varicap according to claim 1 is characterized in that:
Utilize ion to inject the semiconductor regions that forms first conduction type with interstitial impurity concentration, thereby after heat treatment, the position of the peak concentration in the semiconductor regions of described first conduction type with interstitial impurity concentration is at the semiconductor regions of first conduction type with interstitial impurity concentration and have pn knot position between the semiconductor regions of second conduction type of high impurity concentration.
5. method of making varicap comprises:
Step in the Semiconductor substrate of second conduction type with low impurity concentration, forms the semiconductor regions of first conduction type with low impurity concentration;
Step forms mask so that opening with lower area, in described location, forms varicap on the semiconductor regions of described first conduction type with low impurity concentration;
Step, opening portion by described mask, utilize ion to inject, in the semiconductor regions of described first conduction type with low impurity concentration, form the semiconductor regions of first conduction type, make the peak value of described interstitial impurity concentration be positioned at the inside of the semiconductor regions of described first conduction type with low impurity concentration with interstitial impurity concentration;
Step, opening portion by described mask, in the semiconductor regions of described first conduction type with low impurity concentration, form the semiconductor regions of second conduction type, and make the peak value of described high impurity concentration be positioned at the surface portion of the semiconductor regions of described first conduction type with low impurity concentration with high impurity concentration; And
Step by Semiconductor substrate is heat-treated, excites the semiconductor regions and the semiconductor regions with second conduction type of high impurity concentration of first conduction type with interstitial impurity concentration,
After described exciting step, the lateral parts of the semiconductor regions of described second conduction type with high impurity concentration links to each other with described semiconductor regions with first conduction type of low impurity concentration, and the bottom surface portions of the semiconductor regions of described second conduction type with high impurity concentration links to each other with described semiconductor regions with first conduction type of interstitial impurity concentration.
6. the method for manufacturing varicap according to claim 5 is characterized in that:
Have in the step of semiconductor regions of the step of semiconductor regions of first conduction type of interstitial impurity concentration and second conduction type that formation has high impurity concentration in formation, at first form the semiconductor regions of second conduction type, form the semiconductor regions of first conduction type afterwards with interstitial impurity concentration with high impurity concentration.
7. the method for manufacturing varicap according to claim 5 is characterized in that:
The step of semiconductor regions that has second conduction type of high impurity concentration for formation when forming transistorized source electrode of CMOS and drain region, forms the semiconductor regions of second conduction type with high impurity concentration.
8. the method for manufacturing varicap according to claim 5 is characterized in that:
The step of semiconductor regions that has first conduction type of low impurity concentration for formation when forming the transistorized well region of CMOS, forms the semiconductor regions of first conduction type with low impurity concentration.
9. the method for manufacturing varicap according to claim 5 is characterized in that:
Utilize ion to inject the semiconductor regions that forms first conduction type with interstitial impurity concentration, thereby after heat treatment, the position of the peak concentration in the semiconductor regions of described first conduction type with interstitial impurity concentration is at the semiconductor regions of first conduction type with interstitial impurity concentration and have pn knot position between the semiconductor regions of second conduction type of high impurity concentration.
10. varicap is made of Semiconductor substrate and a plurality of unit of being formed on the described Semiconductor substrate according to array format,
Wherein said each unit includes: the semiconductor regions with first conduction type of low impurity concentration; Semiconductor regions with first conduction type of interstitial impurity concentration; Semiconductor regions with second conduction type of high impurity concentration; With the annular contact layer of first conduction type around the semiconductor regions that is formed on described second conduction type with high impurity concentration,
The lateral parts of the semiconductor regions of described second conduction type with high impurity concentration links to each other with described semiconductor regions with first conduction type of low impurity concentration, and the bottom surface portions of the semiconductor regions of described second conduction type with high impurity concentration links to each other with described semiconductor regions with first conduction type of interstitial impurity concentration
Make the position of the pn knot of peak concentration position between the semiconductor regions of the semiconductor regions of described first conduction type with interstitial impurity concentration and described second conduction type with high impurity concentration of the semiconductor regions of described first conduction type with interstitial impurity concentration.
11. varicap according to claim 10, it is characterized in that, form a plurality of unit in such a way: semiconductor regions and each spacing between the annular contact layer of first conduction type on its in-plane with second conduction type of high impurity concentration are equal to each other.
12. varicap according to claim 10, it is characterized in that, form a plurality of unit in such a way: semiconductor regions and each spacing between the annular contact layer of first conduction type on its in-plane with second conduction type of high impurity concentration do not wait each other.
13. varicap according to claim 10 is characterized in that, in the semiconductor regions of second conduction type with high impurity concentration, with its side surface portion with respect to the area of basal surface part than being arranged in 0.08～0.18 the scope.
14. varicap according to claim 10 is characterized in that, in the semiconductor regions of second conduction type with high impurity concentration, its side surface portion is set to 0.13 with respect to the area ratio of basal surface part.
15. varicap according to claim 10, it is characterized in that, have spacing between the contact layer of the semiconductor regions of second conduction type of high impurity concentration and first conduction type and be equal to or greater than width, and be equal to or less than width with the formed depletion layer of maximum voltage of employed reverse biased with the formed depletion layer of minimum voltage of employed reverse biased.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003416209A JP2005175351A (en) | 2003-12-15 | 2003-12-15 | Method for manufacturing semiconductor device |
| JP2003416209 | 2003-12-15 | ||
| JP2004110683 | 2004-04-05 | ||
| JP2004110683A JP4203581B2 (en) | 2004-04-05 | 2004-04-05 | Balicap |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1630102A CN1630102A (en) | 2005-06-22 |
| CN100442542C true CN100442542C (en) | 2008-12-10 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004101011103A Expired - Fee Related CN100442542C (en) | 2003-12-15 | 2004-12-14 | Method of manufacturing variable capacitance diode and variable capacitance diode |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US7321158B2 (en) |
| KR (1) | KR100629194B1 (en) |
| CN (1) | CN100442542C (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7256081B2 (en) * | 2005-02-01 | 2007-08-14 | International Business Machines Corporation | Structure and method to induce strain in a semiconductor device channel with stressed film under the gate |
| US7769443B2 (en) | 2006-09-06 | 2010-08-03 | Giancarlo Barolat | Implantable reel for coiling an implantable elongated member |
| US8554337B2 (en) * | 2007-01-25 | 2013-10-08 | Giancarlo Barolat | Electrode paddle for neurostimulation |
| US8549015B2 (en) | 2007-05-01 | 2013-10-01 | Giancarlo Barolat | Method and system for distinguishing nociceptive pain from neuropathic pain |
| JP5127390B2 (en) * | 2007-10-12 | 2013-01-23 | キヤノン株式会社 | Signal processing apparatus, signal processing method, and program |
| US8214057B2 (en) | 2007-10-16 | 2012-07-03 | Giancarlo Barolat | Surgically implantable electrodes |
| US8513083B2 (en) | 2011-08-26 | 2013-08-20 | Globalfoundries Inc. | Methods of forming an anode and a cathode of a substrate diode by performing angled ion implantation processes |
| RU167582U1 (en) * | 2016-06-08 | 2017-01-10 | Акционерное общество "Научно-исследовательский институт микроприборов-К" | Microwave TIR-VARIKAP WITH CHARGE TRANSFER |
| RU192894U1 (en) * | 2019-07-09 | 2019-10-04 | Федеральное государственное автономное образовательное учреждение высшего образования "Национальный исследовательский университет "Московский институт электронной техники" | Microwave mdp varicap |
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| US4507159A (en) * | 1981-10-07 | 1985-03-26 | Advanced Micro Devices, Inc. | Method of manufacturing high capacity semiconductor capacitance devices |
| US5017950A (en) * | 1989-01-19 | 1991-05-21 | Toko, Inc. | Variable-capacitance diode element having wide capacitance variation range |
| JPH0897443A (en) * | 1994-09-22 | 1996-04-12 | Toko Inc | Manufacture of semiconductor device |
| CN1165586A (en) * | 1995-09-18 | 1997-11-19 | 菲利浦电子有限公司 | Varicap diode and method of manufacturing a varicap diode |
| JPH1168124A (en) * | 1997-08-22 | 1999-03-09 | Toyota Autom Loom Works Ltd | Semiconductor device and its manufacture |
| US6339249B1 (en) * | 1998-10-14 | 2002-01-15 | Infineon Technologies Ag | Semiconductor diode |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5678174A (en) | 1980-11-10 | 1981-06-26 | Hitachi Ltd | Variable capacity diode |
| JP2003158199A (en) | 2001-11-26 | 2003-05-30 | Kawasaki Microelectronics Kk | Semiconductor device and its manufacturing method |
-
2004
- 2004-12-14 CN CNB2004101011103A patent/CN100442542C/en not_active Expired - Fee Related
- 2004-12-15 KR KR1020040106215A patent/KR100629194B1/en not_active IP Right Cessation
- 2004-12-15 US US11/011,037 patent/US7321158B2/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4507159A (en) * | 1981-10-07 | 1985-03-26 | Advanced Micro Devices, Inc. | Method of manufacturing high capacity semiconductor capacitance devices |
| US5017950A (en) * | 1989-01-19 | 1991-05-21 | Toko, Inc. | Variable-capacitance diode element having wide capacitance variation range |
| JPH0897443A (en) * | 1994-09-22 | 1996-04-12 | Toko Inc | Manufacture of semiconductor device |
| CN1165586A (en) * | 1995-09-18 | 1997-11-19 | 菲利浦电子有限公司 | Varicap diode and method of manufacturing a varicap diode |
| JPH1168124A (en) * | 1997-08-22 | 1999-03-09 | Toyota Autom Loom Works Ltd | Semiconductor device and its manufacture |
| US6339249B1 (en) * | 1998-10-14 | 2002-01-15 | Infineon Technologies Ag | Semiconductor diode |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1630102A (en) | 2005-06-22 |
| KR20050060022A (en) | 2005-06-21 |
| US20050148149A1 (en) | 2005-07-07 |
| KR100629194B1 (en) | 2006-09-28 |
| US7321158B2 (en) | 2008-01-22 |
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