JP2005210005A - Semiconductor device, and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and the manufacturing method thereof which includes a varactor having a large variable-capacitance range. <P>SOLUTION: The semiconductor device has a gate electrode 105 formed above an N-well 101 via an insulating film 103 and has a counter impurity layer 108 formed by introducing a p-type impurity into the surface region of the n-well 101 which is present under the gate electrode 105. Further, there is included in the device a varactor for generating a capacitance by the gate electrode 105 and the counter impurity layer 108. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a structure and a manufacturing method of a voltage variable capacitor (varactor), in particular, a MOS (Metal Oxide Semiconductor) type varactor manufactured using an existing CMOS (Complementary Metal Oxide Semiconductor) process.

  Conventionally, a varactor that is a voltage variable capacitor has been widely used in many radio frequency (RF) circuits.

  As a known structure for realizing a varactor, there is a structure using a depletion layer capacitance of a PN junction, specifically, a varactor diode. Here, as an index for evaluating the performance of the varactor, in the case of the PN junction capacity varactor as described above, a tuning ratio is often used. The tuning ratio is a ratio (C2 / C1) between the capacitance C2 at a predetermined PN junction reverse bias V2 and the capacitance C1 (C1> C2) at another predetermined reverse bias V1 (V1 <V2). The larger the tuning ratio, the larger the capacitance change is possible with a constant voltage width applied to the varactor, and the wider the resonance frequency range of the antenna that can be controlled in the RF integrated circuit.

  FIG. 11 is a diagram showing the bias voltage dependency of the capacitance of the PN junction varactor diode. In the PN diode, when the reverse bias voltage applied to the PN junction is increased from V1 to V2, the depletion layer width at the PN junction increases, and thus the capacitance decreases. As is well known, the depletion layer width depends on the impurity concentration. When the impurity concentration increases, the depletion layer width decreases and the capacitance C2 increases. Therefore, in order to increase the depletion layer width for the purpose of obtaining a small C2, in the case of a PN junction varactor, the applied voltage must be increased. Therefore, a PN junction varactor is not suitable for an integrated circuit of low voltage and low power consumption that is often used recently.

  In recent years, there has been a growing demand for circuit miniaturization, and there is a demand for mounting a CMOS device and a varactor on one chip. For this purpose, MOS type varactors that can be formed in substantially the same manufacturing process as CMOS are advantageous and have been widely used. This type of varactor utilizes the gate voltage dependency of a MOS type capacitor. For example, when formed on an N-type substrate, the capacitance changes with respect to the applied voltage as shown in FIG. In the MOS type varactor, as is apparent from FIG. 12, the ratio of the capacitance Cmax at the predetermined positive bias V3 and the capacitance Cmin at the negative bias −V3 can be set as the tuning ratio (Cmax / Cmin). That is, since the capacitance can be changed using both positive voltage and negative voltage, a sufficient operation can be performed with a power supply voltage that is ½ of the voltage change width 2V3. This characteristic means that even when the semiconductor device is highly integrated and the power supply voltage is lowered, a large tuning ratio can be secured with a small voltage width. Therefore, a MOS capacitor that functions as a varactor is formed using an existing CMOS process.

  FIG. 12 shows the bias voltage dependency of the capacity of an ideal varactor (MOS capacitor). In a MOS capacitor, when a negative bias −V3, which is a direction in which carrier depletion proceeds on the surface of an N-type Si substrate, is applied to the gate electrode, the width of the depletion layer increases, and the capacitance C decreases.

  Further, when the bias voltage is in a certain range, the capacitance C varies greatly depending on the bias voltage. However, when the bias voltage is larger or smaller than this range, the dependency of the capacitance C on the bias voltage is reduced, and the capacitance C has a substantially constant value regardless of the bias voltage.

  Here, a range in which the capacitance C greatly changes depending on the bias voltage is referred to as a capacitance variable region. In order to make maximum use of the capacity variable region under the condition that the bias voltage takes a value from −V3 to V3, the bias voltage when the capacity C becomes the average capacity of the capacity Cmax and the capacity Cmin is set as the center voltage Vc, and the center The closer the voltage Vc is to 0, the better. This is because when the center voltage Vc shifts from 0 to either positive or negative, the gate voltage V3 or -V3 enters the region where the capacitance C hardly changes after leaving the capacitance variable region, and the capacitance change is small for the voltage change width. Because it becomes.

  Further, the depletion layer width and the center voltage Vc depend on the impurity concentration on the surface of the Si substrate, as is well known from the CV characteristics of the MOS capacitor. As the impurity concentration increases, the capacitance Cmin increases due to the narrowing of the depletion layer width and a slight shift of the center voltage Vc to the negative bias side occurs.

  FIG. 13 is a cross-sectional view showing a conventional semiconductor device on which a CMOS device and a varactor (MOS capacitor) are mounted. The configuration of the semiconductor device will be described below.

  An N well 11 doped with N type impurities is formed on a P type Si substrate 10. Further, an STI (Shallow Trench Isolation) 12 is formed on the P-type Si substrate, and the surface portion of the P-type Si substrate 10 is partitioned into a plurality of active regions. As the plurality of active regions, there are a transistor formation region Tr in which a MOSFET (Metal Oxide Semiconductor Feild Effect Transistor) in a CMOS device is provided, and a varactor formation region Va in which a varactor is provided. However, MOSFETs in a CMOS device include an N-type MOSFET and a P-type MOSFET, but FIG. 13 shows only a region where a P-type MOSFET is formed.

  A first gate electrode 14 is formed on the P-type Si substrate 10 in the transistor formation region Tr via a gate insulating film 13. The first gate electrode 14 is made of polysilicon doped with a P-type impurity. A second gate electrode 15 is formed on the P-type Si substrate 10 in the varactor formation region Va via a gate transfer insulating film 13. The second gate electrode 15 is made of polysilicon doped with an N-type impurity.

  Source / drain regions doped with P-type impurities (source region and drain region are collectively referred to as such) 16 are formed in regions on both sides of the first gate electrode 14 in the transistor formation region Tr. Yes. Further, substrate contact regions 17 doped with N-type impurities are formed in regions on both sides of the second gate electrode 15 in the varactor formation region Va.

  An interlayer insulating film 18 is formed so as to cover the P-type Si substrate 10, the N well 11, the STI 12, the gate insulating film 13, the first gate electrode 14, the second gate electrode 15, the source / drain region 16 and the substrate contact region 17. Is formed. A contact hole (not shown) is formed in the interlayer insulating film 18.

  The structure shown in FIG. 13 is formed by the following manufacturing process.

  First, an N well 11 and an STI 12 are formed on a P-type Si substrate 10. Thereafter, a common gate insulating film 13 is formed in the transistor formation region Tr and the varactor formation region Va. Next, a first gate electrode 14 made of polysilicon doped with a P-type impurity is formed on the P-type Si substrate 10 via a gate insulating film 13 in the transistor formation region Tr. Subsequently, using the first gate electrode 14 as a mask, ion implantation of P-type impurities is performed to form source / drain regions 16.

  Next, in the varactor formation region Va, a second gate electrode 15 made of polysilicon doped with N-type impurities is formed on the P-type Si substrate 10 via a gate insulating film 13. Subsequently, using the second gate electrode 15 as a mask, N-type impurity ions are implanted to form a substrate contact region 17.

  Since the conventional semiconductor device includes a CMOS device, it includes an N-type MOSFET (not shown) in addition to the P-type MOSFET shown. Therefore, the substrate contact region 17 is formed in the same process as the source / drain region formation of the N-type MOSFET in the CMOS device.

  As described above, each member of the semiconductor device having the structure shown in FIG. 13 can be formed by using an existing CMOS device manufacturing process.

  Although FIG. 13 shows one varactor, when the entire varactor is viewed in plan, the pattern layout is as shown in FIG. The second gate electrode 15 of the varactor formed on the region sandwiched between the N-well substrate contact regions 17 is divided into a plurality of pieces so that the width of each of the second gate electrodes 15 is reduced, and is electrically connected to each other. . In order to apply a voltage to the varactor, a first contact hole 19 is formed on the second gate electrode 15, and a second contact hole 20 is formed on the substrate contact region 17.

  In principle, the gate electrode of the varactor may be a single gate electrode having an area capable of obtaining a predetermined capacitance. However, when the operating frequency of the integrated circuit is in the region of, for example, several GHz, the resistance of the electrode cannot be ignored, which adversely affects noise characteristics and the like. Since the influence of resistance becomes more conspicuous as the electrode is larger, the influence of resistance is mitigated by dividing the gate electrode into a plurality of narrow gate electrodes whose total area is an area where a predetermined capacitance can be obtained. At the same time, the gate electrodes divided into a plurality are electrically connected to each other, and the second contact hole 20 is placed in the gap.

In addition, the resistance of the gate electrode is reduced by replacing the polysilicon as described above with a two-layer structure of a refractory metal silicide and polysilicon.
JP-A-9-121025

  However, the varactor structure using the existing CMOS process has the following problems.

  As the pattern size of transistors progresses, the substrate impurity concentration is increased according to the scaling law. At this time, the impurity concentration on the surface of the Si substrate is optimized with respect to the transistor characteristics. Therefore, also in the varactor forming region Va of FIG. 13, the impurity concentration on the surface of the N well 11 is a relatively high value equivalent to that of the N well 11 in the transistor forming region Tr. For this reason, the spread of the depletion layer is suppressed, and as a result, the capacitance value Cmin increases. At the same time, when the average voltage between the applied voltage Vmin when the capacitance value Cmin is indicated and the applied voltage Vmax when the capacitance value Cmax is indicated as the center voltage Vc, the center voltage Vc is greatly increased from zero to the negative bias side. shift. For this reason, it becomes difficult to apply positive and negative voltages so that the capacitance change has the maximum width.

  Further, the tuning ratio Cmax / Cmin of the varactor in the semiconductor device formed by the conventional manufacturing process tends to decrease as the substrate impurity concentration increases as described above, and the gate length Lg is short. There is also a tendency to decrease as it becomes. For this reason, with a varactor having a small gate electrode width, it is difficult to obtain desired varactor performance that is necessary for obtaining good high-frequency characteristics. The decrease in the tuning ratio accompanying the reduction in the gate length Lg is considered to be caused by the fringing capacitance between the side wall of the second gate electrode 15 and the substrate contact region 17.

  This will be described with reference to FIG. 15, which is an equivalent circuit diagram of the varactor shown in FIG. As shown in FIG. 15, in the periphery of the second gate electrode 15 of this varactor, in addition to the gate insulating film capacitance Cox and the depletion layer capacitance Cdep, the side wall of the second gate electrode 15 and the substrate contact region 17 A fringing capacitance Cf is generated with the interlayer insulating layer 18 interposed therebetween. Here, as the width of the second gate electrode 15 decreases, the gate insulating film capacitance Cox and the depletion layer capacitance Cdep decrease accordingly. However, the fringing capacitance Cf is constant regardless of the reduction in the width of the second gate electrode 15. Therefore, when the width of the second gate electrode 15 is reduced and the gate insulating film capacitance Cox and the depletion layer capacitance Cdep are reduced, the influence of the fringing capacitance Cf, which is a constant in the capacitance of the varactor, is relatively increased. As a result, when the width of the second gate electrode 15 is reduced, the relative change in the varactor capacitance with respect to the change in the bias voltage is reduced. That is, the varactor tuning ratio Cmax / Cmin is reduced.

  Further, since the varactor capacity depends on the length of the gate length Lg, the varactor capacity varies depending on the finished dimension variation of the gate length Lg.

  The present invention solves the above problems. That is, an object of the present invention is to provide a semiconductor device in which a varactor is mounted together with a CMOS device and a manufacturing method thereof using an existing CMOS process, and even if one gate electrode has a small area, An object is to provide a high-performance varactor capable of increasing the depletion layer width below the gate electrode.

  In order to achieve the above object, the first semiconductor device of the present invention changes the voltage applied to the gate electrode formed on the first conductivity type semiconductor region via the insulating film, thereby changing the first semiconductor device. A semiconductor device that realizes a varactor function by changing a capacitance of a depletion layer generated in a conductive semiconductor region, wherein a second conductive impurity is introduced into a lower portion of the gate electrode in the first conductive semiconductor region. The counter impurity layer formed by (1) is provided.

  Here, the first conductivity type semiconductor region means a well or semiconductor substrate having the first conductivity type. Further, the well or semiconductor substrate having the second conductivity type is referred to as a second conductivity type semiconductor region. As for the well, only one of the first conductivity type well and the second conductivity type well may be formed, or both may be formed.

  The first semiconductor device includes a counter impurity layer into which a second conductivity type impurity is introduced in a surface region below the gate electrode of the varactor in the first conductivity type semiconductor region. That is, the second conductivity type impurity is introduced in addition to the first conductivity type impurity included in the first conductivity type semiconductor region, and the effective impurity concentration is lowered in the counter impurity layer. Here, the effective impurity concentration refers to the absolute value of the difference between the first conductivity type impurity concentration and the second conductivity type impurity concentration. With such a configuration, since the effective impurity concentration is lowered, the carrier concentration is lowered. For this reason, even when the impurity concentration of the first conductive type semiconductor region is high, the spread width of the depletion layer below the gate electrode of the varactor can be increased. Therefore, even when the impurity concentration of the first conductivity type semiconductor region is increased due to the miniaturization of the pattern size of the semiconductor element or the like, a semiconductor device including a varactor having a wide capacitance variable range can be realized.

  The second semiconductor device of the present invention is generated in the first conductivity type semiconductor region by changing the voltage applied to the plurality of gate electrodes formed on the first conductivity type semiconductor region via the insulating film. A semiconductor device that realizes a varactor function by changing a capacitance of a depletion layer, the counter being formed by introducing a second conductivity type impurity into a lower portion of a plurality of gate electrodes in a first conductivity type semiconductor region An impurity layer is provided.

  According to the second semiconductor device, the same effect as that of the first semiconductor device can be realized. In addition, by using a plurality of small-area gate electrodes, the influence of the resistance of the gate electrode can be reduced as compared with the case of using a single large-area gate electrode.

  In the second semiconductor device, an interlayer insulating film that covers the first conductivity type semiconductor region and the plurality of gate electrodes is formed, and at least reaches the first conductivity type semiconductor region in a portion between the plurality of gate electrodes. One contact hole may be provided.

  In this way, the effect of the second semiconductor device can be used reliably.

  In the first semiconductor device and the second semiconductor device, the counter impurity layer is preferably substantially an intrinsic semiconductor region. Here, the fact that the counter impurity layer is substantially an intrinsic semiconductor region means that the concentration of the introduced first conductivity type impurity and the concentration of the second conductivity type impurity are equal (in other words, effective It means that the counter impurity layer has intrinsic semiconductor properties).

  In the first semiconductor device and the second semiconductor device, it is preferable that the counter impurity layer substantially has the second conductivity type. Here, the fact that the counter impurity layer substantially has the second conductivity type means that the concentration of the second conductivity type impurity in the counter impurity layer is higher than the concentration of the introduced first conductivity type impurity. Say that.

  In this way, even when the impurity concentration of the first conductivity type semiconductor region is high, the effect of the present invention of forming a varactor having a wide capacitance variable range can be realized with certainty.

  In the first semiconductor device and the second semiconductor device, the maximum of the varactor when a voltage in a predetermined range is applied between the gate electrode and the first conductivity type semiconductor region below the gate electrode. The effective impurity concentration of the counter impurity layer is set to a predetermined value so that an applied voltage (referred to as a center voltage) that generates an average capacitance between the capacitance and the minimum capacitance takes a value near zero and does not substantially depend on the gate length of the gate electrode. The concentration is preferably set.

  In this manner, even if the gate length of the gate electrode varies in the manufacturing process, the variable range of the capacitance is maximized at any gate length, so that the variation in the varactor capacitance can be minimized. Even if the gate length design is changed, the varactor tuning ratio Cmax / Cmin can be kept at the maximum.

  Here, the value near zero means a value of −0.05 V or more and 0.05 V or less, for example. Further, the fact that the center voltage does not substantially depend on the gate length means that the fluctuation range of the center voltage accompanying the change in the gate length is 1% or less of the voltage width applied to the varactor.

  Specifically, the carrier having the second conductivity type accumulates on the surface of the counter impurity layer when a bias in a direction in which depletion of the first conductivity type carrier proceeds on the semiconductor substrate surface is applied. The starting concentration is preferred.

  With such a concentration, even if variations occur in the gate length of the gate electrode in the manufacturing process, the variable range of capacitance is maximized at any gate length, so that variation in varactor capacitance can be minimized. You can be sure. Even if the gate length design is changed, the tuning ratio Cmax / Cmin of the varactor can be reliably kept at the maximum.

  The method for manufacturing a semiconductor device according to the present invention includes a first step of forming a counter impurity layer by introducing a second conductivity type impurity into a first conductivity type semiconductor region of a varactor formation region, and a first step in the transistor formation region. A second step of forming a first gate electrode on the conductive type semiconductor region and forming a second gate electrode on the first conductive type semiconductor region in the varactor forming region; A third step of forming a source / drain region by introducing a second conductivity type impurity into the portions on both sides of the first gate electrode of the one conductivity type semiconductor region using the first gate electrode as a mask; and a varactor formation region In the substrate, the first conductivity type impurity is introduced into the portions on both sides of the second gate electrode of the first conductivity type semiconductor region by using the second gate electrode as a mask. And a fourth step of forming a Ntakuto region.

  According to the method for manufacturing a semiconductor device of the present invention, the counter impurity layer is formed by introducing the second conductivity type impurity into the first conductivity type semiconductor region in the varactor formation region. For this reason, even when the impurity concentration of the first conductivity type semiconductor region is high, it is possible to manufacture a semiconductor device in which the spread width of the depletion layer under the gate electrode of the varactor is large. Thus, even when the impurity concentration of the first conductivity type semiconductor region is high, a semiconductor device including a varactor having a wide capacitance variable range, that is, a large tuning ratio can be manufactured.

  Prior to the second step, the method further includes a step of forming an insulating film on the first conductivity type semiconductor region, and the second step includes a step of forming a conductive film on the insulating film, Preferably, the method includes a step of forming the first gate electrode and the second gate electrode by selectively removing and patterning.

  In this way, the semiconductor device of the present invention can be reliably manufactured.

  A fifth step of forming a third gate electrode on the second conductive type semiconductor region of the other transistor forming region; and a third gate electrode of the second conductive type semiconductor region in the other transistor forming region. A sixth step of forming another source / drain region by introducing a first conductivity type impurity into the portions on both sides using the third gate electrode as a mask, and a fourth step and a sixth step. Are preferably performed simultaneously.

  In this way, the semiconductor device of the present invention can be manufactured without the need for adding a step for forming the substrate contact region to the existing CMOS device manufacturing process.

  According to the present invention, since the effective impurity concentration is reduced by introducing impurities of the opposite conductivity type into the semiconductor substrate or well below the gate electrode of the varactor, the semiconductor substrate or well is used for miniaturization of pattern dimensions, etc. Even when the impurity concentration is high, the width of the depletion layer when the gate voltage is applied can be increased and the capacitance can be reduced. This makes it possible to increase the tuning ratio. In addition, by a simple method of adjusting the effective impurity concentration, it is possible to improve the performance of a varactor element having a short gate length, and to suppress the influence of the varactor capacitance from variations in the finished dimension of the gate length.

  Hereinafter, a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a cross-sectional view showing the structure of a semiconductor device according to the present embodiment, specifically, a semiconductor device in which a varactor (MOS capacitor) and a CMOS device are mixedly mounted. In particular, a semiconductor element having a small size such as an FET is provided. Is.

  As shown in FIG. 1, an N well 101 doped with N type impurities is formed on the surface of a P type Si substrate 100. Further, an STI 102 is formed on the P-type Si substrate 100, and the surface portion of the P-type Si substrate 100 is partitioned into a plurality of active regions. The plurality of active regions include a transistor formation region Tr in which a MOSFET in the CMOS device is provided and a varactor formation region Va in which a varactor is provided. However, MOSFETs in a CMOS device include an N-type MOSFET and a P-type MOSFET, but only the P-type MOSFET is shown in FIG.

  A first gate electrode 104 is formed on the N well 101 in the transistor formation region Tr via a gate insulating film 103 made of, for example, a silicon oxynitride film. The first gate electrode 104 is made of, for example, polysilicon doped with a P-type impurity. A second gate electrode 105 is formed on the N well 101 in the varactor formation region Va via a gate insulating film 103 made of, for example, a silicon oxynitride film. The second gate electrode 105 is made of, for example, polysilicon doped with an N-type impurity.

  In the transistor formation region Tr, source / drain regions 106 doped with P-type impurities are formed on both sides of the first gate electrode 104 on the N well 101. A substrate contact region 107 doped with an N-type impurity is formed on both sides of the second gate electrode 105 of the N well 101 in the varactor formation region Va.

  A counter impurity layer 108 into which a P-type impurity is introduced is provided below the second gate electrode 105 on the N well 101 in the varactor formation region Va.

  Further, an interlayer insulating film 109 is formed so as to cover the pattern of the first gate electrode 104 and the second gate electrode 105 formed on the P-type Si substrate 100. Although not shown in FIG. 1, a contact hole is formed at a predetermined position of the interlayer insulating film 109. As shown in FIG. 3, the contact hole includes a first contact hole 110 reaching the second gate electrode 105 and a second contact hole 111 reaching the substrate contact region 107.

  FIG. 2 shows the impurity concentration distribution in the counter impurity layer 108 with respect to the depth from the surface of the P-type Si substrate 100. In FIG. 2, N (101) indicates the concentration distribution of the N-type impurity introduced for forming the N well 101 of FIG. P (108) indicates the concentration distribution of the P-type impurity introduced to form the counter impurity layer 108 in FIG.

  As described above, the semiconductor device of this embodiment includes the counter impurity layer 108 in which the P-type impurity is introduced into the surface region of the N well 101 under the gate electrode of the varactor. That is, the counter impurity layer 108 is formed by further introducing a P-type impurity into the N well 101 into which the N-type impurity has been introduced. For this reason, since both the N-type impurity and the P-type impurity exist in the counter impurity layer 108, the substantial carrier concentration is lowered.

  For this reason, even when the power supply voltage of the semiconductor device on which the varactor is mounted is determined and the N-type impurity concentration of the N well is increased in accordance with the miniaturization of the pattern size of the semiconductor element, the gate of the varactor The spread of the depletion layer on the lower side of the electrode can be increased. As a result, it is possible to realize a varactor having a wide capacitance variable range, in other words, a varactor having a large tuning ratio.

  In FIG. 1, the second gate electrode 105 is shown as one gate electrode as a cross-sectional view. However, the pattern layout on the plane of the second gate electrode 105 may be divided into a plurality of narrow gate electrodes that are electrically connected to each other as shown in FIG. . At this time, the total area of each second gate electrode 105 is an area where a predetermined varactor capacitance is obtained. In addition, an interlayer insulating film 109 (not shown) covering the second gate electrode 105 and the substrate contact region 107 is provided with a first contact hole 110 and a substrate contact for establishing electrical connection with the second gate electrode 105. A second contact hole 111 for establishing electrical connection with the region 107 is formed.

  In this way, the influence of the resistance on the second gate electrode 105 can be alleviated and the effect of the present invention can be realized. Since the influence of resistance becomes more conspicuous as the electrode is larger, the influence of resistance can be reduced by using a plurality of smaller electrodes.

  The reason why a varactor having a large tuning ratio can be realized by this embodiment will be further described with reference to FIG.

  FIG. 4 is a graph showing experimental results showing the capacity change characteristics of the varactor. The curve a shows the capacity change characteristics of the varactor according to the present invention, and the curve b shows the capacity change characteristics of the conventional varactor. 4 represents the gate bias voltage Vg, and the vertical axis represents the varactor capacitance C.

  If the common internal power supply voltage in the integrated circuit of this embodiment is 1.5 V, the varactor must be driven within the voltage range. In this case, the maximum value Cmax and the minimum value Cmin of the capacity of the varactor are the capacities shown when the gate bias is 0.75 V and -0.75 V, respectively, which is half of 1.5V. The ratio (Cmax / Cmin) between the maximum value Cmax and the minimum value Cmin of the capacity of the varactor is the tuning ratio and indicates the size of the variable range of the capacity.

  As shown in FIG. 4, by performing P-type impurity implantation (referred to as counter impurity implantation) into the N-well 101 below the second gate electrode 105 of the varactor, the minimum value Cmin ( a) is lower than the minimum value Cmin (b) of the capacity of the varactor of the conventional semiconductor device, and the variable range of the capacity is expanded. For this reason, the amount of change in capacitance with respect to the amount of change in Vg in the capacitance variable range increases.

  The power supply voltage may be designed to a required value for each semiconductor device, and is not limited to 1.5 V as in this embodiment. Therefore, the maximum value 0.75 V and the minimum value −0.75 V of the applied voltage are not limited to these values. The same applies to the following description.

  Further, the voltage Vc (a) that generates the center capacitance of the maximum value Cmax and the minimum value Cmin (a) of the varactor of the present invention with respect to the applied voltage in a predetermined range is the voltage Vc (b) that generates the center capacitance in the conventional varactor. ) Compared to), it can be shifted to the positive bias side and set to almost zero. This is also a factor that can increase the tuning ratio.

  Next, the absolute value of the difference between the N-type impurity concentration and the P-type impurity concentration is considered as the effective impurity concentration on the substrate surface of the counter impurity layer 108 in the varactor region Va. When the P-type impurity concentration is higher than the N-type impurity concentration, the counter impurity layer 108 or the substrate surface of the region Va is substantially P-type. In addition, a state where the effective impurity concentration is almost zero is referred to as an intrinsic semiconductor state.

  In order to maximize the tuning ratio, it is preferable that the substrate surface under the second gate electrode 105 of the varactor has an effective impurity concentration of almost 0, that is, a substantially intrinsic semiconductor state. It is also preferable that the P-type, that is, the N-well 101 is of the opposite conductivity type to the N-type.

  In this way, a semiconductor device having a varactor with a large tuning ratio can be realized. This will be described with reference to FIG.

  FIG. 5 is a graph showing the dependence of the depletion layer width under the second gate electrode 105 of the varactor on the effective impurity concentration on the substrate surface. This graph shows a case where the applied voltage between the N-type well region 101 and the second gate electrode 105 is −0.75 V and the gate length Lg is 0.5 μm. As shown in FIG. 5, the width of the depletion layer continues to increase as the substrate surface (counter impurity layer 108 in FIG. 1) moves from N-type to P-type. Therefore, as shown in FIG. 4 above, Cmin can be lowered by performing counter impurity implantation. Thus, it is preferable that the substrate surface of the counter impurity layer 108 is substantially in a true semiconductor state or substantially P-type because a varactor with a high tuning ratio can be realized.

  The gate length Lg is not particularly limited, and may be a value other than 0.5 μm. Even in this case, it is possible to set the effective impurity concentration so that the substrate surface of the counter impurity layer 108 is substantially in a true semiconductor state.

  FIG. 6 shows the dependence of the varactor tuning ratio on the effective impurity concentration on the substrate surface. Here, as an example, the case where the gate length Lg of the second gate electrode 105 is 0.5 μm is shown. As FIG. 6 shows, the tuning ratio increases as the substrate surface substantially transitions from N-type to P-type, but saturates at a certain concentration.

  This is considered to be due to the following reason. That is, as the substrate surface becomes substantially P-type, holes are more likely to accumulate on the Si substrate surface when the applied gate voltage is negative. As a result, when a negative gate voltage is applied, the charge density on the substrate surface remains high, and therefore Cmin does not decrease much. For this reason, it is considered that the increase in the tuning ratio is saturated at a certain effective impurity concentration as described above.

FIG. 7 shows the result of a simulation for obtaining the depletion layer width when a bias is applied to the second gate electrode 105 in the negative direction. The simulation is performed under the condition that the effective impurity concentration on the substrate surface is 1 × 10 ¹⁷ / cm ^{3. As} shown in FIG. 6, the tuning ratio is almost saturated with respect to the impurity concentration. .

As shown in FIG. 7, when the negative gate bias is larger than −0.75 V, the increase in the width of the depletion layer accompanying the increase in voltage is reduced. For this reason, in the range where the bias voltage is greater than −0.75, the decrease in capacity due to the increase in voltage is reduced. That is, the capacity when the bias voltage is around -0.75 is Cmin. Therefore, when the driving voltage of the varactor is ± 0.75 V, the effective impurity concentration on the substrate surface is preferably 1 × 10 ¹⁷ / cm ³ or more. In this way, the variable capacity region of the varactor can be utilized to the maximum extent.

  Further, a bias voltage that generates a center capacitance of the maximum value Cmax and the minimum value Cmin for the applied voltage in a predetermined range of the varactor is defined as a center voltage Vc. It is preferable to determine the effective impurity concentration of the counter impurity layer 108 so that the center voltage Vc takes a value near zero and does not substantially depend on the gate length Lg of the second gate electrode 105. Here, the value near zero means a value of −0.05 V or more and 0.05 V or less, for example. Further, the fact that the center voltage does not substantially depend on the gate length means that the fluctuation range of the center voltage accompanying the change in the gate length is 1% or less of the voltage width applied to the varactor.

  In this way, the tuning ratio can be kept at the maximum regardless of the set value of the gate length Lg of the second gate electrode 105. This and a specific effective impurity concentration will be described with reference to FIG.

  FIG. 8 shows the dependence of the central voltage Vc on the effective impurity concentration on the substrate surface with respect to four gate lengths Lg (Lg = 10 μm, Lg = 0.5 μm, Lg = 0.3 μm and Lg = 0.15 μm). It shows. As shown in FIG. 8, when the counter impurity layer 108 is substantially P-type and the effective impurity concentration is a certain value, the center voltage Vc is substantially constant regardless of Lg. You can see that it takes a value. The center voltage is actually a value of −0.05 V or more and 0.05 V or less.

  The effective impurity concentration of the counter impurity layer 108 at this time coincides with the concentration at which carriers having the conductivity type opposite to the N well start to accumulate on the substrate surface of the counter impurity layer 108. In this embodiment, since the N well 101 is N-type, it matches the concentration at which P-type carriers having the opposite conductivity type, that is, holes start to accumulate on the surface of the counter impurity layer 108. Furthermore, the concentration is also a concentration at which the tuning ratio starts to saturate with respect to the effective impurity concentration.

  In the present embodiment, the effective impurity concentration of the counter impurity layer 108 is preferably set to such a concentration. In this way, it is possible to reduce the variation in varactor capacity caused by the process variation of the gate length Lg of about 10% in the actual manufacturing process. Further, the tuning ratio Cmax / Cmin of the varactor can be kept at the maximum without being affected by the setting of the gate electrode length constituting the varactor and its change.

Specifically, in this embodiment, the counter impurity layer 108 is substantially P-type, and the effective impurity concentration starts to accumulate holes, which are carriers having a conductivity type opposite to that of the N well, on the substrate surface. It is preferable that the value is 1 × 10 ¹⁷ / cm ³ . However, the preferable effective impurity concentration differs for each semiconductor device, and the effective impurity concentration in the present invention is not limited to 1 × 10 ¹⁷ / cm ³ .

  Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. FIGS. 9A to 9C and FIGS. 10A and 10B are cross-sectional views showing respective steps of the method for manufacturing a semiconductor device of the present invention.

First, in the step shown in FIG. 9A, an N well 101 is formed by implanting an N type impurity such as phosphorus or arsenic into the P type Si substrate 100. The ion implantation conditions are, for example, a dose of 1 × 10 ¹³ cm ⁻² and an acceleration voltage of 640 keV for phosphorus, and a dose of 1.7 × 10 ¹² cm ⁻² and an acceleration voltage of 70 keV for arsenic.

  Further, the STI 102 is formed to partition the substrate surface into a plurality of active regions. The plurality of active regions include a transistor formation region Tr and a varactor formation region Va.

Next, in the step shown in FIG. 9B, in the varactor formation region Va, a P-type impurity having conductivity opposite to the impurity implanted to form the N well 101 in the N well 101, for example, boron. And so on. The conditions for implanting the counter impurity are, for example, a dose of 2 to 8 × 10 ¹² cm ⁻² and an acceleration voltage of 10 keV. When the boron dose is 3.5 × 10 ¹² cm ⁻² , the counter impurity layer 108 in the varactor formation region Va has substantially intrinsic semiconductor properties. This is because the number of donors introduced for forming the N well 101 and the number of acceptors introduced for forming the counter impurity layer 108 are substantially equal. When the boron dose is 3.5 × 10 ¹² cm ⁻² or more, the substrate surface of the counter impurity layer 108 is substantially P-type. In the present embodiment, the P-type impurity is implanted with such a dose amount that the substrate surface which is the counter impurity layer 108 is substantially P-type.

  Next, in the step shown in FIG. 9C, in the transistor formation region Tr and the varactor formation region Va, a silicon oxynitride film having a thickness of about 2.8 nm and a thickness of about 180 nm, for example, are formed on the N well 101. A polysilicon film is deposited. Subsequently, by patterning the polysilicon film and the silicon oxide film, the first gate electrode 104 and the second gate electrode 105 are formed on the N well with the gate insulating film 103 interposed therebetween. For the first gate electrode 104 and the second gate electrode 105, for example, the gate length Lg can be reduced to 0.15 μm. These film thicknesses and gate lengths Lg may be set as necessary and are not particularly limited.

  Next, in the step shown in FIG. 10A, in the transistor formation region Tr, the P-type impurity such as boron is formed on the both sides of the first well electrode 104 of the N well 101 using the first gate electrode 104 as a mask. Inject. In this manner, the P-type impurity is introduced into the first gate electrode 104, and the source / drain regions 106 are formed in a self-aligned manner.

  Next, in the step shown in FIG. 10B, in the varactor formation region Va, N-type impurities such as arsenic are formed on both sides of the second well electrode 105 of the N well 101 using the second gate electrode 105 as a mask. And inject phosphorus. In this manner, the N-type impurity is introduced into the second gate electrode 105 and the substrate contact region 107 is formed in a self-aligning manner.

  Next, an interlayer insulating film 109 is formed so as to cover patterns such as the first gate electrode 104, the second gate electrode 105, the source / drain region 106, and the substrate contact region 107 formed on the semiconductor substrate 100. . Further, although not shown, a contact hole is formed at a predetermined position of the interlayer insulating film 109.

  As described above, the semiconductor device of this embodiment can be manufactured using the existing manufacturing process for CMOS devices. That is, since the counter impurity layer 108 is formed under the second gate electrode 105, the spread width of the depletion layer under the second gate electrode 105 is large even when the impurity concentration of the N well 101 is high. A semiconductor device can be manufactured. For this reason, even when the impurity concentration of the N well 101 is high, a semiconductor device including a varactor having a wide capacitance variable range can be manufactured.

  Since the semiconductor device of this embodiment includes a CMOS device, an N-type MOSFET (not shown) is formed in addition to the P-type MOSFET shown in the figure. Therefore, the step of injecting the N-type impurity into the N well 101 using the second gate electrode 105 as a mask in the varactor forming region Va shown in FIG. 10B is performed by introducing impurities into the gate electrode of the N-type MOSFET and the N-type MOSFET. It is preferable to carry out simultaneously with the step of forming the source / drain.

  In this way, the semiconductor device of this embodiment can be manufactured without adding new processes for introducing the N-type impurity into the second gate electrode 105 and forming the substrate contact region 107.

  In addition, the implantation conditions such as the type of ions implanted in each step, the implantation amount, and the acceleration voltage are not limited to the above, and may be set as necessary. Furthermore, in this embodiment, ions are introduced by ion implantation, but may be introduced by other methods such as diffusion.

  In this embodiment, the N well 101 is formed, but the N well 101 is not an essential component, and a transistor or a varactor may be formed directly on the N-type semiconductor substrate.

  In the present embodiment, the first conductivity type is N-type and the second conductivity type is P-type. However, the first conductivity type opposite to this may be P-type and the second conductivity type may be N-type.

  The semiconductor device including the varactor of the present invention can be used for a voltage variable capacitor (varactor) used in a radio frequency (RF) circuit such as a voltage controlled oscillator.

It is a typical sectional view of a semiconductor device concerning one embodiment of the present invention. It is a figure which shows impurity concentration distribution with respect to the depth from a substrate surface in the counter impurity layer of the semiconductor device which concerns on one Embodiment of this invention. It is a figure which shows the planar layout pattern of the varactor of the semiconductor device which concerns on one Embodiment of this invention. It is a figure which shows an example of the capacitance-gate bias characteristic of the varactor of the semiconductor device which concerns on this invention, and the conventional varactor. It is a figure which shows the dependence of the depletion layer width with respect to the effective impurity density | concentration of the substrate surface in the varactor of the semiconductor device which concerns on one Embodiment of this invention. It is a figure which shows the dependence of the tuning ratio with respect to the effective impurity density | concentration of the substrate surface in the varactor of the semiconductor device which concerns on one Embodiment of this invention. It is a figure which shows the dependence of the depletion layer width with respect to gate bias in the varactor of the semiconductor device which concerns on one Embodiment of this invention. It is a figure which shows the dependence of the center voltage Vc with respect to the effective impurity density | concentration of the substrate surface in the varactor of the semiconductor device which concerns on one Embodiment of this invention. (A)-(c) is sectional drawing which shows each process from N well formation to gate electrode formation among the manufacturing processes of the semiconductor device which concerns on one Embodiment of this invention. (A) And (b) is sectional drawing which shows each process from the impurity implantation to N well to interlayer insulation film formation among the manufacturing processes of the semiconductor device which concerns on one Embodiment of this invention. It is a figure which shows typically the dependence with respect to the bias voltage of the capacity | capacitance in a general PN junction varactor diode. It is a figure which shows typically the bias voltage dependence of the capacity | capacitance of an ideal MOS type | mold varactor. It is typical sectional drawing of the semiconductor device carrying the conventional MOS type | mold varactor. It is a figure which shows typically the planar layout pattern of the conventional MOS type | mold varactor. It is an equivalent circuit diagram of a conventional MOS type varactor.

Explanation of symbols

100 P-type Si substrate 101 N well 102 STI
103 Gate insulating film 104 First gate electrode 105 Second gate electrode 106 Source / drain region 107 Substrate contact region 108 Counter impurity layer 109 Interlayer insulating film 110 First contact hole 111 Second contact hole Tr Transistor formation region Va Varactor formation area

Claims (10)

By changing the voltage applied to the gate electrode formed on the first conductive type semiconductor region through the insulating film, the capacitance of the depletion layer generated in the first conductive type semiconductor region is changed, thereby providing a varactor function. A semiconductor device to be realized,
A semiconductor device comprising: a counter impurity layer formed by introducing a second conductivity type impurity in a portion below the gate electrode in the first conductivity type semiconductor region. By changing the voltage applied to the plurality of gate electrodes formed on the first conductive type semiconductor region via the insulating film, the capacitance of the depletion layer generated in the first conductive type semiconductor region is changed to change the varactor. A semiconductor device that realizes a function,
A semiconductor device, comprising: a counter impurity layer formed by introducing a second conductivity type impurity into a lower portion of the plurality of gate electrodes in the first conductivity type semiconductor region. An interlayer insulating film covering the first conductive type semiconductor region and the plurality of gate electrodes;
The semiconductor device according to claim 2, further comprising at least one contact hole reaching the first conductivity type semiconductor region in a portion between the plurality of gate electrodes.   The semiconductor device according to claim 1, wherein the counter impurity layer is substantially an intrinsic semiconductor region.   The semiconductor device according to claim 1, wherein the counter impurity layer substantially has a second conductivity type.   Applied voltage that generates an average capacity of the maximum capacity and the minimum capacity of the varactor when a voltage in a predetermined range is applied between the gate electrode and the first conductive semiconductor region below the gate electrode. The effective impurity concentration of the counter impurity layer is set to a predetermined concentration so as not to substantially depend on the gate length of the gate electrode. The semiconductor device described.   7. The semiconductor device according to claim 6, wherein the predetermined concentration is a concentration at which carriers having the second conductivity type start to accumulate on the surface of the counter impurity layer. A first step of forming a counter impurity layer by introducing a second conductivity type impurity into the first conductivity type semiconductor region of the varactor forming region;
A second step of forming a first gate electrode on the first conductive type semiconductor region in the transistor forming region and forming a second gate electrode on the first conductive type semiconductor region in the varactor forming region; When,
In the transistor formation region, a source region and a drain region are formed by introducing a second conductivity type impurity into the portions on both sides of the first gate electrode of the first conductivity type semiconductor region using the first gate electrode as a mask. A third step of forming;
In the varactor formation region, a substrate contact region is formed by introducing a first conductivity type impurity into the portions on both sides of the second gate electrode of the first conductivity type semiconductor region using the second gate electrode as a mask. A semiconductor device manufacturing method comprising: a fourth step. Before the second step, further comprising a step of forming an insulating film on the first conductivity type semiconductor region,
In the second step, a conductive film is formed on the insulating film, and the conductive film is selectively removed and patterned to form the first gate electrode and the second gate electrode. The method for manufacturing a semiconductor device according to claim 8, further comprising: a forming step. A fifth step of forming a third gate electrode on the second conductivity type semiconductor region of the other transistor formation region;
In another transistor formation region, a first conductivity type impurity is introduced into both sides of the second conductivity type semiconductor region on both sides of the third gate electrode, using the third gate electrode as a mask, so that another source region and A sixth step of forming a drain region,
10. The method for manufacturing a semiconductor device according to claim 8, wherein the fourth step and the sixth step are performed simultaneously.

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