JP2005175351A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a method for manufacturing a semiconductor device which can minimize the number of additional steps in an LSI procedure and can form an accurate variable capacitance diode with less variations among such diodes. <P>SOLUTION: A mask material 4 is first formed on a p<SP>-</SP>semiconductor substrate 3 so that a variable capacitance diode formation region is opened. A B<SP>+</SP>ion implantation layer 5 is then formed by ion implantation so that the concentration peak of a p region 6 eventually forms a pn junction 8 with an n<SP>+</SP>region 10. Next, an As<SP>+</SP>ion implantation layer 9 is formed by ion implantation so that the concentration peak of the n<SP>+</SP>region 10 comes near to the surface of the p<SP>-</SP>semiconductor substrate 3. Finally, the mask material 4 is removed, and then heat treatment causes the B<SP>+</SP>ion implantation layer 5 and the As<SP>+</SP>ion implantation layer 9 to be activated, thus forming an anode layer 7 and a cathode layer 10 respectively. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which variable capacitance diodes are integrated with devices such as MOS transistors and bipolar transistors.

  In recent years, as mobile communication devices such as mobile phones are miniaturized, circuits including external components such as a frequency synthesizer (PLL) and a voltage controlled oscillator (VCO) have been rapidly made into one chip. In order to incorporate the VCO in the PLL semiconductor chip, it is necessary to integrate the variable capacitance diodes constituting the VCO circuit without impairing basic characteristics such as a low series resistance and a large capacitance change for a given voltage change. is there.

  2. Description of the Related Art Conventionally, as a variable capacitance diode formed on a semiconductor substrate, a variable capacitance diode that uses a depletion layer capacitance of a PN junction to control a capacitance value with an applied voltage is frequently used. In order to obtain a large capacitance change with respect to the applied voltage, the variable capacitance diode structure is made to be a super staircase junction in which the impurity concentration decreases with increasing distance from the PN junction surface, and the surface impurity concentration and impurity concentration profile of the region forming the PN junction It is important to optimize the above.

  Hereinafter, the structure of the variable capacitance diode described in Patent Document 1 and Patent Document 2 will be described as a conventional example.

FIG. 5 is a structural diagram of a conventional variable capacitance diode described in Patent Document 1, and FIG. 6 is an impurity concentration distribution along a CC line in FIG. In FIG. 5, 1 is an n semiconductor substrate, 15 is an n ⁻ region, 16 is an n region, 17 is an n ′ region, 18 is a cathode layer, 8 is a PN junction, 19 is an anode layer (p ⁺ region), and 12 is an interlayer. It is an insulating film. FIG. 7 is a structural diagram of a conventional variable capacitance diode described in Patent Document 2, and FIG. 8 is an impurity concentration distribution in a DD section in FIG. In FIG. 7, 1 is an n semiconductor substrate, 2 is a p ⁻ region, 6 is a p region, 7 is an anode layer, 8 is a PN junction, 10 is a cathode layer (n ⁺ region), 12 is an interlayer insulating film, and 11 is an anode. A contact layer, 14 is an anode electrode, and 13 is a cathode electrode.

  The operation of the variable capacitance diode configured as described above will be described below.

First, in FIG. 5, by applying a reverse bias to the PN junction 8, a variable capacitance diode is configured mainly using a depletion layer spreading in the cathode layer 18. Next, in FIG. 7, by applying a reverse bias to the PN junction 8, a variable capacitance diode is configured mainly using a depletion layer spreading in the anode layer 7.
Japanese Patent No. 1143905 JP-A-11-68124

  However, in the above-described conventional configuration, in the variable capacitance diode using the PN junction, first, with the miniaturization of the element, in FIG. 5, the anode layer is formed larger than the cathode layer (n region and n ′ region) due to the structure. In FIG. 7, the anode layer (p region) and the cathode layer are misaligned, which makes it difficult to improve accuracy. Next, when forming a variable capacitance diode having a large variable capacitance ratio, that is, a depletion layer capacitance having a large reverse bias voltage dependency, the concentration gradient of the n ′ region in the PN junction of FIG. 6 or the PN junction of FIG. Since the concentration gradient of the p region in each part is steep, the concentration variation of the PN junction due to manufacturing variations increases, and as a result, the variation of the variable capacitance ratio increases.

  SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems, and a semiconductor device capable of forming a highly accurate variable capacitance diode with minimal variation while minimizing an additional step of forming a variable capacitance diode in an LSI process. It aims at providing the manufacturing method of.

  In order to achieve this object, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a mask so that a variable capacitance diode forming region on a first conductivity type semiconductor substrate having a low impurity concentration is opened, Forming a first conductivity type semiconductor region having a medium impurity concentration in the opening of the mask by ion implantation; and forming a second conductivity type semiconductor region having a high impurity concentration in the opening of the mask; The semiconductor substrate is heat-treated to activate the first conductivity type semiconductor region having the medium impurity concentration and the second conductivity type semiconductor region having the high impurity concentration.

  With this configuration, first, the anode layer and the cathode layer of the variable capacitance diode are formed by ion implantation using the same mask, whereby the anode layer and the cathode layer can be formed in a self-aligned manner. As a result, there is no misalignment between the anode layer and the cathode layer, and it is possible to prevent a decrease in accuracy due to element miniaturization. Further, since the mask process is performed once, it is possible to minimize the additional process of forming the variable capacitance diode in the LSI process. Further, in the case of an LSI process equipped with a CMOS transistor, it is not necessary to add a mask process by forming the source and drain regions at the same time. It is possible to form. Next, the peak concentration position of the first conductivity type semiconductor region having a final medium impurity concentration is set to the PN junction position with the second conductivity type semiconductor region having a high impurity concentration, so that Since the concentration gradient of the first conductivity type semiconductor region having a medium impurity concentration becomes gradual, variation in the concentration of the PN junction due to manufacturing variation is reduced, and as a result, variation in the variable capacitance ratio can be suppressed. is there.

  A method of manufacturing a semiconductor device according to the present invention includes a step of forming a mask so that a variable capacitance diode forming region on a first conductivity type semiconductor substrate having a low impurity concentration is opened, and an ion implantation method in the opening of the mask A step of forming a first conductivity type semiconductor region having a medium impurity concentration, a step of forming a second conductivity type semiconductor region having a high impurity concentration in the opening of the mask, and heat-treating the semiconductor substrate. A method of activating the first conductivity type semiconductor region having the medium impurity concentration and the second conductivity type semiconductor region having the high impurity concentration; And forming the first conductive type semiconductor region having a medium impurity concentration and the second conductive type semiconductor region having a high impurity concentration at the same time as the source and drain regions in the CMOS transistor. It has. Next, the peak concentration position of the first conductivity type semiconductor region having a medium impurity concentration after the heat treatment is provided as a PN junction position with the second conductivity type semiconductor region having a high impurity concentration. With this configuration, first, the anode layer and the cathode layer of the variable capacitance diode are formed by ion implantation using the same mask, whereby the anode layer and the cathode layer can be formed in a self-aligned manner. As a result, there is no misalignment between the anode layer and the cathode layer, and it is possible to prevent a decrease in accuracy due to element miniaturization. Further, since the mask process is performed once, it is possible to minimize the additional process of forming the variable capacitance diode in the LSI process. Further, in the case of an LSI process equipped with a CMOS transistor, it is not necessary to add a mask process by forming the source and drain regions at the same time. It is possible to form. Next, the peak concentration position of the first conductivity type semiconductor region having a final medium impurity concentration is set to the PN junction position with the second conductivity type semiconductor region having a high impurity concentration, so that Since the concentration gradient of the first-conductivity-type semiconductor region having a medium impurity concentration becomes gentle, fluctuations in the concentration of the PN junction due to manufacturing variations are reduced, and as a result, variations in the variable capacitance ratio can be suppressed. Thus, an excellent method for manufacturing a semiconductor device is realized.

  Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a cross-sectional view of main steps showing a variable capacitance diode manufacturing method according to an embodiment of the present invention, and FIG. 2 is an impurity concentration distribution along the line AA in FIG. In FIG. 1, 3 is a p ⁻ semiconductor substrate, 4 is a mask material, 5 is a B ⁺ ion implantation layer, 6 is a p region, 7 is an anode layer, 8 is a PN junction, 9 is an As ⁺ ion implantation layer, and 10 is a cathode. A layer (n ⁺ region), 11 is an anode contact layer, 12 is an interlayer insulating film, 13 is a cathode electrode, and 14 is an anode electrode.

  The operation of the variable capacitance diode according to the first embodiment and the manufacturing method thereof configured as described above will be described below.

First, the mask material 4 is formed on the p ⁻ semiconductor substrate 3 so that the variable capacitance diode formation region is opened (see FIG. 1A).

Next, the B ⁺ ion implantation layer 5 is formed by ion implantation so that the concentration peak of the p region 6 finally becomes the PN junction 8 part with the n ⁺ region 10 (FIG. 1B). reference).

Next, the As ⁺ ion implantation layer 9 is formed by ion implantation so that the concentration peak of the n ⁺ region 10 is near the surface of the p ⁻ semiconductor substrate 3 (see FIG. 1C).

Next, the mask material 4 is removed to obtain a B ⁺ ion implantation layer 5 and an As ⁺ ion implantation layer 9 in the p ⁻ semiconductor substrate 3 (see FIG. 1D).

Next, the B ⁺ ion implantation layer 5 and the As ⁺ ion implantation layer 9 are activated by heat treatment to form the anode layer 7 and the cathode layer 10 respectively (see FIG. 1E).

Finally, the anode contact layer 11, the interlayer insulating film 12, the cathode electrode 13, and the anode electrode 14 are sequentially formed to obtain the p ⁻ semiconductor substrate 3 on which the variable capacitance diode element is mounted (see FIG. 1 (f)).

As described above, according to the first embodiment, first, the anode layer and the cathode layer of the variable capacitance diode are formed by ion implantation using the same mask, so that the anode layer and the cathode layer are self-aligned. It becomes possible to form. Further, in the case of an LSI process equipped with a CMOS transistor, by simultaneously forming the cathode layer of the variable capacitance diode and the source and drain regions of the NchMOS transistor, the anode contact layer of the variable capacitance diode and the source and drain region of the PchMOS transistor, respectively. There is no need to add a mask process, and it becomes possible to form a variable capacitance diode by adding only one process of ion implantation of the p region of the anode layer. Next, by forming a B ⁺ ion implantation layer by ion implantation so that the concentration peak of the p region finally becomes the PN junction with the n ⁺ region, the concentration of the p region at the PN junction is determined. Since the gradient becomes gentle, fluctuations in the concentration of the PN junction due to manufacturing variations are reduced, and as a result, variations in the variable capacitance ratio can be suppressed.

  Next, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 3 is a cross-sectional view of main steps showing a method for manufacturing a variable capacitance diode according to the second embodiment of the present invention, and FIG. 4 is an impurity concentration distribution of a BB cross section in FIG. In FIG. 3, 1 is an n semiconductor substrate, 2 is a p ⁻ region, 4 is a mask material, 5 is a B ⁺ ion implantation layer, 6 is a p region, 7 is an anode layer, 8 is a PN junction, and 9 is an As ⁺ ion implantation. Layers 10 and 10 are cathode layers (n ⁺ regions), 11 is an anode contact layer, 12 is an interlayer insulating film, 13 is a cathode electrode, and 14 is an anode electrode.

  The operation of the variable capacitance diode configured as described above and the method of manufacturing the same according to the second embodiment will be described below.

First, after forming the p ⁻ region 2 on the n semiconductor substrate 1, the mask material 4 is formed so as to open the variable capacitance diode forming region (see FIG. 3A).

Next, the B ⁺ ion implantation layer 5 is formed by ion implantation so that the concentration peak of the p region 6 finally becomes the PN junction 8 part with the n ⁺ region 10 (FIG. 3B). reference).

Next, the As ⁺ ion implantation layer 9 is formed by ion implantation so that the concentration peak of the n ⁺ region 10 is near the surface of the p ⁻ semiconductor substrate 3 (see FIG. 3C).

Next, the mask material 4 is removed to obtain a B ⁺ ion implantation layer 5 and an As ⁺ ion implantation layer 9 in the p ⁻ semiconductor substrate 3 (see FIG. 3D).

Next, the B ⁺ ion implantation layer 5 and the As ⁺ ion implantation layer 9 are activated by heat treatment to form the anode layer 7 and the cathode layer 10 respectively (see FIG. 3E).

  Finally, the anode contact layer 11, the interlayer insulating film 12, the cathode electrode 13, and the anode electrode 14 are sequentially formed to obtain the n semiconductor substrate 1 on which the variable capacitance diode element is mounted (see FIG. 3 (f)).

As described above, according to the second embodiment, the following effects can be obtained in addition to the first embodiment. That is, a p ⁻ region is first formed on an n semiconductor substrate, and then a variable capacitance diode is formed in the p ⁻ region, whereby the anode and cathode of the variable capacitance diode are in an electrically floating state from the substrate. That is, as a method of using the variable capacitance diode, in the first embodiment, the anode potential needs to be always set to the same potential as the substrate potential due to the structure of the variable capacitance diode. Then, since the anode and cathode of the variable capacitance diode are in an electrically floating state from the substrate, the anode and cathode potentials can be used at arbitrary potentials. Further, in the case of an LSI process equipped with a CMOS transistor, it is possible to form a variable capacitance diode without an additional process by simultaneously forming the p ⁻ region of the anode layer of the variable capacitance diode and the p well region of the NchMOS transistor. Become.

As the method for forming the cathode layer (n ⁺ region) 10, an As ⁺ ion implantation method is used, but a vapor deposition diffusion method or the like may be used, and the formation method is not limited. Next, the order of formation of the B ⁺ ion implantation layer 5 and the As ⁺ ion implantation layer 9 is reversed, that is, even if the B ⁺ ion implantation layer 5 is formed after the As ⁺ ion implantation layer 9 is formed first, An equivalent effect was obtained. The B ⁺ ion implantation layer 5 and the As ⁺ ion implantation layer 9 do not limit the ion species for implantation as long as they satisfy the respective conductivity types.

  Further, although the P type is used as the first conductivity type and the N type is used as the second conductivity type, conversely, the N type may be used as the first conductivity type, and the P type may be used as the second conductivity type. In that case, the same effect was obtained. Further, the presence / absence of a surface protective film at the time of ion implantation, the film type and film thickness of the mask material, the film type and film thickness of the interlayer insulating film, and detailed conditions are not limited.

  A method of manufacturing a semiconductor device according to the present invention includes a step of forming a mask so that a variable capacitance diode forming region on a first conductivity type semiconductor substrate having a low impurity concentration is opened, and an ion implantation method in the opening of the mask A step of forming a first conductivity type semiconductor region having a medium impurity concentration, a step of forming a second conductivity type semiconductor region having a high impurity concentration in the opening of the mask, and heat-treating the semiconductor substrate. A method of activating the first conductivity type semiconductor region having the medium impurity concentration and the second conductivity type semiconductor region having the high impurity concentration; And forming the first conductive type semiconductor region having a medium impurity concentration and the second conductive type semiconductor region having a high impurity concentration at the same time as the source and drain regions in the CMOS transistor. It has. Next, the peak concentration position of the first conductivity type semiconductor region having a medium impurity concentration after the heat treatment is provided as a PN junction position with the second conductivity type semiconductor region having a high impurity concentration. With this configuration, first, the anode layer and the cathode layer of the variable capacitance diode are formed by ion implantation using the same mask, whereby the anode layer and the cathode layer can be formed in a self-aligned manner. As a result, there is no misalignment between the anode layer and the cathode layer, and it is possible to prevent a decrease in accuracy due to element miniaturization. Further, since the mask process is performed once, it is possible to minimize the additional process of forming the variable capacitance diode in the LSI process. Further, in the case of an LSI process equipped with a CMOS transistor, it is not necessary to add a mask process by forming the source and drain regions at the same time. It is possible to form. Next, the peak concentration position of the first conductivity type semiconductor region having a final medium impurity concentration is set to the PN junction position with the second conductivity type semiconductor region having a high impurity concentration, so that Since the concentration gradient of the first-conductivity-type semiconductor region having a medium impurity concentration becomes gentle, fluctuations in the concentration of the PN junction due to manufacturing variations are reduced, and as a result, variations in the variable capacitance ratio can be suppressed. Thus, an excellent method for manufacturing a semiconductor device is realized.

Sectional drawing of the main process which shows the manufacturing method of the semiconductor device in one Embodiment of this invention The figure which shows the impurity concentration distribution of the AA cross section in FIG. Sectional drawing of the main process which shows the manufacturing method of the variable capacitance diode in the 2nd Embodiment of this invention. The figure which shows the impurity concentration distribution of the BB cross section in FIG. Structure diagram of variable capacitance diode of first conventional example The figure which shows the impurity concentration distribution of CC cross section in FIG. Structure diagram of variable capacitance diode of second conventional example The figure which shows the impurity concentration distribution of the DD cross section in FIG.

Explanation of symbols

1 n semiconductor substrate 2 p ^- region 3 p ^- semiconductor substrate 4 mask material 5 B ⁺ ion-implanted layer 6 p region 7 anode layer 8 PN junctions 9 As ⁺ ion-implanted layer 10 cathode layer (n ⁺ region)
DESCRIPTION OF SYMBOLS 11 Anode contact layer 12 Interlayer insulating film 13 Cathode electrode 14 Anode electrode 15 n ^- region 16 n region 17 n 'region 18 Cathode layer 19 Anode layer (p ⁺ region)

Claims (10)

Forming a mask so that the variable capacitance diode forming region on the first conductivity type semiconductor substrate having a low impurity concentration is opened, and the first conductivity type having an intermediate impurity concentration by ion implantation in the opening of the mask; Forming a semiconductor region, a step of forming a second conductivity type semiconductor region having a high impurity concentration in the opening of the mask, and a first conductivity type having the medium impurity concentration by heat-treating the semiconductor substrate. And a second conductivity type semiconductor region having a high impurity concentration is activated. Forming a first conductivity type semiconductor region having a low impurity concentration in a second conductivity type semiconductor substrate having a low impurity concentration, and forming a mask so as to open a variable capacitance diode formation region on the semiconductor substrate; A step of forming a first conductivity type semiconductor region having a medium impurity concentration in the opening of the mask by ion implantation, and a second conductivity type semiconductor region having a high impurity concentration in the opening of the mask. And a step of heat-treating the semiconductor substrate to activate the first conductivity type semiconductor region having the medium impurity concentration and the second conductivity type semiconductor region having the high impurity concentration. Device manufacturing method. The step of forming the first conductivity type semiconductor region having a medium impurity concentration and the second conductivity type semiconductor region having a high impurity concentration is performed after the formation of the second conductivity type semiconductor region having a high impurity concentration. The method for manufacturing a semiconductor device according to claim 1, further comprising a method of forming a semiconductor region of a first conductivity type having a concentration. The step of forming a first conductivity type semiconductor region having a medium impurity concentration and a second conductivity type semiconductor region having a high impurity concentration are formed at the same time and simultaneously with the source and drain regions in the CMOS transistor. A method of manufacturing a semiconductor device according to claim 1 or 2. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the step of forming the first conductivity type semiconductor region having a low impurity concentration is formed at the same time and simultaneously with the well region in the CMOS transistor. The peak concentration position of the first conductivity type semiconductor region having a medium impurity concentration after the heat treatment is a PN junction position with the second conductivity type semiconductor region having a high impurity concentration. 3. A method for manufacturing a semiconductor device according to 2. The method of manufacturing a semiconductor device according to claim 1, wherein the concentration of the first conductivity type semiconductor substrate having a low impurity concentration is 1 × 10 ¹⁷ cm ⁻³ or less. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the peak concentration of the first conductivity type semiconductor region having a low impurity concentration is 1 × 10 ¹⁶ cm ⁻³ or more and 1 × 10 ¹⁷ cm ⁻³ or less. . 3. The semiconductor according to claim 1, wherein a peak concentration of the first conductivity type semiconductor region having a medium impurity concentration is 5 × 10 ¹⁶ cm ⁻³ or more and 1 × 10 ¹⁸ cm ⁻³ or less. Device manufacturing method. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the second conductivity type semiconductor region having a high impurity concentration has a peak concentration of 1 × 10 ²⁰ cm ⁻³ or more.

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