CN100433024C - Software and hardware synergism communication method - Google Patents
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Abstract
The invention relates to the software-hardware coordinate-simulation communication method for SOC. Wherein, in initiation stage, the data package exchanged between the software and hardware comprises: a direction mark for data transmission, a data type mark to show whether the package contains register configuration information, a first data mark to show whether the package is signal enable bit, a register address, a register data as the register configuration information, a first enable mark. This invention is benefit to complete validation on whole system.
Description
Technical field
The present invention relates to the integrated circuit (IC) design technical field, particularly the design verification technology of SOC (system-on-a-chip SOC (system on a chip)).
Background technology
In traditional SOC design, its process generally is the beforehand research of system, divides each functional module (comprising software, hardware), and the realization of concrete module is set, the checking of each module then.According to the conventional method, hardware module and software module verify separately separately whether its function is correct, that is to say, their checking is not under same environment.There are a lot of shortcomings in this method.At first, the hardware and software module must be set up verification environment separately according to system requirements, and this must cause the inconsistency of two environment; Simultaneously, additionally increased the realistic model of hardware simulation software environment and software simulation hardware environment; In addition, realistic model is different from actual code, to such an extent as to when integrating at last, be easy to generate the mistake that can not expect, causes whole design repeatedly.The software-hardware synergism checking has then solved the separately shortcoming of checking to the full extent, makes software and hardware Collaboration as early as possible, allows software debugging and hardware debug carry out at one time, in time finds the mistake of software and hardware.
In order to address this problem, a series of method is arranged in the industry at present: modal a kind of be soft prototype verification, being about to hardware design is simulated on workstation by the HDL emulator, between software model and the hardware emulator by api interface the communicate by letter associative simulation of the software and hardware part that realizes total system, i.e. Co-simulation.The advantage of this method is that the controllability of whole simulation proof procedure and monitoring property are fine, and cost is low; Its shortcoming is to verify limited in one's ability, can only be applicable to early stage test, interface debugging and code debugging aspect; And emulation run speed is very slow; It can only the correctness of verification model on function in addition, is not accurate to the cycle, also is not accurate to pin; And it is difficult to solve the synchronous requirement of peripheral data.Method is a rapid prototyping system in another, and the realization approach comprises imitation (Emulation), reconfigurable Yuan Xingxitong ﹠amp; Special-purpose prototype system, it be a kind of with SOC system fast mapping to the method for coming based on processor array or the reconfigurable platform that builds based on the FPGA device design is verified.The advantage of this method is that simulation velocity is very fast, but the controllability of simulation process and detectability are poor, and cost is very high.
Therefore, the software and hardware combined checking of SOC is still the problem that a needs solves.Below enumerate some solutions that existing patent and project propose.
The typical case of the SOC software and hardware verification platform of domestic research and development has: the Media Processor software and hardware cooperating simulation verification platform (MPSP) of Zhejiang University, Institute of Microelectronics of Tsinghua Univertity have proposed modified SoC prototype verification board design scheme etc. based on RC1000 and the RC200 platform of Celoxica.But the MPSP specificity of Zhejiang University is strong excessively, and extensibility can not satisfy the actual needs of SoC system research and development, and that is that all right is ripe for the SoC prototype verification scheme of Tsing-Hua University, and complete platform can not be provided.
Summary of the invention
Technical matters to be solved by this invention is, for the software and hardware combined checking of SOC provides a kind of software and hardware both sides data communication mechanism, for joint verification provides communication support.
The technical scheme that the present invention solve the technical problem employing is that software and hardware synergism communication method may further comprise the steps:
A, initialization;
B, software side send the excited data bag to the hardware side;
C, hardware lateral root carry out simulation process according to the excited data bag, and result is beamed back software side, and are the software side reception;
D, circulation step b-c finish up to emulation;
It is characterized in that,
In the simulation initialisation stage, software side sends two kinds of packets to the hardware side, wherein first kind of packet comprises register address and register data, and register address is used to identify the address of the register of needs configuration, the configuration information that register data is promptly sent to register; Second kind of packet comprises that clock, input signal enable to identify, output signal enables to identify, be used to define two-way signaling enable bit first enable sign;
In the simulation run stage, software side sends the excited data bag to the hardware side, and hardware side direction software side sends response data packet afterwards, hocket successively, wherein:
Software side comprises clock, input marking, bearing mark and second enable flag to the packet that the hardware side sends, and is specially:
Clock: 8 clocks of definable altogether, most significant digit is first clock, inferior position is second clock, the rest may be inferred 24 be the 8th clock;
Input marking: the value that is used for explaining input signal;
Bearing mark: the value that is used for explaining the two-way signaling input direction;
Second enable flag: the value of the enable bit of input and two-way signaling;
The packet that hardware side direction software side sends comprises INOUT position and OUTPUT position, and wherein INOUT is used for storing the value of two-way signaling outbound course, OUTPUT: the value that is used for storing output signal;
And in simulation initialisation stage and simulation run stage, the packet header of all packets all comprises following sign:
Direction signs are used to identify notebook data and wrap in the direction that both sides transmit;
The data type sign, whether be used to identify the notebook data bag is register configuration information;
Whether first Data Identification, being used to identify the notebook data bag is the signal enable bit.
Further, in the simulation initialisation stage, also comprise in the packet:
The simulation model type identification, being used for sign, to belong to the associative simulation pattern still be the vector simulation model;
First length mark is used for the number of identification data packet frame;
Second length mark is used for identifying the number of this communication packet.
In the simulation run stage, all packets are regular lengths, if curtailment fills up with filler.
The invention has the beneficial effects as follows, for hardware accelerator or imitate device and the correct transmission data at a high speed of software simulator provide support, make software and hardware both sides collaborative work, to finish checking to total system.
The present invention is further illustrated below in conjunction with the drawings and specific embodiments.
Description of drawings
Fig. 1 is the structural drawing of realization software and hardware cooperating simulation communication protocol data bag of the present invention;
Fig. 2 is the package head format synoptic diagram of packet of the present invention;
Fig. 3 is the structural representation of a frame in the inclusion of initial phase configuration register;
Fig. 4 is the inclusion form synoptic diagram of enable bit;
Fig. 5 is the detailed inclusion organized formats of initial phase;
Fig. 6 is the form synoptic diagram that simulation run stage software side passes to the inclusion of hardware side;
Fig. 7 is the form synoptic diagram that simulation run stage software side passes to the detailed packet header of hardware side.
Fig. 8 is a form synoptic diagram of being passed back the data inclusion of software side by the hardware side;
Fig. 9 is detailed packet physique formula synoptic diagram;
Figure 10 is the form synoptic diagram of the concrete inclusion of emulation ending phase.
Figure 11 is the working environment synoptic diagram of communication means of the present invention.
Embodiment
Communication means of the present invention is based on following SOC authentication mechanism:
SOC software and hardware integration design and verification method may further comprise the steps: a, initialization; B, software side send the excited data bag to the hardware side; C, hardware lateral root carry out simulation process according to the excited data bag, and result is beamed back software side, and are the software side reception; D, circulation step b-c finish up to emulation.
With the Co-Simulation mode simulation is example.
The basic mechanism of Co-Simulation mode simulation: after simulation initialisation, can enter the simulation run stage.During simulation run, software sends an excited data bag to hardware earlier, receives a response data packet from hardware then; Then send an excited data bag again, receive a response data packet then; So cycle alternation goes on, till emulation finishes.
A) initial phase of emulation
Initial phase in emulation, software side is by sending two packets to the hardware side, the configuration information that wherein comprises hardware side register in first packet, write corresponding value by the register to the hardware side, the input and output direction to each data bit in second packet defines.Thereby finish initialization to the hardware side.
B) the simulation run stage
In the operation phase of emulation, the software and hardware data communication transmits with the form of packet, packet comprises packet header (Packet Header) and inclusion (Packet Body, for the Co-Simulation pattern, the data in a just corresponding collaborative simulation cycle of data inclusion), in emulation is carried out, send a packet (constituting followed by a load data bag) in each collaborative simulation cycle by software environment by data packet head, after waiting for that hardware side finishes emulation, after packet (being made of immediately following the load data bag data packet head) passed back, be returned to emulator after handling.Provide the packet in simulation run stage and the form of load data here.The simulation process of Co-Simulation pattern: software sends first excited data bag, read the response data packet of first excited data bag that hardware returns, send second excited data bag, read the response data packet of second excited data bag that hardware returns, so circulation is gone down, and finishes up to emulation.Promptly in simulation process, send to the hardware side and after initializationization is finished, determine from the size that the hardware side sends to the packet of software side from software side.The packet that does not allow variation length during emulation occurs.
C) emulation ending phase
Software side is after emulation finishes, and sending a word length by software side to the hardware side is 17 32 bit data bags.Notice hardware is to finish emulation.Wherein the load data bag promptly is the direction enable information (complete is ' 0 ') of turn-offing all I/O of associative simulation card.
Accompanying drawing 1 is the structural drawing of realization software and hardware cooperating simulation communication protocol data bag of the present invention; Be taken as the data stream segment among the figure, it is made up of packet, and packet 32 frame one by one constitutes, and the number of frame is by concrete type of data packet decision; Packet is made up of packet header and inclusion, the length in packet header is that what to be fixed is a frame, be mainly used to define the number etc. of length, packet header marker bit and packet of type, the inclusion of direction, designation data inclusion type, the packet of Validation Mode, data stream, inclusion is made of several frames, its number is unfixed, and the number of frame is by concrete type of data packet decision.
Whole software and hardware cooperating simulation process is divided into three phases: simulation initialisation, simulation run and emulation finish; The uniform format of the packet of each simulation stage is defined as shown in Figure 1, and wherein each lattice is a frame, and the size of frame is 32bit; First frame of packet is the packet header of packet, and immediately following being inclusion, inclusion is made up of n frame behind the packet header, and n is the type decided by packet.
In software and hardware cooperating simulation communication protocol unified Definition the package head format of packet, as shown in Figure 2; For inclusion, different definition formats is arranged at different simulation stage;
The following description of concrete meaning of each in the packet header:
DIR: the direction position, the 31st of packet header frame, 0 expression packet is delivered to the hardware side from software side, and 1 expression packet is delivered to software side from the hardware side;
Type: type bit, the 30th of packet header frame, 1 expression packet is a register configuration information, 0 expression packet is non-register configuration information;
Mode: simulation model is selected the position, the 29th of packet header frame, 1 expression Co-Simulation pattern (associative simulation pattern), 0 expression Vector simulation model (vector simulation model);
EN: marker bit, the 28th of data packet head, 1 expression packet is the information of signal enable bit, 0 expression packet is not the information of signal enable bit.
SHD: turn-off the bag position, the 27th of data packet head, 1 expression packet is for turn-offing bag, and 0 expression packet is non-shutoff bag;
N/A: keep the position, the 17th to 16 and the 26th to 24 of data packet head stay and expand after doing;
Length: the 23rd to 18 of packet header, the number (comprising inclusion and packet header) of frame is a digit with 32bit in the expression packet;
NO_FRA: the number of expression packet;
The packet header marker bit: the 9th to 0 of packet header is steady state value 0x0A5;
For the formal definition of inclusion, we have different definition at different simulation stage:
The simulation initialisation stage:
Software side sends data to the hardware side, and the hardware side is carried out initialization; The data that send contain two types packet, comprise the configuration information of hardware side register in wherein a kind of packet, and the register of hardware side is write corresponding initialization value, and another kind of packet is number and the input/output signal that is used for defining clock.According to the different inclusion of different type of data packet definition: a kind of inclusion is used for the register in the configure hardware side, a kind of enable bit that is used for configurable clock generator and input, output and two-way signaling.Concrete inclusion is defined as follows:
The inclusion form of configuration register (being illustrated in figure 3 as a frame in the inclusion).
ADDR1 and ADDR2 are the addresses of the register that will dispose, and DATA1 and DATA2 are the configuration informations of the register that will dispose; For the register configuration information of 32 of less thaies, with 1 as filling; The warm reset of hardware realizes: realize resetting by the 0x00 register being write the FF value.The time that resets is determined for the value that the 01H register writes by the address.Hardware automatically restores to normal duty after reset time.Warm reset adopts different packets to send with configuration register.
At initial phase, need the register such as the following table 1 of configuration listed, the address is 12 registers of 0x00～0x0B:
| Register name | Register address | Attribute (scope) | Function declaration | |
| Reset | 0x00 | Keep | The warm reset signal.When this register writes 0xFF in the ban, the hardware warm reset. | |
| Reset Time | 0x01 | Keep | CSM card warm reset time value (clock periodicity of CSM card). | |
| Sim_Mode | 0x02 | 0x0F, 0xF0 | 0x0F represents the Co-simulation pattern; 0xF0 represents the Vector | |
| No_clk | 0x03 | |||
| 0～0xFF | For ' 1 ' bit representation is enabled this clock, then represent this clock of not enabled for ' 0 '.Represent only to have enabled to be numbered two clocks of 0 and 3 among the MVP as 10010000. | |||
| | 0x04 | 1～15 | In an emulation cycle, CSM is to (CSM clock) periodicity at interval between DUT loading data and the loading clock event | |
| Lo_dly | 0x05 | |||
| 1～15 | In an emulation cycle, CSM loads clock to DUT and receives (CSM clock) periodicity at interval between the | |||
| No_input_L | 0x06 | |||
| 0～0xFF | The least-significant byte data of expression input signal width. | |||
| | 0x07 | 0～1 | The 9th bit data of expression input signal width.When the input signal width greater than 256 the time, this position is 1.Otherwise be 0. | |
| | 0x08 | 0～0xFF | The least-significant byte data of expression two-way signaling width. | |
| | 0x09 | 0～1 | The 9th bit data of expression two-way signaling width.When the two-way signaling width greater than 256 the time, this position is 1.Otherwise be 0. | |
| | 0x0A | 0～0xFF | The least-significant byte data of expression output signal width. | |
| | 0x0B | 0～1 | The 9th bit data of expression output signal width.When the output signal width greater than 256 the time, this position is 1.Otherwise be 0. | |
| State_1 | 0x0C | Only_read | ||
| State_2 | 0x0D | Only_read |
| State_3 | 0x0E | Only_read | |
| State_4 | 0x0F | Only_read |
Table 1
Be used for the inclusion form of enable bit of configurable clock generator and input, output and two-way signaling signal, as shown in Figure 4; The number of frame is variable in the inclusion, and it is by the number decision of input, output and two-way signaling, fills with 0 for the frame of discontented 32bit.Detailed inclusion organized formats as shown in Figure 5.
CLOCK: be used for defining clock, 8 clocks of definable altogether, most significant digit is first clock, inferior position is second clock, the rest may be inferred 24 be the 8th clock; For example: enable when being numbered 0 and 3 clock, then eight of the clock section is 1001000.
INPUT ' EN: be used for defining the enable bit of input signal, with 1 filling, 1 number is by the number decision of input signal;
OUTPUT ' EN: be used for defining the enable bit of output signal, with 1 filling, 1 number is by the number decision of output signal;
INOUT ' EN: be used for defining the enable bit of two-way signaling, with 1 filling, 1 number is by the number decision of two-way signaling;
Padding: filler is used for filling the frame of being discontented with 32bit;
At initial phase, send above two packets after, just think that the initialization of hardware is just finished, when emulation each time started, software all will carry out initialization to hardware.
The simulation run stage:
Software side sends data to the hardware side hardware side is applied pumping signal, waits for after the hardware side is finished emulation and passes data back software side by PCI.The inclusion of the packet in simulation run stage is divided into two kinds: a kind ofly send to the hardware side by software side, it is the pumping signal that hardware is applied; Another kind passes to software side by the hardware side, and it is the emulated data of reading back from hardware.Concrete data packet format definition:
The form of transmission (passing to the hardware side by software side) inclusion as shown in Figure 6.
CLOCK: be used for defining clock, 8 clocks of definable altogether, most significant digit is first clock, inferior position is second clock, the rest may be inferred 24 be the 8th clock; For example: enable when being numbered 0 and 3 clock, then eight of the clock section is 10010000.
INPUT: the value that is used for storing input signal;
INOUT: the value that is used for storing the two-way signaling input direction;
EN: the value of the enable bit of input and two-way signaling, 1 expression enable signal, with 1 filling, 1 number is by the number decision of input signal or two-way signaling;
Padding: filler is used for filling the frame of being discontented with 32bit;
Detailed package head format as shown in Figure 7.
To sending some explanation of inclusion form:
The length perseverance of CLOCK clock bit is 8, and corresponding to 31 of first 32 bit data, the 30....24 position is successively corresponding to the 0th, 1,2,3,4,5,6,7 clock passages of clock passage.Clock data is the current actual level of clock signal.The not enabled clock is filled with 0 all the time, and such as enabling 0 channel clock, then 8 CLOCK values are:? 000_0000 (annotate:? representing this to enable clock signal is actual level corresponding under the current emulated data).
CLK if the figure place sum of INPUT and INOUT is not 32 integral multiple, then passes through in its back to introduce PADDING information, it is expanded to 32 integral multiple, as shown above.Wherein INPUT has the X position.INOUT has the Y position.As: 8+X+Y=55, then should add 91, in the back as filler.
The EN position, as send data (comprise clock, input, inout) Wei direction selection signal, the corresponding position of 1 expression is input (software transmission excitation information hardware); The corresponding transmission of 0 expression data bit is output signal (data returns to software side from hardware).Each data of EN position and the clock that sends data, input, each of inout position is corresponding one by one, during integral multiple that less than is 32, adds PADIDNG information in the back.
About 8 EN of clock signal correspondence, if saltus step has taken place the clock signal of current data packet correspondence, the EN of its corresponding position is ' 1 ', otherwise is ' 0 ', such as, current data packet is that reference numeral is 3 clock saltus step, then these 8 EN are encoded to 0001000.
The processing of EN position when not having INOUT bi-directional data position is the special circumstances of the Y=0 in this document.With Y! The disposal route of=0 (when the bi-directional data position is arranged) is the same.
The form that receives (passing software side back by the hardware side) data inclusion as shown in Figure 8.
INOUT: the value that is used for storing the two-way signaling outbound course
OUTPUT: the value that is used for storing output signal;
Padding1 and Padding2: filler is used for filling the frame of being discontented with 32bit;
Detailed packet physique formula is referring to Fig. 9.
In the data of returning from the hardware side, include PADDING information and INOUT position and OUTPUT position.
In simulation process, send to the hardware side and after initializationization is finished, determine from the size that the hardware side sends to the packet of software side from software side.The packet that does not allow variation length during emulation occurs.
The emulation ending phase:
After emulation finished, sending a word length by software side to the hardware side was 17 32 bit data bags, with notice hardware to finish emulation.The form of concrete inclusion as shown in figure 10.Wherein 32 32 is ' 0 ' entirely.
Working environment of the present invention is referring to Figure 11.The pin map information that test and excitation that employing C language or hardware description language are write and hardware virtual map software (MVP) produce, adopt the packing based on transaction-level of C language compilation to unpack in the application program module via third party's emulation tool and by PL API (HDL application interface function) or direct sending to by text, this module breaks into excitation information according to the software and hardware communication protocol of described platform the packet of prescribed form, and send to hardware (among the FIFO of pci card) by pci bus, hardware is sent to excitation among the FIFO of associative simulation integrated circuit board by the two Handshake Protocols of software and hardware communication then, by emulation main control module (or BFM) module the excited data bag is carried out decompression processing subsequently and convert to concrete clock through the test and excitation signal loading of standard in tested module, treat the corresponding emulation cycle finish after tested module (DUT) pass the response signal of gained back emulation main control module (or BFM) module and pack according to software and hardware communication protocol by it, then these response data packet are stored among the up FIFO of associative simulation daughter board, wait its software and hardware communication module to shake hands after the success, then response data packet is sent among the FIFO of pci card, being transmitted back to by former road by pci bus at last adopts the packing based on transaction-level of C language compilation to unpack in the application program module, this module with the response data packet decompress(ion) of receiving after, pass response message back the third party emulation tool, or directly preserve by corresponding API (Application Programming Interface) function with textual form.Adopt user in the whole process of this verification method of described platform can not feel the existence of whole simulation hardware environment, whole simulation operating process and common software simulation emulation there are not difference, but simulation velocity has great raising.
Claims (3)
1, software and hardware synergism communication method may further comprise the steps:
A, initialization;
B, software side send the excited data bag to the hardware side;
C, hardware lateral root carry out simulation process according to the excited data bag, and result is beamed back software side, and are the software side reception;
D, circulation step b-c finish up to emulation;
It is characterized in that,
In the simulation initialisation stage, software side sends two kinds of packets to the hardware side, wherein first kind of packet comprises register address and register data, and register address is used to identify the address of the register of needs configuration, the configuration information that register data is promptly sent to register; Second kind of packet comprises that clock, input signal enable to identify, output signal enables to identify, be used to define two-way signaling enable bit first enable sign;
In the simulation run stage, software side sends the excited data bag to the hardware side, and hardware side direction software side sends response data packet afterwards, hocket successively, wherein:
Software side comprises clock, input marking, bearing mark and second enable flag to the packet that the hardware side sends, and is specially:
Clock: 8 clocks of definable altogether, most significant digit is first clock, inferior position is second clock, the rest may be inferred 24 be the 8th clock;
Input marking: the value that is used for explaining input signal;
Bearing mark: the value that is used for explaining the two-way signaling input direction;
Second enable flag: the value of the enable bit of input and two-way signaling;
The packet that hardware side direction software side sends comprises INOUT position and OUTPUT position, and wherein INOUT is used for storing the value of two-way signaling outbound course, OUTPUT: the value that is used for storing output signal;
And in simulation initialisation stage and simulation run stage, the packet header of all packets all comprises following sign:
Direction signs are used to identify notebook data and wrap in the direction that both sides transmit;
The data type sign, whether be used to identify the notebook data bag is register configuration information;
Whether first Data Identification, being used to identify the notebook data bag is the signal enable bit.
2, software and hardware synergism communication method as claimed in claim 1 is characterized in that, in the simulation initialisation stage, also comprises in the packet:
The simulation model type identification, being used for sign, to belong to the associative simulation pattern still be the vector simulation model;
First length mark is used for the number of identification data packet frame;
Second length mark is used for identifying the number of this communication packet.
3, software and hardware synergism communication method as claimed in claim 1 is characterized in that, in the simulation run stage, all packets are regular lengths, if curtailment fills up with filler.
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| CN101420437B (en) * | 2008-11-14 | 2011-08-17 | 北京航空航天大学 | Interface device for prototype system and HLA simulation system |
| CN103258067B (en) * | 2012-02-20 | 2016-05-25 | 京微雅格（北京）科技有限公司 | In a kind of configurable SOC(system on a chip), keep the conforming method of framework, software and hardware |
| CN103226531B (en) * | 2013-04-07 | 2016-01-20 | 北京工业大学 | A kind of dual-port peripheral configuration interface circuit |
| CN105205249B (en) * | 2015-09-17 | 2018-08-28 | 深圳国微技术有限公司 | A kind of SOC debugging verification systems and its software-hardware synergism method |
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