CN100429792C - Flat capacitor structure and flat capacitor, grid and resistance forming technique method - Google Patents
Flat capacitor structure and flat capacitor, grid and resistance forming technique method Download PDFInfo
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- CN100429792C CN100429792C CNB2005101106042A CN200510110604A CN100429792C CN 100429792 C CN100429792 C CN 100429792C CN B2005101106042 A CNB2005101106042 A CN B2005101106042A CN 200510110604 A CN200510110604 A CN 200510110604A CN 100429792 C CN100429792 C CN 100429792C
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- 238000000034 method Methods 0.000 title claims abstract description 15
- 239000003990 capacitor Substances 0.000 title abstract 6
- 239000002184 metal Substances 0.000 claims abstract description 30
- 238000005530 etching Methods 0.000 claims abstract description 22
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 27
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 23
- 229920005591 polysilicon Polymers 0.000 claims description 22
- 238000005229 chemical vapour deposition Methods 0.000 claims description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- 230000004888 barrier function Effects 0.000 claims description 7
- 238000000465 moulding Methods 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 2
- 238000000151 deposition Methods 0.000 abstract 3
- 230000003647 oxidation Effects 0.000 abstract 2
- 238000007254 oxidation reaction Methods 0.000 abstract 2
- 239000000126 substance Substances 0.000 abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 230000008021 deposition Effects 0.000 abstract 1
- 239000003292 glue Substances 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
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Abstract
This invention discloses one plane capacitor structure and its plate capacitor, grating electrode and resistance form process method, which comprises the following steps: a, depositing multiple silicon chemical phase and injecting phosphor; b, medium chemical phase deposition for growing and to remove capacitor down electrode and high resistance medium subject; c, metal layer splashing; d depositing and growing block oxidation layer phase; e, etching the block oxidation layer and metal layer through light etch glue to form capacitor top electrode and grating electrode and resistance metal layer.
Description
Technical field
The present invention relates to the formation process of a kind of capacity plate antenna, grid and resistance.
Background technology
As shown in Figure 1, it is existing capacity plate antenna, grid, low resistivity layer resistance and resistive formation electric resistance structure schematic diagram, doing in the product of grid (Gate) with polysilicon (Poly) and metal level (Metal) at present, capacity plate antenna is by making bottom crown with grid layer (Poly+Metal), with chemical vapor deposition (CVD) process deposits inter-level dielectric, physical vapor deposition (PVD) or CVD one deck Metal realize as top crown again.Carve the last utmost point and the inter-level dielectric of electric capacity during etching earlier, carve the following utmost point of electric capacity more in the lump, Gate and low resistivity layer resistance.And resistive formation resistance needs independent polysilicon (HR polysilicon) growth/injection to add the etching engineering with photoetching to finish.
When the problem of such technology maximum is the etching inter-level dielectric, grid and the ohmically metal level of low resistivity layer are had in various degree etching, cause low resistivity layer resistance resistivity (ρ s) internal homogeneity to worsen, be easy to cause production loss.In addition, very big step is arranged between capacitive region and diffusion region, this also brings hidden danger for the thickness homogeneity of the inter-level dielectric (PMD) before the metal of back.
Summary of the invention
Technical problem to be solved by this invention provides the formation process of a kind of capacity plate antenna, grid and resistance, and it can simplify technology, and can improve yields, improves low-resistance resistivity internal homogeneity, improves PMD thickness homogeneity.
In order to solve above technical problem, the invention provides the formation process of a kind of capacity plate antenna, grid and resistance, described resistance comprises low resistivity layer resistance and resistive formation resistance, wherein capacity plate antenna and resistance moulding on the carrying out local oxide isolation layer, grid is moulding on gate oxide, and it mainly may further comprise the steps, the first step, chemical vapor deposition of polysilicon is grown up, and phosphorus injects comprehensively; Second step, the inter-level dielectric chemical vapor deposition growth, and be that mask etching is removed the following utmost point of electric capacity and the inter-level dielectric beyond the high resistant with the photoresist; The 3rd step, the metal level sputter; In the 4th step, the barrier oxide layer chemical vapour deposition (CVD) is grown up; The 5th step, by described barrier oxide layer of photoresist mask etching and described metal level, form the utmost point and the metal level that forms grid and resistance on the electric capacity, and then make the mask etching polysilicon jointly with described photoresist and inter-level dielectric, form the polysilicon of the following utmost point of electric capacity and grid, low resistivity layer resistance, resistive formation resistance.
Bottom crown has saved the layer of metal layer in capacity plate antenna structure of the present invention, and at the technological process of its formation and corresponding grid, low resistivity layer resistance, resistive formation resistance forms in the flow process, because bottom crown has saved the layer of metal layer in the capacity plate antenna structure, and in growth during inter-level dielectric after the direct etching, carry out the metal level sputter, so just can avoid when etching growth inter-level dielectric, causing infringement to the metal level of grid and low resistivity layer, and owing to can etch the metal level of the utmost point and grid and resistance on the electric capacity simultaneously, and the following utmost point and the grid of electric capacity, low resistivity layer resistance, the polysilicon of resistive formation resistance, so just can simplify technology, reduced cost, improve low-resistance ρ s internal homogeneity, improve PMD thickness homogeneity.
Description of drawings
Below in conjunction with the drawings and specific embodiments the present invention is further elaborated.
Fig. 1 is existing capacity plate antenna, grid, low resistivity layer resistance and resistive formation electric resistance structure schematic diagram;
Fig. 2 is capacity plate antenna of the present invention, grid, low resistivity layer resistance and resistive formation electric resistance structure schematic diagram.
Embodiment
As shown in Figure 2, it is capacity plate antenna 1 of the present invention, grid 2, low resistivity layer resistance 3 and resistive formation resistance 4 structural representations.The polysilicon of its utilization after injecting carried out the inter-level dielectric of electric capacity 1 earlier as the following utmost point of electric capacity 1 before the metal level PVD of grid 2, again the utmost point on while PVD grid 2 metal levels and the electric capacity 1.During etching, earlier the metal level of the utmost point on the electric capacity 1 with grid 2 and low resistivity layer resistance 3 carved, utilize inter-level dielectric and photoresist to make the polysilicon that mask etches 1 time utmost point of electric capacity and grid 2/ low resistivity layer resistance 3 simultaneously jointly again, even can also etch high-resistance polysilicon, and inject by the transoid that high energy sees through dielectric medium and to adjust its resistance value.
The specific implementation process is as follows:
1. polysilicon CVD grows up, and phosphorus injects adjustment resistivity comprehensively;
2. inter-level dielectric (SiO2 or ONO) CVD grows up, and by photoresist (PR)
Mask etching is removed the inter-level dielectric beyond 1 time utmost point of capacity plate antenna and the resistive formation resistance 4;
3. metal level sputter (Metal sputter), thickness can be decided the demand of low resistivity layer resistance 3 according to product;
4. barrier layer oxide (abbreviating " oxide layer " as) such as adopting SiO2, carries out CVD growth (exempting from drain-source (SD) implant damage in order to protection electric capacity 1 inter-level dielectric);
5. by PR mask etching barrier layer oxide and metal level, form the last utmost point of electric capacity 1 and the metal level of grid 2 and low resistivity layer resistance 3, make the mask etching polysilicon jointly with this layer mask and inter-level dielectric again, form the following utmost point and the polysilicon of grid 2 and low resistivity layer resistance 3 and the polysilicon of resistive formation resistance 4 of electric capacity 1;
6. see through the resistance of polycrystalline silicon of high energy transoid injection (B injection) the adjustment resistive formation resistance 4 of medium with a step, divest photoresist again.
When returning quarter (Gate Spacer EtchBack), can remove grid side wall in the present invention the medium on 1 time utmost point extending part of electric capacity polysilicon; And be that mask can prevent to form oxide on the polysilicon of resistive formation resistance 4 with the inter-level dielectric.
Technology of the present invention can be saved a single metal layer sputter and a step etching polysilicon, if simultaneously when making resistive formation resistance 4, improved technology also can be saved the polysilicon growth of a step resistive formation resistance 4, the etching polysilicon of one mask and resistive formation resistance 4.
In the improved technology, on the etching electric capacity 1 extremely the metal level to grid 2 and low resistivity layer resistance 3 do not have etching, low resistivity layer resistance 3 internal homogeneities improve; During grid 2 etchings, there is the barrier layer oxide to make mask, can improves the pattern of grid 2; Distribution front end (FEOL) step reduces, and the PMD internal homogeneity improves.
Claims (3)
1, the formation process of a kind of capacity plate antenna, grid and resistance, described resistance comprises low resistivity layer resistance and resistive formation resistance, wherein capacity plate antenna and resistance moulding on the carrying out local oxide isolation layer, grid is moulding on gate oxide, it is characterized in that it mainly comprises the steps, the first step, chemical vapor deposition of polysilicon is grown up, and phosphorus injects comprehensively; In second step, the inter-level dielectric chemical vapour deposition (CVD) is grown up, and is the following utmost point and high resistant inter-level dielectric in addition that mask etching is removed electric capacity with the photoresist; The 3rd step, the metal level sputter; In the 4th step, the barrier oxide layer chemical vapour deposition (CVD) is grown up; The 5th step, by described barrier oxide layer of photoresist mask etching and described metal level, form the utmost point and the metal level that forms grid and resistance on the electric capacity, and then make the mask etching polysilicon jointly with described photoresist and inter-level dielectric, form the polysilicon of the following utmost point of electric capacity and grid, low resistivity layer resistance, resistive formation resistance.
2, the formation process of capacity plate antenna as claimed in claim 1, grid and resistance is characterized in that, it also comprises a step: inject by the high energy transoid of medium and adjust the resistive formation resistance, and then divest photoresist.
3, the formation process of capacity plate antenna as claimed in claim 1 or 2, grid and resistance is characterized in that, the 3rd step, described metal layer thickness was decided the needs of low resistivity layer resistance according to product.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101106042A CN100429792C (en) | 2005-11-22 | 2005-11-22 | Flat capacitor structure and flat capacitor, grid and resistance forming technique method |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2005101106042A CN100429792C (en) | 2005-11-22 | 2005-11-22 | Flat capacitor structure and flat capacitor, grid and resistance forming technique method |
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| CN1971947A CN1971947A (en) | 2007-05-30 |
| CN100429792C true CN100429792C (en) | 2008-10-29 |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101673671B (en) * | 2009-09-22 | 2013-02-27 | 上海宏力半导体制造有限公司 | Method for manufacturing high-resistance resistors |
| CN102129977B (en) * | 2010-01-20 | 2012-07-11 | 上海华虹Nec电子有限公司 | High-resistance resistor and method for realizing same |
| CN104347504A (en) * | 2013-08-08 | 2015-02-11 | 北大方正集团有限公司 | Manufacturing method of mixed signal integrated circuit |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03220764A (en) * | 1990-01-25 | 1991-09-27 | Nec Corp | Manufacture of semiconductor device |
| JP2001308192A (en) * | 1992-06-15 | 2001-11-02 | Asahi Kasei Microsystems Kk | Semiconductor device |
| US6617221B1 (en) * | 2003-01-30 | 2003-09-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of making capacitors |
| US20050110070A1 (en) * | 2003-10-24 | 2005-05-26 | Masayoshi Omura | Semiconductor device with capacitor and fuse and its manufacture method |
-
2005
- 2005-11-22 CN CNB2005101106042A patent/CN100429792C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03220764A (en) * | 1990-01-25 | 1991-09-27 | Nec Corp | Manufacture of semiconductor device |
| JP2001308192A (en) * | 1992-06-15 | 2001-11-02 | Asahi Kasei Microsystems Kk | Semiconductor device |
| US6617221B1 (en) * | 2003-01-30 | 2003-09-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of making capacitors |
| US20050110070A1 (en) * | 2003-10-24 | 2005-05-26 | Masayoshi Omura | Semiconductor device with capacitor and fuse and its manufacture method |
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| CN1971947A (en) | 2007-05-30 |
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