CN100426250C - Device and method for detecting system main board receiving signal sensitivity - Google Patents
Device and method for detecting system main board receiving signal sensitivity Download PDFInfo
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- CN100426250C CN100426250C CNB2005100360949A CN200510036094A CN100426250C CN 100426250 C CN100426250 C CN 100426250C CN B2005100360949 A CNB2005100360949 A CN B2005100360949A CN 200510036094 A CN200510036094 A CN 200510036094A CN 100426250 C CN100426250 C CN 100426250C
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Abstract
The present invention is measurement apparatus and method for system main board signal receiving sensitivity, and the system main board adopts SATA/SAS interface specification. The measurement apparatus include one computer and one control board, which include one coding circuit, one parallel/serial converter circuit, one output buffering circuit, one mixer, one jitter generator, one input buffering circuit, one serial/parallel converter circuit and one decoding circuit. The measurement method includes: setting the system main board as the double emitting state and setting one initial jitter level value, one initial output voltage level value, etc; sending several signals to the control board with the computer; regulating the computer to obtain the maximum jitter level, minimum output voltage level, etc while the computer has different received signal and emitted signal and recording as the system main board signal receiving sensitivity.
Description
[technical field]
The present invention relates to a kind of measurement mechanism and method of signal sensitivity, especially a kind of measurement mechanism and method that adopts the system board receiving signal sensitivity of SATA/SAS standard.
[background technology]
SATA/SAS is the IO interface standard of new generation of SATA standard and SAS standard compatibility, SAS (Serial Attached SCIS, the serial connecting small computer system interface) is hard disk IO interface standard of new generation, in the exchanges data framework, the territory of SAS, equipment and port have been inherited the corresponding concepts of SCSI and ATA fully, the electrical equipment specification of its interface and cable is taken from SATA, connecting object not only comprises starting outfit (as adapter) or target device (as hard disk or CD-ROM drive etc.), can also be expansion equipment (as router).Wherein, SATA (Serial Advanced Technology Architecture, serial high-order hard disk structure) is a kind of mode connected in series of high speed, can be widely used in the memory devices such as hard disk, CD-ROM drive and IDE matrix and have replaced traditional ATA connected mode gradually; SATA and SAS have solved the framework restriction of corresponding concurrent technique, adopt the transmission mode of single data stream, speed during than parallel transmission fast 30 times.
SATA has expanded the development blueprint of ATA technology, and the disk interconnect speed is from the 1.5Gbits/s take-off.Desktop PC, basic server and network store system are important determinative with cost all, and SATA then becomes the hard-disk interface technology of main flow in this several fields because of every GB lower cost; SAS is the successor of parallel scsi interface, and it has remedied the deficiency in the present main flow storage solution, and 16256 equipment of the maximum addressing of every port have reliably point-to-point connected in seriesly, and top speed can reach 3Gbit/s.SAS interconnect interface and SATA be compatibility and universal interconnect on specification, and SAS or SATA drive can directly be connected with the SAS environment.
SAS has defined the standard of 3 aspects, they are respectively: SSP (Serial SCSI Protocol, serial SCSI standard), STP (Serial ATA Tunneled Protocol, SATA pipeline standard) and SMP (Serial Management Protocol, serial management regulation).Wherein STP is that SATA has increased multiple goal addressing and many initiated access, and SATA equipment can be used in the SAS environment.In the SAS territory, SCSI starts and target port all uses SSP, supports its enable port of STP could visit the SATA target port and have only---and prerequisite is that the expansion equipment that this target port connects will have STP commentaries on classics SATA function.
According to the difference of environment for use, SAS connector and cable are divided into inside and outside two kinds: aerial lug is supported 4 physical connections (16 data lines), and the physical connection number of cable is then between 1～4; Internal connector is supported 2 physical connections (dual-port), and 15 pin power interfaces are (totally 29 pins) also together, and the physical connection number of cable is 1 or 2 (dual-port).
Utilization SATA/SAS standard can be carried out the test of transport property, understand the transmission performance of system board, the speed of data transmission can reach 3.0Gb/s, existing test specification only can be learnt the transmittability of system, can not know the receiving ability of system, yet, requirement for clear definition compatibility, correct sensitivity can provide the important indicator of total system effect assessment, therefore, need the receiving sensitivity of accurate measurement system mainboard.
Listed the parameter of reflection system board receiving signal sensitivity in the existing SATA/SAS standard,, set the minimum output voltage level of separating when strong, do not had minimum output voltage level and the strong level of maximal solution when strong of separating of setting as the maximum jitter level.Digital signaling zero and 1 voltage levvl of changing moment are called output voltage level, the voltage levvl of non-state exchange and the ratio of the voltage levvl between state exchange are called the strong level of separating, the shake composition that adds to system board from the external world is called jitter level, although existing SATA/SAS standard has been listed the parameter of above-mentioned measurement system mainboard receiving signal sensitivity, do not determine concrete measuring equipment and method.
[summary of the invention]
In view of above technology contents, be necessary to provide a kind of sensitivity measuring apparatus and method of system board received signal, in order to measure sensitivity based on the system board received signal of SATA/SAS standard.
A kind of measurement mechanism of system board receiving signal sensitivity, described system board adopts the SATA/SAS standard, the measurement mechanism of described system board receiving signal sensitivity comprises a computing machine and a control panel, the input and output interfaces of described computing machine links to each other with described control panel, described control panel links to each other with the SATA/SAS interconnect interface of described system board, the input and output interfaces of described system board links to each other with the input and output interfaces of described computing machine, described control panel comprises a coding circuit, the one parallel serial circuit that changes, one output buffer, one mixer, one shake generator, one input buffer circuit, a parallel circuit and a decoding circuit are changeed in one serial, described coding circuit is used for some random digital signals of described computing machine output are converted to some parallel signals of the described SATA/SAS interconnect interface of coupling, described parallel commentaries on classics serial circuit links to each other with described coding circuit, be used for converting described parallel signal to some serial signals, described output buffer links to each other with described parallel commentaries on classics serial circuit, be used for described serial signal conversion is formed in some high-speed simulation signals of physical layer operation, described output buffer comprises some registers, set described register by the bottom software of described computing machine, adjust the output voltage relevant with the system board sensitivity specification, separate strong horizontal parameter, described mixer is connected between described output buffer and the described system board, be used for that described high-speed simulation signal is mixed the back generation with a jitter level and include some simulating signals of shake composition to described system board, described shake generator links to each other with described mixer, be used to provide described jitter level, described input buffer circuit links to each other with described system board, described system board returns described simulating signal to described input buffer circuit, described input buffer circuit is exported some serial signals, described transformation from serial to parallel circuit links to each other with described input buffer circuit, be used for converting the serial signal of described input buffer circuit output to some parallel signals, described decoding circuit links to each other with described transformation from serial to parallel circuit, is used for converting the parallel signal that described transformation from serial to parallel circuit is exported to the number of digital signal and inputs to described computing machine.
A kind of measuring method of system board receiving signal sensitivity, described system board adopts the SATA/SAS standard, and the measuring method of described system board receiving signal sensitivity comprises:
(1) control panel is set, described control panel is linked to each other with the output/input interface of a computing machine, described control panel links to each other with the SATA/SAS interconnect interface of described system board, and the input and output interfaces of described system board links to each other with the output/input interface of described computing machine;
(2) bottom software by described computing machine is set at the state that send that covers with described system board;
(3) by the bottom software of described computing machine set a jitter level initial value, an output voltage level initial value and is separated strong horizontal initial value;
(4) described computing machine sends some signals to described control panel, is sent to described system board by described control panel, and described system board returns the signal that receives to described control panel, is sent to described computing machine by described control panel again;
(5) adjust signal that described computing machine the receives maximum jitter level when not conforming to the signal of its transmission, the strong level of minimum output voltage level and maximal solution is recorded as described system board receiving signal sensitivity.
With respect to prior art, the measurement mechanism of described system board receiving signal sensitivity utilizes system board to be in to cover the characteristics of receiving and transmitting signal when sending state, and come the correlation parameter of Adjustment System mainboard receiving signal sensitivity, thereby know the system board receiving signal sensitivity by described computing machine and control panel.
[description of drawings]
Fig. 1 is the connection diagram of the measurement mechanism of the system board receiving signal sensitivity of preferred embodiment of the present invention.
Fig. 2 is the control panel circuit block diagram of Fig. 1.
Fig. 3 is the process flow diagram of the measuring method of the system board receiving signal sensitivity of preferred embodiment of the present invention.
[embodiment]
Fig. 1 is the connection diagram of the measurement mechanism of the system board receiving signal sensitivity of preferred embodiment of the present invention, and it comprises a computing machine 20, one control panels 30 and a system board 40.Described computing machine 20 control test runs, and be responsible for testing adjustment; Described system board 40 adopts the SATA/SAS standard, and described system board 40 comprises an IO interface and a built-in SATA/SAS interconnect interface (figure does not show).The IO interface of described computing machine 20 (figure does not show) links to each other with described control panel 30, described control panel 30 links to each other with the SATA/SAS interconnect interface of described system board 40, and the IO interface of described system board 40 links to each other with the IO interface of described computing machine 20.
ShapeFig. 2 is control panel 30 circuit block diagrams of Fig. 1.Described control panel 30 comprises a coding circuit 31, one parallel serial circuit 32, one output buffers 33, one mixers, 34, one shake generators, 35, one input buffer circuits, 36, one serials commentaries on classics parallel circuit 37 and the decoding circuits 38 of changeing.Described computing machine 20 sends random digital signal, comprise 8 data-signal and 4 control signal, as the input of described coding circuit 31, described coding circuit 31 converts described random digital signal to the parallel signal of the described SATA/SAS interconnect interface of coupling.Because the traditional bus of computing machine is a parallel signal, new high speed signal is the lifting transfer efficiency, and reduces the wiring area, therefore begins to move towards the standard of universal serial bus, so must carry out and walk to the conversion of serial.Described parallel signal converts serial signal to through described parallel commentaries on classics serial circuit 32.Described serial signal is difficult in operation without distortion under the actual transmission environment as a kind of high-speed digital signal, so need described serial signal is converted to simulate signal.Described serial signal inputs to described output buffer 33, and described output buffer 33 is formed in described serial signal conversion the high-speed simulation signal of physical layer operation.Described output buffer 33 comprises some registers, bottom software that can be by described computing machine 20, and register as described in setting as BIOS is adjusted the output voltage level relevant with the SATA/SAS sensitivity specification, is separated parameter such as strong level.Described mixer 34 is connected between the SATA/SAS interconnect interface of described output buffer 33 and described system board 40, described high-speed simulation signal is mixed mutually with the shake that described shake generator 35 produces, and output includes the simulating signal of shake composition and gives described system board 40.In test for the allowed amount of jitter of measuring system mainboard, so add the composition of shake.
Basic Input or Output System (BIOS) by described computing machine 20 is arranged to cover the state that send with described system board, and described system board 40 is in and covers when sending state, the signal that receives can be sent immediately.After so described system board 40 is received the simulating signal of described mixer 34 outputs, immediately send out high speed analog signal to described input buffer circuit 36, described input buffer circuit 36 converts described high speed analog signal to serial signal and exports described transformation from serial to parallel circuit 37 to, by described transformation from serial to parallel circuit 37 output parallel signals, described decoding circuit 38 is decoded into described parallel signal in 8 data-signal and 4 s' the described computing machine 20 that controls signal to.
Fig. 3 is the process flow diagram of the measuring method of the system board receiving signal sensitivity of preferred embodiment of the present invention.Step 1 after the measurement mechanism of said system mainboard receiving signal sensitivity connected, starts described computing machine 20; Step 2, the bottom software by described computing machine 20 is set at the state that send that covers with described system board 40; Step 3, setting a jitter level initial value by the bottom software of described computing machine 20 is that 0 (initial value is the null representation non-jitter, the tester also can set initial value according to own experience, to reduce the test duration), an output voltage level initial value is that to separate strong horizontal initial value be 0 to 1200mv and; Step 4, send random digital signal to described control panel 30 by described computing machine 20, described control panel 30 is sent to described system board 40 after described random digital signal is changed, described system board 40 returns the signal that receives to described control panel 30, again by being sent to described computing machine 20 after described control panel 30 conversions; Step 5, whether the signal that is relatively received by described computing machine 20 conforms to the signal of its transmission, then increases jitter level and enters described step 4 if conform to, if be not inconsistent, enters step 6; Step 6 writes down described jitter level, reduces described output voltage level; Step 7 sends random digital signal to described control panel 30 by described computing machine 20; Step 8, whether the signal that is relatively received by described computing machine 20 conforms to the signal of its transmission, then reduces described output voltage level and enters described step 7 if conform to, if be not inconsistent, enters step 9; Step 9 writes down described output voltage level, increases the strong level of separating; Step 10 sends random digital signal to described control panel 30 by described computing machine 20; Step 11, whether the signal that is relatively received by described computing machine 20 conforms to the signal of its transmission, describedly separates strong level and enters step 10 if conform to then to increase, if be not inconsistent, enters step 12; Step 12, the maximum jitter level adjusting out in the record abovementioned steps, minimum output voltage level and the strong level of maximal solution when not having setting and separating strong level.
The minimum output voltage level of do not have setting when separating strong level satisfies following relational expression with the minimum output voltage level of setting when separating strong level:
T＝20log
10(V1/V2)
Wherein, minimum output voltage level when V1 separates strong level for setting, minimum output voltage level when V2 separates strong level for do not have setting, T is the strong level of maximal solution, according to the nothing adjusting out set minimum output voltage level when separating strong level and the strong level of maximal solution and above-mentioned relation formula and can draw the minimum output voltage level of setting when separating strong level.Experienced tester also can will separate strong horizontal initial value in described step 3 and be set at other value, obtain the minimum output voltage level of setting when separating strong level earlier, obtain the minimum output voltage level of do not have setting when separating strong level according to the above-mentioned relation formula again, so can save Measuring Time.
Above-mentioned steps at first adjusts signal that described computing machine 20 the receives maximum jitter level when not conforming to the signal of its transmission, adjust signal that described computing machine 20 the receives minimum output voltage level when not conforming to then with the signal of its transmission, adjust signal that described computing machine 20 the receives strong level of maximal solution when not conforming to again with the signal of its transmission, and with described maximum jitter level, the strong level of minimum output voltage level and maximal solution is as the parameter of described system board 40 receiving signal sensitivities, the adjustment order of these parameters also can be changed, and can't influence the effect of sensitivity measure.
Claims (9)
1. the measurement mechanism of a system board receiving signal sensitivity, described system board adopts the SATA/SAS standard, it is characterized in that: the measurement mechanism of described system board receiving signal sensitivity comprises a computing machine and a control panel, the IO interface of described computing machine links to each other with described control panel, described control panel links to each other with the SATA/SAS interconnect interface of described system board, the IO interface of described system board links to each other with the IO interface of described computing machine, and described control panel comprises:
One coding circuit is used for converting some random digital signals of described computing machine output to mate described SATA/SAS interconnect interface some parallel signals;
The one parallel serial circuit that changes links to each other with described coding circuit, is used for converting described parallel signal to some serial signals;
One output buffer links to each other with described parallel commentaries on classics serial circuit, be used for described serial signal conversion is formed in some high-speed simulation signals of physical layer operation, described output buffer comprises some registers, set described register by the bottom software of described computing machine, adjust the output voltage relevant, separate strong horizontal parameter with the system board sensitivity specification;
One mixer, it is connected between described output buffer and the described system board, is used for that described high-speed simulation signal is mixed the back generation with a jitter level and includes some simulating signals of shake composition to described system board;
One shake generator links to each other with described mixer, is used to provide described jitter level;
One input buffer circuit links to each other with described system board, and described system board returns described simulating signal to described input buffer circuit, and described input buffer circuit is exported some serial signals;
One serial is changeed parallel circuit and is linked to each other with described input buffer circuit, is used for converting the serial signal of described input buffer circuit output to some parallel signals;
One decoding circuit links to each other with described transformation from serial to parallel circuit, is used for converting the parallel signal that described transformation from serial to parallel circuit is exported to the number of digital signal and inputs to described computing machine.
2. the measurement mechanism of the system as claimed in claim 1 mainboard receiving signal sensitivity is characterized in that: the random digital signal of described computing machine output comprises data-signal and control signal.
3. the measuring method of a system board receiving signal sensitivity, described system board adopts the SATA/SAS standard, and it is characterized in that: the measuring method of described system board receiving signal sensitivity comprises:
(1) control panel is set, described control panel is linked to each other with the output/input interface of a computing machine, described control panel links to each other with the SATA/SAS interconnect interface of described system board, and the output/input interface of described system board links to each other with the output/input interface of described computing machine;
(2) bottom software by described computing machine is set at the state that send that covers with described system board;
(3) by the bottom software of described computing machine set a jitter level initial value, an output voltage level initial value and is separated strong horizontal initial value;
(4) described computing machine sends some signals to described control panel, is sent to described system board by described control panel, and described system board returns the signal that receives to described control panel, is sent to described computing machine by described control panel again;
(5) adjust signal that described computing machine the receives maximum jitter level when not conforming to the signal of its transmission, the strong level of minimum output voltage level and maximal solution is recorded as described system board receiving signal sensitivity.
4. the measuring method of system board receiving signal sensitivity as claimed in claim 3 is characterized in that: described step (5) comprising:
(51) adjust described maximum jitter level;
(52) adjust described minimum output voltage level;
(53) adjust the strong level of described maximal solution.
5. the measuring method of system board receiving signal sensitivity as claimed in claim 4, it is characterized in that: described step (51) comprising: whether the signal that described computing machine relatively receives conforms to the signal of its transmission, then increase jitter level if conform to, enter described step (4), if be not inconsistent, then write down described jitter level, reduce described output voltage level.
6. the measuring method of system board receiving signal sensitivity as claimed in claim 4 is characterized in that: described step (52) comprising:
(a) described computing machine sends some signals to described control panel;
(b) whether the signal that relatively receives of described computing machine conforms to the signal of its transmission, then reduces described output voltage level if conform to, and enters described step (a), if be not inconsistent, then writes down described output voltage level, increases the described strong level of separating.
7. the measuring method of system board receiving signal sensitivity as claimed in claim 4 is characterized in that: described step (53) comprising:
(c) described computing machine sends some signals to described control panel;
(d) whether the signal that relatively receives of described computing machine conforms to the signal of its transmission, then increases the described strong level of separating if conform to, and enters described step (c), if be not inconsistent, then writes down the described strong level of separating.
8. as the measuring method of claim 3 or 4 described system board receiving signal sensitivities, it is characterized in that: the minimum output voltage level when described minimum output voltage level is separated strong level for do not have setting.
9. as the measuring method of claim 3 or 4 described system board receiving signal sensitivities, it is characterized in that: the minimum output voltage level when described minimum output voltage level is separated strong level for setting.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100360949A CN100426250C (en) | 2005-07-18 | 2005-07-18 | Device and method for detecting system main board receiving signal sensitivity |
| US11/308,933 US7991045B2 (en) | 2005-06-10 | 2006-05-29 | Device and method for testing signal-receiving sensitivity of an electronic subassembly |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2005100360949A CN100426250C (en) | 2005-07-18 | 2005-07-18 | Device and method for detecting system main board receiving signal sensitivity |
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| CN1900915A CN1900915A (en) | 2007-01-24 |
| CN100426250C true CN100426250C (en) | 2008-10-15 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103308843A (en) * | 2012-03-09 | 2013-09-18 | 鸿富锦精密工业（深圳）有限公司 | Chip with receiver test function and circuit board with receiver test function |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109143043B (en) * | 2018-09-30 | 2021-04-16 | 深圳市盈科互动科技有限公司 | Controller IO input anti-shake detection method, system, device and storage medium |
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| TW230857B (en) | 1992-04-28 | 1994-09-21 | Mitsubishi Electric Machine | |
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| CN103308843A (en) * | 2012-03-09 | 2013-09-18 | 鸿富锦精密工业（深圳）有限公司 | Chip with receiver test function and circuit board with receiver test function |
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