CN100419998C - A making method for the integration circuit of the CMOS low-voltage difference adjustor - Google Patents

Abstract

This invention relates to one CMOS low voltage difference adjuster process method, which comprises integration MOS transistor tube, N shape groove JFET transistor tube and NPN transistor tube and PNP transistor tube on regular CMOS process, wherein, the MOS transistor tube adopts LDD to provide circuit work voltage; N shape groove and JFET transistor tube are used as base circuit start; the PNP transistor is used as output adjust tube to lower integration electrode resistance through adding P shape imbed layer to ensure low voltage difference circuit output voltage; the integration inner amplifier, calibration circuit and output circuit need NPN transistor tube and PNP transistor tube.

Description

A kind of manufacture method of CMOS type low-voltage difference adjustor integrated circuit

(1) technical field

The present invention relates to a kind of manufacture method of integrated circuit, particularly about a kind of manufacture method of CMOS type low-voltage difference adjustor.

(2) background technology

Power supply is the core of various electronic equipments, and wherein low-voltage difference adjustor is the important component part of power supply.Low dropout voltage is adjusted circuit and is generally comprised analog circuit and digital circuit two parts, for example all comprises modules such as little power consumption band gap reference, sleep mode, SET comparator, control and offset generating circuit, sample resistance transmission gate switch, input and output voltage monitoring, error amplifier, output stage usually.

What at present, general low-voltage difference adjustor adopted is CMOS technology or bipolar process.The low-voltage difference adjustor that adopts bipolar process to make by adjusting epitaxial thickness, can make its voltage range broad, but power consumption is bigger, can not reach the requirement of system's (such as battery power supply system) economize on electricity, therefore now less employing.Common CMOS technology low-voltage difference adjustor is owing to be subjected to the device Effect on Performance, and adjustable input voltage range is wide inadequately, generally is no more than 15V.In order to ensure output pressure reduction, in the CMOS of routine technology, add the adjustment pipe of parasitic bipolar transistor as voltage modulator, though puncture voltage is than higher, but control circuit portion C MOS device is withstand voltage not high, limited adjustable maximum input voltage scope, generally be no more than 18V, and conventional MOS transistor leakage current increases and obviously increases with drain-source voltage, and reference circuit is to workpiece current requirements harshness, and therefore conventional MOS transistor is unfavorable for that reference circuit is stable.

(3) summary of the invention

The purpose of this invention is to provide a kind of CMOS type low-voltage difference adjustor method for manufacturing integrated circuit,, and kept its low-power consumption and the low characteristics of exporting pressure reduction with the input voltage adjustable range of raising low-voltage difference adjustor.

For achieving the above object, the inventive method is on the basis of conventional cmos technology, integrated MOS transistor, N type raceway groove JFET transistor and 4 parts such as NPN pipe and PNP pipe.Wherein, MOS transistor has adopted LDD (lightly doped drain) structure, and the circuit voltage scope is provided; N type raceway groove JFET transistor is used to form the startup branch road of reference circuit or the difference of amplifier is imported pipe; PNP transistor is adjusted pipe as output, reduces collector series resistance by increasing p type buried layer, and is poor to guarantee the extremely low output voltage of low pressure difference circuit; NPN that integrated internal amplifier, reference circuit and output circuit are required and PNP transistor.

The manufacture method of its CMOS type low-voltage difference adjustor integrated circuit may further comprise the steps:

1. at highly doped N ⁺Make buried regions on the type silicon chip;

2. N grows on described buried regions ^-The type epitaxial loayer;

3. at described N ^-Adopt CMOS technology on the type epitaxial loayer, making to comprise provides the LDD of operating voltage range structure MOS transistor; Start required N type raceway groove JFET transistor with reference circuit; The NPN transistor required with internal amplifier, reference circuit and output circuit; CMOS type low-voltage difference adjustor integrated circuit with the required PNP transistor of internal amplifier, reference circuit and output circuit.

Described at highly doped N ⁺Making burried layer process on the type silicon chip comprises:

(1) at described highly doped N ⁺Clean on the type silicon chip, zero standard oxidation for the first time, zero standard photoetching, burn into remove photoresist, clean;

(2) carry out the zero standard oxidation second time, float light silicon dioxide, oxidation;

(3) buried regions photoetching, burn into remove photoresist, clean;

(4) inject preceding thin oxidation, the injection of buried regions impurity, cleaning, annealing, formation buried regions.

N grows on described buried regions ^-Type epitaxial loayer step comprises floats light silicon dioxide layer, cleaning, growth N ^-The type epitaxial loayer.

At described N ^-Adopt CMOS technology on the type epitaxial loayer, making to comprise provides the LDD of operating voltage range structure MOS transistor; Start required N type raceway groove JFET transistor with reference circuit; The NPN transistor required with internal amplifier, reference circuit and output circuit; Comprise with the CMOS type low-voltage difference adjustor integrated circuit step of the required PNP transistor of internal amplifier, reference circuit and output circuit:

(1) at the described N that grown ^-Form the P trap on the silicon chip of type epitaxial loayer;

(2) the P type penetrating region of the N type base of the LDD district of formation MOS transistor, PNP transistor, the transistorized N channel region of N type raceway groove JFET, PNP transistor;

(3) active area of formation P type and N type ring isolated area, all crystals pipe;

(4) the polycrystalline gate electrode of formation MOS transistor;

(5) form the P type source-drain area of MOS transistor, N type source-drain area, PNP transistor emitter region, NPN transistor emitter region and the grid region, the transistorized top of N type raceway groove JFET of MOS transistor;

(6) make metal thin film resistor;

(7) make contact hole, metal lead wire, passivation layer.

Beneficial effect

Because the inventive method is that on the basis of conventional cmos technology, adopted following method: 1) MOS transistor of LDD structure provides the circuit voltage scope when making the voltage adjuster integrated circuit; 2) N type raceway groove JFET transistor is as benchmark start-up circuit device; 3) PNP transistor is adjusted pipe as output, reduces collector series resistance by increasing p type buried layer, and is poor to guarantee the extremely low output voltage of low pressure difference circuit; 4) as the NPN and the PNP transistor of internal amplifier, reference circuit and output circuit.Therefore, adjustable input voltage range is brought up to 30V, and kept the low-voltage difference adjustor low-power consumption---static working current has reached the level of 20 μ A, low pressure reduction---5V output voltage, 300mA output current down output pressure reduction about 300mV, high accuracy---input voltage 6V is under 25V, line regulation at several mV with interior characteristics, and the MOS transistor leakage current of LDD substantially not everywhere drain-source voltage change and change, improve reference circuit stability greatly.

(4) description of drawings

Fig. 1 is through zero standard oxidation for the first time; Photoetching, corrosion; Silicon chip generalized section after the oxidation of secondary zero standard;

Fig. 2 is the generalized section after the silicon chip of Fig. 1 forms buried regions;

Fig. 3 is in extension on the silicon chip of Fig. 2 and the generalized section after forming the P trap of being with field oxygen layer;

Fig. 4 is the generalized section behind the pre-oxygen layer of growth on the silicon chip of Fig. 3;

Fig. 5 is the generalized section after forming LDD structure, PNP transistor N type base, N type raceway groove JFET transistor channel region, P type penetrating region on the silicon chip of Fig. 4;

Fig. 6 is the generalized section after forming P type ring isolated area and N type ring isolated area and active area on the silicon chip of Fig. 5;

Fig. 7 is the generalized section behind the polycrystalline gate electrode that forms MOS transistor on the silicon chip on Fig. 6;

Fig. 8 is the generalized section after forming P type source-drain area, N type source-drain area, PNP transistor emitter region, NPN transistor emitter region, N type raceway groove JFET grid region, transistorized top and chrome-silicon resistance on the silicon chip of Fig. 7;

Fig. 9 is the generalized section after forming lead-in wire and passivation layer on the silicon chip of Fig. 8.

(5) embodiment

Below in conjunction with specific embodiment and accompanying drawing, the present invention is described in further detail.

Original material: the N of twin polishing ⁺ Type silicon chip 1,＜100〉crystal orientation, resistivity 0.008～0.02 Ω cm, 400 microns of silicon wafer thicknesses.

1. at highly doped N ⁺Make buried regions 5 on the type silicon chip 1:

(1) with 1# liquid NH ₄OH: H ₂O ₂: H ₂O=1: 2: 7+2# liquid HCl: H ₂O ₂: H ₂O=1: respectively clean 10 minute (this cleaning process hereinafter to be referred as RCA clean) at 2: 7, zero standard oxidation for the first time, 1050 ℃ of temperature, oxide layer 2 thickness 400 ± 50nm, the zero standard photoetching, corrosion is removed photoresist, and RCA cleans, as shown in Figure 1;

(2) zero standard oxidation for the second time, 1050 ℃ of temperature, oxide layer 3 thickness 600 ± 50nm, all oxide layer on the corrosion of silicon.1050 ℃ of field oxidizing temperatures, oxide layer 4 thickness 600 ± 50nm;

(3) buried regions photoetching, corrosion is removed photoresist, and RCA cleans;

(4) before the injection, thin oxidation oxidated layer thickness is 10～15nm, BF ₂Implantation dosage 2E15/cm ², energy 70keV, RCA clean, 1050 ℃ of following nitrogen atmospheres of annealing temperature 1 hour, and the synthetic oxidation of hydrogen-oxygen 55 minutes is elevated to 1200 ℃ again and handled 5 hours down, cools under 850 ℃ of the temperature again, handles the P of formation 3～5 μ m 1 hour ⁺Buried regions 5, as shown in Figure 2.

2. N grows ^-The type epitaxial loayer:

Float all silicon dioxide of light silicon chip surface, RCA cleans, and under 1200 ℃ of the epitaxial temperatures, thickness 12 ± 2 μ m, resistivity 0.8～1.2 Ω cm form N ^-Type epitaxial loayer 6, as shown in Figure 3.

3. form the P trap:

(1) RCA cleans, 1050 ℃ of oxidizing temperatures, and oxide layer 7 thickness 600 ± 50nm, photoetching P well region, corrosion P well region removes photoresist, and RCA cleans;

(2) thin oxygen thickness 10～15nm, P well region boron implantation dosage 6E12～1.5E13/cm ², energy 60keV, RCA clean, the 1200 ℃ of following nitrogen atmospheres 420 minutes of anneal, and formation P well region 8, as shown in Figure 3.

4. form N type base, the transistorized N ditch of the N type raceway groove JFET district of LDD district, the PNP transistor of metal-oxide-semiconductor, the P type penetrating region of PNP pipe:

(1) float field oxide 7, RCA cleans;

(2) 850 ℃ of pre-oxidation, pre-oxidation layer 9 thickness 40～50nm, as shown in Figure 4;

(3) LDD district photoetching, LDD district (boron, phosphorus) impurity implantation dosage 4～7E12/cm ², energy 60keV removes photoresist;

(4) phosphorus impurities implantation dosage 1～3E13/cm ², energy 60keV, the N type base of formation PNP pipe removes photoresist;

(5) the transistorized N ditch of N type raceway groove JFET district's photoetching, phosphorus impurities implantation dosage 6E12～2E13/cm ², energy 60keV;

(6) the P penetrating region implantation dosage 4E14～6E14/cm of all p type island regions ², energy 60keV removes photoresist;

(7) RCA cleans, annealing, and 1150 ℃ of annealing 80 minutes down float pre-oxygen layer 9, form 10 (comprising PLDD and NLDD) of LDD district, N type base 11, the transistorized N channel region 12 of N type raceway groove JFET, P penetrating region 13, as shown in Figure 5.

5. form P type and N type ring isolated area, all crystals pipe source region:

(1) RCA cleans, 850 ℃ of pre-oxidation, and pre-oxidation layer 14 layer thickness 40～50nm, as shown in Figure 6;

(2) P type ring isolated area photoetching, boron injects, dosage 2～5E15/cm ², energy 80keV, remove photoresist;

(2) N type ring isolated area photoetching, phosphorus injects, dosage 2～5E15/cm ², energy 100keV removes photoresist;

(3) RCA cleans, low temperature deposition oxide layer, 700 ℃, oxide layer 15 thickness 400～500nm; Under 900 ℃, density 60 minutes forms P type ring isolated area 16 and N type ring isolated area 17;

(4) photoetching, corrosion are formed with source region 18, remove photoresist.

6. form the polycrystalline gate electrode of MOS transistor:

(1) RCA cleans, 850 ℃ of gate oxidations, grid oxygen 19 thickness 45～55nm; Low temperature deposition polysilicon layer thickness 400～500nm;

(2) phosphorus doping, square resistance 10-30 Ω cm; The photoetching of polycrystalline gate electrode, corrosion, removing photoresist forms polycrystalline gate electrode 20.As shown in Figure 7;

7. form the P type source-drain area of MOS transistor, N type source-drain area, PNP transistor emitter region, NPN transistor emitter region and the grid region, the transistorized top of N type raceway groove JFET of MOS transistor:

(1) P type source light leak is carved, and boron injects, dosage 2～5E15/cm ², energy 80keV removes photoresist;

(2) N type source light leak is carved, and phosphorus injects, dosage 2～5E15/cm ², energy 100keV removes photoresist;

(3) RCA cleans, low temperature deposition silicon dioxide, and under 700 ℃, thickness 400～500nm, 960 ℃ of following density 60 minutes;

(4) photoetching, etch pit; Finally, form P type source-drain area 21, N type source-drain area 22, PNP transistor emitter region 23, NPN transistor emitter region 24, grid region, the transistorized top of N type raceway groove JFET 25, as shown in Figure 8.

8. making metal thin film resistor:

(1) sputter Pt, Pt annealing, 300 ℃, 10 minutes, chloroazotic acid boiled;

(2) sputter chrome-silicon, titanium tungsten, photoetching, corrosion chrome-silicon, titanium tungsten remove photoresist;

(3) clean, annealing was annealed 30 minutes down, is formed chrome-silicon resistance 26, as shown in Figure 8 for 460 ℃.

The corresponding steps that chrome-silicon resistance forms is optional, if the circuit of made does not adopt chrome-silicon resistance, also can save corresponding operation.

9. make contact hole metal lead wire, passivation layer:

(1) sputter aluminum bronze, thickness 1.2 ± 0.2 μ m, the photoetching lead-in wire, the corrosion aluminum bronze removes photoresist;

(2) fuming nitric aicd cleans, and alloying was handled 30 minutes in 440 ℃ of following blanket of nitrogen, formed lead-in wire 27, as shown in Figure 9;

(3) PECVD method deposit silicon dioxide 600nm, silicon nitride 500nm, the photoetching pressure welding point, dry etching silicon nitride, silicon dioxide remove photoresist, and clean in the organic liquor, and alloying was handled 30 minutes in 440 ℃ of following blanket of nitrogen again, formed pressure welding point 28, as shown in Figure 9.

Claims (4)

1. the manufacture method of a CMOS type low-voltage difference adjustor integrated circuit, it may further comprise the steps:

(1) at highly doped N ⁺Make buried regions on the type silicon chip;

(2) N that on described buried regions, grows ^-The type epitaxial loayer;

(3) at described N ^-Adopt CMOS technology on the type epitaxial loayer, making to comprise provides the LDD of operating voltage range structure MOS transistor; Start required N type raceway groove JFET transistor with reference circuit; The NPN transistor required with internal amplifier, reference circuit and output circuit; CMOS type low-voltage difference adjustor integrated circuit with the required PNP transistor of internal amplifier, reference circuit and output circuit.

2. the manufacture method of a kind of CMOS type low-voltage difference adjustor integrated circuit as claimed in claim 1 is characterized in that: described at highly doped N ⁺Making burried layer process on the type silicon chip comprises:

(1) at described highly doped N ⁺Clean on the type silicon chip, zero standard oxidation for the first time, zero standard photoetching, burn into remove photoresist, clean;

(2) carry out the zero standard oxidation second time, float light silicon dioxide, oxidation;

(3) buried regions photoetching, burn into remove photoresist, clean;

(4) inject preceding thin oxidation, the injection of buried regions impurity, cleaning, annealing, formation buried regions.

3. the manufacture method of a kind of CMOS type low-voltage difference adjustor integrated circuit as claimed in claim 1 is characterized in that: N grows on described buried regions ^-Type epitaxial loayer step comprises floats light silicon dioxide layer, cleaning, growth N ^-The type epitaxial loayer.

4. the manufacture method of a kind of CMOS type low-voltage difference adjustor integrated circuit as claimed in claim 1 is characterized in that: at described N ^-Adopt CMOS technology on the type epitaxial loayer, making to comprise provides the LDD of operating voltage range structure MOS transistor; Start required N type raceway groove JFET transistor with reference circuit; The NPN transistor required with internal amplifier, reference circuit and output circuit; Comprise with the CMOS type low-voltage difference adjustor integrated circuit step of the required PNP transistor of internal amplifier, reference circuit and output circuit:

(1) at the described N that grown ^-Form the P trap on the silicon chip of type epitaxial loayer;

(2) form the LDD district of MOS transistor, the N type base of PNP transistor, the N channel region of N type raceway groove JFET pipe, the P type penetrating region of PNP pipe;

(3) active area of formation P type and N type ring isolated area, all crystals pipe;

(4) the polycrystalline gate electrode of formation MOS transistor;

(5) form the P type source-drain area of MOS transistor, N type source-drain area, PNP transistor emitter region, NPN transistor emitter region and the grid region, the transistorized top of N type raceway groove JFET of MOS transistor;

(6) make metal thin film resistor;

(7) make contact hole metal lead wire, passivation layer.

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