CN100481354C - Method for producing silicon contacting device on low grid spreading electric capacity isolator - Google Patents
Method for producing silicon contacting device on low grid spreading electric capacity isolator Download PDFInfo
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- CN100481354C CN100481354C CNB200610112701XA CN200610112701A CN100481354C CN 100481354 C CN100481354 C CN 100481354C CN B200610112701X A CNB200610112701X A CN B200610112701XA CN 200610112701 A CN200610112701 A CN 200610112701A CN 100481354 C CN100481354 C CN 100481354C
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Abstract
This invention discloses a method for preparing contacting apparatuses of low grid expanded capacitor SOI including: a, growing and peeling off a sacrifice oxidation layer on the silicon of SOI top layer and carrying out injection of N and P fields and isolating the obtained apparatuses electrically, B, heat-growing SiO2 layers on the surfaces of the apparatuses, injecting impurities through the SiO2 layer to adjust the threshold voltage, C, depositing a SiO2 layer by chemical gas phase on the SiO2 layer and increasing a layer of grid expanded photoetching plate to etch the heat-growing and deposited SiO2 with the photoetching glue as the mask, D, removing the glue then growing a qualified grid oxidation layer under low temperature and depositing a polysilicon layer by chemical gas phase to carry out ionic injection to the deposited polysilicon, E, annealing and etching the polysilicon with a grid photoetching plate.
Description
Technical field
The present invention relates to silicon-on-insulator in microelectronics and the solid electronics (SOI) body-contacted device preparing technical field, relate in particular to a kind of method for preparing grid expanded capacitor SOI body-contacted device.
Background technology
The SOI technology is one of main flow semiconductor technology of 21st century of generally acknowledging, and very likely substitutes the first-selection that body silicon becomes CMOS technology.On the whole, for the body silicon device, it is little that the SOI device has parasitic capacitance, low in energy consumption, and speed is fast, does not have advantages such as latch-up, and particularly the SOI device more can be handled the challenge of various adverse circumstances with confidence, as radiation environment.
SOI is divided into part depletion silicon-on-insulator (PDSOI) and full depleted silicon on insulator (FDSOI) according to the thickness of top silicon surface.Because the full-exhaustion SOI device has technological difficulties such as wayward threshold voltage, and partial depletion SOI is easy to control threshold voltage, so partial depletion SOI has obtained using widely in industrial quarters.
The partial depletion SOI device exists a neutral zone in the tagma, because this regional electromotive force is lower, the hole that ionizing collision produced (for n type field-effect transistor) can accumulate in this zone, produce a series of floater effect thus, such as kink effect, parasitic bipolar transistor effect etc.
In these floater effects, the kink effect can increase for the speed of device, but owing to can bring noise, therefore can be influential to analog circuit; The parasitic bipolar transistor effect then can cause secondary kink phenomenon, reduces the puncture voltage of device.And under the radiation parameter, floater effect also can increase bipolar gain amplifier, destroys circuit performance.
Therefore, for some circuit, people draw unnecessary electric charge by the tagma being increased an individual contact (BodyContact), thus but the property of raising circuit.
SOI device body contact form commonly used is T type grid and H type grid structure.The input capacitance of this body contact SOI device comprises positive gate capacitance and grid expanded capacitor two parts, and the SOI device input capacitance of not having a body contact includes only positive gate capacitance.Because the existence of grid expanded capacitor, increase capacitive load, according to the research of IBM Kerry Bernstein and Norman J.Rohrer, the SOI device operating rate of no body contact is faster than the body silicon device, and body silicon device operating rate contacts the SOI device faster than the body of T type grid and H type grid structure.Simultaneously, body contacts the existence of SOI device grid expanded capacitor, also can increase the power consumption of circuit, because P=C
LV
2 DDf
d, P is the dynamic power consumption that a door consumes, V
DDBe supply voltage, f
dBe average operating frequency, C
LBe load capacitance.
Therefore, how in the process of preparation SOI body-contacted device, to reduce the grid expanded capacitor of SOI body-contacted device, to improve the operating rate of circuit, reduce the power consumption of circuit, the advantage that keeps the SOI body-contacted device, effectively suppress floater effect and parasitic bipolar transistor effect, become the important technological problems that present urgent need solves.
Summary of the invention
(1) technical problem that will solve
Deficiency at above-mentioned prior art existence, main purpose of the present invention is to provide a kind of method for preparing grid expanded capacitor SOI body-contacted device, to reduce the grid expanded capacitor of SOI body-contacted device, improve the operating rate of circuit, reduce the power consumption of circuit, keep the advantage of SOI body-contacted device, effectively suppress floater effect and parasitic bipolar transistor effect.
(2) technical scheme
For achieving the above object, technical scheme of the present invention is achieved in that
A kind of method for preparing grid expanded capacitor silicon-on-insulator body-contacted device, this method comprises:
A, growth and peel off one deck sacrificial oxide layer on the SOI top layer silicon carry out that the N field is injected and the injection of P field, and the device that obtains is carried out electric isolation;
B, the heat of the device surface after electric isolation growth layer of silicon dioxide, implanted dopant penetrates the silicon dioxide layer that heat is grown, and regulates threshold voltage;
C, on the silicon dioxide layer of heat growth the chemical vapor deposition layer of silicon dioxide, increase one deck grid expansion reticle, be mask with the photoresist, the silicon dioxide of heat growth and deposit is carried out etching;
D, remove photoresist, heat growth one deck gate oxide then, chemical vapor deposition one deck polysilicon carries out ion to the polysilicon of deposit and injects;
E, annealing utilize grid version reticle that polysilicon is carried out etching, form grid expanded capacitor SOI body-contacted device.
Electric isolation described in the steps A adopts localized oxidation of silicon LOCOS technology to carry out.
Comprise in the heat growth of the device surface after electric isolation layer of silicon dioxide described in the step B: under 840 ℃, 12.04 liters/minute of logical hydrogen, 8.14 liters/minute of oxygen heated 16 minutes, and device surface heat growth one layer thickness after electric isolation is the silicon dioxide of 20nm.
Implanted dopant described in the step B penetrates the silicon dioxide layer that heat is grown, and regulates threshold voltage and comprises:
For n type field-effect transistor, inject BF
2Ion makes that the threshold voltage of n type field-effect transistor is 1.5V;
For p type field-effect transistor, inject the P ion, make the threshold voltage of p type field-effect transistor be-1.6V.
Describedly n type field-effect transistor and p type field-effect transistor are carried out the condition that ion injects be: inject energy in 30KeV to 100KeV scope, implantation dosage is 2 * 10
11Cm
-2To 5 * 10
12Cm
-2Scope, implant angle are 7 degree.
The thickness range of the silicon dioxide of chemical vapor deposition described in the step C is 20 to 50nm, and described silicon dioxide to heat growth and deposit carries out etching and adopts dry etching, keeps the silicon dioxide of grid expansion.
The one deck of heat growth described in step D gate oxide comprises: the thick gate oxide of heat growth 20nm under less than 900 ℃ of temperature;
The thickness of the polysilicon of chemical vapor deposition described in the step D is 400nm;
Described in the step D polysilicon of deposit being carried out ion injects and comprises: with energy 70KeV, and dosage 8 * 10
15Cm
-2In the polysilicon of deposit, inject the P ion.
Annealing described in the step e comprises: in nitrogen atmosphere, annealed 30 minutes down for 800 ℃;
Utilizing grid version reticle that polysilicon is carried out etching described in the step e comprises: utilize grid version reticle that polysilicon is carried out dry etching, and over etching 10%, and remove photoresist.
Further comprise after the described step e: the grid expanded capacitor SOI body-contacted device that forms is carried out lightly doped drain LDD inject, adopt spacer to form technology, generate the grid side wall, then carry out the source and leak the impurity injection, carry out rapid thermal treatment, generate Titanium silicide, and device is metallized and Passivation Treatment.
Described grid expanded capacitor SOI body-contacted device to formation carries out lightly doped drain LDD injection and is used to reduce drain terminal electric field strength and improves device lifetime;
The impurity injection is leaked in the described source of carrying out, and injects the P ion for n type field-effect transistor, injects the B ion for p type field-effect transistor, and implantation dosage is 1 * 10
15Cm
-2
The described rapid thermal treatment of carrying out is carried out under 1000 ℃, is used to activate the impurity of injection and repairs damage.
(3) beneficial effect
From technique scheme as can be seen, the present invention has following beneficial effect:
1, utilizes the present invention, because under the situation that does not change positive gate oxide thickness, increased the oxidated layer thickness of grid expansions, thereby reduced the grid expanded capacitor of SOI body-contacted device effectively, improved the operating rate of circuit, reduce the power consumption of circuit, kept the advantage of SOI body-contacted device, and effectively suppressed floater effect and parasitic bipolar transistor effect.
2, the method for preparing grid expanded capacitor SOI body-contacted device provided by the invention, compatible fully with complementary metal-oxide-semiconductor field effect transistor (SOI CMOS) technology, be applicable to low-voltage and low-power dissipation high speed integrated circuit field, can be used to commercially produce.
3, because n type field-effect transistor and p type field-effect transistor polysilicon gate are N+, the present invention has carried out heavy dose of P ion to it and has injected, so n type field-effect transistor is the surface channel device, p type field-effect transistor is the buried channel device, thereby improved the carrier mobility of p type field-effect transistor, and reduced the ratio of n type field-effect transistor and p type field-effect transistor, reduced area of chip.
Description of drawings
Fig. 1 is used to prepare the initial soi wafer structural representation of grid expanded capacitor SOI body-contacted device for the present invention;
Fig. 2 is the realization flow figure of preparation grid expanded capacitor SOI body-contacted device overall technological scheme provided by the invention;
Fig. 3-1 is for growth on the SOI top layer silicon and peel off one deck sacrificial oxide layer, carries out the schematic diagram that the N field is injected and the P field is injected;
Fig. 3-2 is the device surface heat growth silicon dioxide after electric isolation, and implanted dopant is regulated the schematic diagram of threshold voltage;
Fig. 3-3 is a chemical vapor deposition layer of silicon dioxide on the silicon dioxide layer of heat growth, and silicon dioxide is carried out the schematic diagram of etching;
Fig. 3-4 is low warm growth gate oxide, chemical vapor deposition polysilicon, and the schematic diagram that the polysilicon of deposit is carried out the ion injection;
Fig. 3-5 forms the schematic diagram of grid expanded capacitor SOI body-contacted device for polysilicon is carried out etching;
Fig. 4 is the method flow diagram of preparation grid expanded capacitor SOI body-contacted device in the embodiment of the invention;
Fig. 5 is the schematic diagram of the T type grid structure transistor domain that is used to prepare grid expanded capacitor SOI body-contacted device in the embodiment of the invention;
Fig. 6 is the schematic diagram along AA ' directional profile among Fig. 4;
Fig. 7 is the test circuit figure of check advantage of the present invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
As shown in Figure 1, Fig. 1 is used to prepare the initial soi wafer structural representation of grid expanded capacitor SOI body-contacted device for the present invention.Described soi wafer comprises top silicon surface (1), buried oxide layer (2) and silicon substrate (3).
Wherein, top silicon surface (1) is used to form active device, can form active device region therein.Buried oxide layer (2) is used for electric isolation silicon substrate (3) and top silicon surface (1).Silicon substrate (3) is used to support top silicon surface (1) and buried oxide layer (2).The making of soi wafer can utilize the conventional oxonium ion known to the person skilled in the art to inject isolation (SIMOX) technology, also can adopt other common process to comprise, for example, and thermal bonding and cutting technique etc.
As shown in Figure 2, Fig. 2 is the realization flow figure of preparation grid expanded capacitor SOI body-contacted device overall technological scheme provided by the invention, and this method may further comprise the steps:
Step 201: growth and peel off one deck sacrificial oxide layer on the SOI top layer silicon, carry out that the N field is injected and the injection of P field, the device that obtains is carried out electric isolation;
The process schematic representation corresponding with this step is shown in Fig. 3-1, and Fig. 3-1 is for growth on the SOI top layer silicon and peel off one deck sacrificial oxide layer, carries out the schematic diagram that the N field is injected and the P field is injected.
Step 202: the device surface heat growth layer of silicon dioxide after electric isolation, implanted dopant penetrates the silicon dioxide layer that heat is grown, and regulates threshold voltage;
The process schematic representation corresponding with this step is shown in Fig. 3-2, and Fig. 3-2 is the device surface heat growth silicon dioxide after electric isolation, and implanted dopant is regulated the schematic diagram of threshold voltage.
Step 203: chemical vapor deposition layer of silicon dioxide on the silicon dioxide layer of heat growth, increase one deck grid expansion reticle, be mask with the photoresist, the silicon dioxide of heat growth and deposit is carried out etching;
The process schematic representation corresponding with this step is shown in Fig. 3-3, and Fig. 3-3 is a chemical vapor deposition layer of silicon dioxide on the silicon dioxide layer of heat growth, and silicon dioxide is carried out the schematic diagram of etching.
Step 204: remove photoresist, low then warm growth one deck gate oxide, chemical vapor deposition one deck polysilicon carries out ion to the polysilicon of deposit and injects;
The process schematic representation corresponding with this step as shown in Figure 3-4, Fig. 3-4 is low warm growth gate oxide, chemical vapor deposition polysilicon, and the polysilicon of deposit carried out the schematic diagram that ion injects.
Step 205: annealing, utilize grid version reticle that polysilicon is carried out etching, form grid expanded capacitor SOI body-contacted device.
The process schematic representation corresponding with this step is shown in Fig. 3-5, and Fig. 3-5 forms the schematic diagram of grid expanded capacitor SOI body-contacted device for polysilicon is carried out etching.
Based on the realization flow figure of preparation grid expanded capacitor SOI body-contacted device overall technological scheme shown in Figure 2, Fig. 4 shows the method flow diagram of preparation grid expanded capacitor SOI body-contacted device in the embodiment of the invention, and this method may further comprise the steps:
Step 401: growth and peel off one deck sacrificial oxide layer on the SOI top layer silicon, carry out that the N field is injected and the P field is injected, device employing localized oxidation of silicon (LOCOS) technology that obtains is carried out electric isolation.
Step 402: under 840 ℃, 12.04 liters/minute of logical hydrogen, 8.14 liters/minute of oxygen heated 16 minutes, and device surface heat growth one layer thickness after electric isolation is the silicon dioxide of 20nm.
Step 403:, inject BF for n type field-effect transistor
2Ion makes that the threshold voltage of n type field-effect transistor is 1.5V; For p type field-effect transistor, inject the P ion, make the threshold voltage of p type field-effect transistor be-1.6V; Describedly n type field-effect transistor and p type field-effect transistor are carried out the condition that ion injects be: inject energy in 30KeV to 100KeV scope, implantation dosage is 2 * 10
11Cm
-2To 5 * 10
12Cm
-2Scope, implant angle are 7 degree.
Step 404: chemical vapor deposition one deck thickness range is 20 to 50nm silicon dioxide on the silicon dioxide of implanted dopant, increase one deck grid expansion reticle (20), with the photoresist is mask, and the silicon dioxide of heat growth and deposit is carried out dry etching, keeps the silicon dioxide of grid expansion.
Step 405: remove photoresist, the thick gate oxide of heat growth 20nm under less than 900 ℃ of temperature then, chemical vapor deposition one layer thickness is the 400nm polysilicon.
Step 406: with energy 70KeV, dosage 8 * 10
15Cm
-2In the polysilicon of deposit, inject the P ion.
Step 407: in nitrogen atmosphere, annealed 30 minutes down for 800 ℃.
Step 408: utilize grid version reticle that polysilicon is carried out dry etching, over etching 10%, and remove photoresist, it is long to have formed 0.8 μ m grid, promptly forms grid expanded capacitor SOI body-contacted device.
Step 409:, the grid expanded capacitor SOI body-contacted device that forms is carried out lightly doped drain LDD inject in order to reduce drain terminal electric field strength and to improve device lifetime.
Step 410: adopt spacer to form technology, generate the grid side wall.
Step 411: inject the P ion for n type field-effect transistor, inject the B ion for p type field-effect transistor, implantation dosage is 1 * 10
15Cm
-2
Step 412: for impurity and the reparation damage that activates injection, under 1000 ℃, wafer is carried out rapid thermal treatment, generate Titanium silicide, and device is metallized and Passivation Treatment.
As shown in Figure 5, Fig. 5 is the schematic diagram of the T type grid structure transistor domain that is used to prepare grid expanded capacitor SOI body-contacted device in the embodiment of the invention.This T type grid structure transistor domain includes source region version (50), and N+ injects version (70), and P+ injects version (40), contact hole version (60), grid version (30), grid expansion reticle (20).Wherein, grid expansion reticle (20) are the reticle that the present invention increases newly, do not contain this layer photoetching version in the common SOI body-contacted device domain.
As shown in Figure 6, Fig. 6 is the schematic diagram along AA ' directional profile among Fig. 5.Wherein comprise top silicon surface (1), buried oxide layer (2), silicon substrate (3), polysilicon (10), grid expansion oxide layer (02), positive gate part oxide layer (03).
As shown in Figure 7, Fig. 7 is the test circuit figure of check advantage of the present invention.This test circuit figure is three grades of inverter series circuits.N type field-effect transistor breadth length ratio is 8 μ m/0.8 μ m, and p type field-effect transistor breadth length ratio is 16 μ m/0.8 μ m.Circuit working is under 5V voltage.The signal source rising edge of a pulse time is 0.1nS, and the trailing edge time is 0.1nS, and the cycle is 40nS, duty ratio 50%.
Electric capacity shown in the figure is n type field-effect transistor and p type field-effect transistor grid expanded capacitor sum.Obtain single-stage inverter delay time by second level inverter input A node and output B node.
Second level inverter TpLH equals to export B node rising edge value 2.5V time corresponding and deducts input A node trailing edge value 2.5V time corresponding;
TpHL equals to export B node trailing edge value 2.5V time corresponding and deducts input A node rising edge value 2.5V time corresponding.
Total Tp time of delay (total)=1/2 (TpLH+TpHL).
The electric capacity that does not adopt the inventive method is 2 * (2 * 2 * 10
-12m
2* 1.05 * 10
-10F/m)/(20 * 10
-9M)=and 42fF, single-stage inverter delay time is 0.5 * (21-20.6+40.9-40.3)=500pS.
Adopting the electric capacity of the inventive method is 2 * (2 * 2 * 10
-12m
2* 1.05 * 10
-10F/m)/(72 * 10
-9M)=and 11.67fF, single-stage inverter delay time is 0.5 * (20.7-20.5+40.6-40.2)=300pS.
Because P=C
LV
2 DDf
d, P is the dynamic power consumption that a door consumes, V
DDBe supply voltage, f
dBe average operating frequency, C
LBe load capacitance.So adopt the inventive method to reduce grid expansion electric capacity, mean the reduction of node load electric capacity, thereby can reduce power consumption.
This method for preparing grid expanded capacitor SOI body-contacted device provided by the invention greatly reduces SOI body-contacted device grid expanded capacitor, improved the operating rate of circuit, reduced the power consumption of circuit, also kept simultaneously the advantage of SOI body-contacted device, floater effect and parasitic bipolar transistor effect have effectively been suppressed.
In addition, the present invention and complementary metal-oxide-semiconductor field effect transistor (SOICMOS) technology is compatible fully, is applicable to low-voltage and low-power dissipation high speed integrated circuit field, can be used to commercially produce.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1, a kind of method for preparing grid expanded capacitor silicon-on-insulator body-contacted device is characterized in that this method comprises:
A, growth and peel off one deck sacrificial oxide layer on silicon-on-insulator SOI top layer silicon carry out that the N field is injected and the injection of P field, and the device that obtains is carried out electric isolation;
B, the heat of the device surface after electric isolation growth layer of silicon dioxide, implanted dopant penetrates the silicon dioxide layer that heat is grown, and regulates threshold voltage;
C, on the silicon dioxide layer of heat growth the chemical vapor deposition layer of silicon dioxide, increase one deck grid expansion reticle, be mask with the photoresist, the silicon dioxide of heat growth and deposit is carried out etching;
D, remove photoresist, heat growth one deck gate oxide then, chemical vapor deposition one deck polysilicon carries out ion to the polysilicon of deposit and injects;
E, annealing utilize grid version reticle that polysilicon is carried out etching, form grid expanded capacitor SOI body-contacted device.
2, the method for preparing grid expanded capacitor silicon-on-insulator body-contacted device according to claim 1 is characterized in that, electric isolation described in the steps A adopts localized oxidation of silicon LOCOS technology to carry out.
3, the method for preparing grid expanded capacitor silicon-on-insulator body-contacted device according to claim 1 is characterized in that, the device surface heat growth layer of silicon dioxide described in the step B after electric isolation comprises:
Under 840 ℃, 12.04 liters/minute of logical hydrogen, 8.14 liters/minute of oxygen heated 16 minutes, and device surface heat growth one layer thickness after electric isolation is the silicon dioxide of 20nm.
4, the method for preparing grid expanded capacitor silicon-on-insulator body-contacted device according to claim 1 is characterized in that, implanted dopant described in the step B penetrates the silicon dioxide layer that heat is grown, and regulates threshold voltage and comprises:
For n type field-effect transistor, inject BF
2Ion makes that the threshold voltage of n type field-effect transistor is 1.5V;
For p type field-effect transistor, inject the P ion, make the threshold voltage of p type field-effect transistor be-1.6V.
5, the method for preparing grid expanded capacitor silicon-on-insulator body-contacted device according to claim 4 is characterized in that, describedly n type field-effect transistor and p type field-effect transistor are carried out the condition that ion injects is:
Inject energy in 30KeV to 100KeV scope, implantation dosage is 2 * 10
11Cm
-2To 5 * 10
12Cm
-2Scope, implant angle are 7 degree.
6, the method for preparing grid expanded capacitor silicon-on-insulator body-contacted device according to claim 1 is characterized in that,
The thickness range of the silicon dioxide of chemical vapor deposition described in the step C is 20 to 50nm, and described silicon dioxide to heat growth and deposit carries out etching and adopts dry etching, keeps the silicon dioxide of grid expansion.
7, the method for preparing grid expanded capacitor silicon-on-insulator body-contacted device according to claim 1 is characterized in that,
The one deck of heat growth described in step D gate oxide comprises: the thick gate oxide of heat growth 20nm under less than 900 ℃ of temperature;
The thickness of the polysilicon of chemical vapor deposition described in the step D is 400nm;
Described in the step D polysilicon of deposit being carried out ion injects and comprises: with energy 70KeV, and dosage 8 * 10
15Cm
-2In the polysilicon of deposit, inject the P ion.
8, the method for preparing grid expanded capacitor silicon-on-insulator body-contacted device according to claim 1 is characterized in that,
Annealing described in the step e comprises: in nitrogen atmosphere, annealed 30 minutes down for 800 ℃;
Utilizing grid version reticle that polysilicon is carried out etching described in the step e comprises: utilize grid version reticle that polysilicon is carried out dry etching, and over etching 10%, and remove photoresist.
9, the method for preparing grid expanded capacitor silicon-on-insulator body-contacted device according to claim 1 is characterized in that, further comprises after the described step e:
The grid expanded capacitor SOI body-contacted device that forms is carried out lightly doped drain LDD inject, adopt spacer to form technology, generate the grid side wall, then carry out the source and leak the impurity injection, carry out rapid thermal treatment, generate Titanium silicide, and device is metallized and Passivation Treatment.
10, the method for preparing grid expanded capacitor silicon-on-insulator body-contacted device according to claim 9 is characterized in that,
Described grid expanded capacitor SOI body-contacted device to formation carries out lightly doped drain LDD injection and is used to reduce drain terminal electric field strength and improves device lifetime;
The impurity injection is leaked in the described source of carrying out, and injects the P ion for n type field-effect transistor, injects the B ion for p type field-effect transistor, and implantation dosage is 1 * 10
15Cm
-2
The described rapid thermal treatment of carrying out is carried out under 1000 ℃, is used to activate the impurity of injection and repairs damage.
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|---|---|---|---|
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6071783A (en) * | 1998-08-13 | 2000-06-06 | Taiwan Semiconductor Manufacturing Company | Pseudo silicon on insulator MOSFET device |
| US6090673A (en) * | 1998-10-20 | 2000-07-18 | International Business Machines Corporation | Device contact structure and method for fabricating same |
| CN1507072A (en) * | 2002-11-26 | 2004-06-23 | ��������ͨ���о�Ժ | Semiconductor device with T-shape grid electrode and producing method thereof |
| CN1585138A (en) * | 2004-06-08 | 2005-02-23 | 江苏长电科技股份有限公司 | Radio frequency SIO power NMOSFET with stepped grid oxidized layer and manufacturing method thereof |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6071783A (en) * | 1998-08-13 | 2000-06-06 | Taiwan Semiconductor Manufacturing Company | Pseudo silicon on insulator MOSFET device |
| US6090673A (en) * | 1998-10-20 | 2000-07-18 | International Business Machines Corporation | Device contact structure and method for fabricating same |
| CN1507072A (en) * | 2002-11-26 | 2004-06-23 | ��������ͨ���о�Ժ | Semiconductor device with T-shape grid electrode and producing method thereof |
| CN1585138A (en) * | 2004-06-08 | 2005-02-23 | 江苏长电科技股份有限公司 | Radio frequency SIO power NMOSFET with stepped grid oxidized layer and manufacturing method thereof |
Non-Patent Citations (1)
| Title |
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| Simulation of a Double-Gate Dynamic Threshold VoltageFullyDepleted Silicon-on-Insulator nMOSFET. 毕津顺，吴峻峰，海潮和.半导体学报，第27卷第1期. 2006 * |
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