CN100416492C - Random number generator and probability generator - Google Patents

Abstract

A random number generator characterized in that a flip-flop that determines an output state (0 or 1) corresponding to a phase difference of signals input to two input parts, a delay part that causes a phase difference between the two input signals, and a The above-mentioned input signal controls the above-mentioned phase difference so that the occurrence rate of 0 or 1 output by the flip-flop is constant in a predetermined repetition cycle.

Description

Random number generator and probability generator

technical field

The present invention relates to a random number generating device suitable for use in scientific and technical calculations, game machines, encryption processing, etc., and a probability generating device formed using the random number generating device. Furthermore, the present invention relates to a random number generator that automatically adjusts the phase difference between two input signals input to a flip-flop so that the occurrence rate of 0 or 1 output by the flip-flop is constant, and particularly relates to an effective phase adjustment unit.

Background technique

The use of random numbers is indispensable for high-level scientific and technical calculations, game machines, encryption processing, etc., and in recent years, there are no random numbers that have identity (when there is no difference in the occurrence rate due to random numbers) and do not have random numbers There is an increasing need for high-performance natural random number (intrinsic random number) generators and probability generators with regularity, correlation, and periodicity.

In addition, as the above-mentioned natural random number/probability generator, it is known to use random pulses obtained by, for example, weak radiation, thermal noise of resistors and diodes, or vibration of a quartz oscillator.

However, the random number/probability generation circuit using random pulses from the above-mentioned natural phenomena includes many analog elements such as the above-mentioned random pulse generation source, signal interrupter, waveform shaping, and identity optimization circuit. Therefore, the circuit Logic LSIs that become larger and more complex, making it difficult to mount them as an issue, are disadvantageous for use in ultra-small and thin high-tech devices such as IC cards that are expected to be expected in the future. Due to difficulty in making LSI, productivity deteriorates and cost increases.

In particular, when using thermal noise, it is easily affected by external noise, power supply fluctuations, or temperature, and the disadvantage is that the operation stability is lacking. When using radiation, there is concern about the impact of radiation on the environment even if it is weak. Therefore, the amount of radiation that can be used There is a limit, and thus, it is difficult to cope with the use of generating a large number of random numbers in a short time.

Contents of the invention

The object of the present invention is to provide a high-performance and high-security random number generator and probability generator, by realizing the generation of natural random numbers by the structure of a digital circuit, which solves the problems of the above-mentioned prior art. Regularity, correlation, periodicity and other issues.

Another object of the present invention is to provide a high-performance random number generator and probability generator, which solves the above-mentioned problems in the prior art, realizes the miniaturization and thinning of LSI loading, and facilitates production. Issues such as identity, regularity, correlation, and periodicity arise.

Another object of the present invention is to provide a high-speed and high-performance random number generator.

Another object of the present invention is to provide a 1-bit random number generator, a multi-bit random number generator and a probability generator, which can easily check the appearance identity of random number data and improve reliability.

Here, a D-type flip-flop is known as a flip-flop that determines an output state (0 or 1) based on a phase difference between signals input to two input units.

As shown in FIG. 13, this D-type flip-flop has a clock terminal CLK and a data terminal D as input parts. As shown in the input and output waveforms shown in FIGS. 14(a) and 14(b), when the rising edge of CLK The state (0 or 1) of the data terminal D determines the state of the outputs Q and Q (Q: an inverted output of Q), a so-called edge-triggered type flip-flop.

Here, when the difference (phase difference) Δt between the rising edge time of the CLK signal and the rising edge time of the D signal is approached to 0 from the state of FIG. 14(a) or FIG. 14(b), as shown in FIG. 14(c), There is a phase difference range in which the flip-flop outputs Qn and /Qn are uncertain.

The present invention actively exploits the non-deterministic behavior of such triggers to generate natural random numbers.

<First Form of the Invention>

That is, the random number generator described in technical solution 1 is characterized in that there is a flip-flop that determines the output state (0 or 1) corresponding to the phase difference of the signals input to the two input parts; The output delay circuit and the selection circuit corresponding to the selected input selects one of the delayed outputs to generate a phase difference between the two input signals; and the feedback circuit has: a first step for measuring a predetermined repetition period of the above-mentioned input signal a counter; a second counter that counts the number of occurrences of 0 or 1 output by the above-mentioned flip-flop in each repetition cycle; a register that holds the measurement output of the second counter in each repetition cycle; and generates a register for setting the output of the above-mentioned flip-flop A constant setter for comparison data of the occurrence rate of 0 or 1; a comparator for comparing the output data of the above-mentioned register with the size of the above-mentioned comparison data; a reversible counter for generating a selection signal of the above-mentioned selection circuit according to the comparison output of the comparator, and A feedback circuit that controls the above-mentioned phase difference through the above-mentioned input signal so that the occurrence rate of 0 or 1 output by the flip-flop is constant in a predetermined repetition period.

In the structure described in the above technical solution, regarding the generation of random numbers, all digital circuits are used to realize the generators of natural random numbers with the same type and no regularity, correlation, or periodicity. By appropriately setting the repetition period of the input signal and the resolution of the set phase difference of the delay unit, a large number of random numbers can be generated at high speed. Moreover, it is a digital circuit structure, and it is easy to adapt to LSI.

According to the random number generator described in technical solution 4, it is characterized in that as the setting data of the repetition cycle set in the above-mentioned first counter and the comparison data of the above-mentioned comparator, the random number output by the above-mentioned trigger is used or the random number is encrypted. A random number composed of numbers.

In this configuration, the periodicity associated with the generation of random numbers is completely lost.

According to the random number generating device described in technical solution 5, it is characterized in that there is an auxiliary random number generating device having the same structure as the random number generating device described in technical solution 3, as the setting of the repetition period set in the first counter The data and the comparison data of the above-mentioned comparator use the random number generated by the above-mentioned auxiliary random number generator.

According to the random number generator described in technical solution 6, it is characterized in that there is an auxiliary random number generator with the same structure as the random number generator described in technical solution 3, as the setting of the repetition period set in the first counter The data and the comparison data of the comparator use a random number generated by the auxiliary random number generator and a random number obtained by encrypting the random number generated by the random number generator.

In the structures described in claim 5 and claim 6, none of the random number data from the auxiliary random number generator is output to the outside (other than the random number generator), so the nature, tendency, periodicity, etc. of the generated random numbers cannot be determined. Predictions are thus completely natural random numbers.

The random number generator according to claim 7 is characterized in that a waveform shaping circuit is added to the input signal line of the flip-flop.

By blunting the input signal generated by waveform shaping, the uncertain action range of the flip-flop is expanded, and random numbers are easily generated.

The random number generator according to claim 8 is characterized by comprising an initial control circuit which sets the comparison data of the comparator to 0 for a predetermined period when the power is turned on.

This shortens the period from when the power is turned on to when an appropriate random number is generated.

The random number generator according to technical solution 9 is characterized in that a D-type flip-flop or an R-S flip-flop is used as the flip-flop.

The random number generator according to technical solution 10 is characterized in that a plurality of random number generators according to technical solution 1 are arranged in parallel. There is no relationship between the random number generators constituting this parallel type random number generator. Each random number generator has no regularity, correlation or periodicity.

The probability generating device according to technical solution 11 is characterized by having the random number generating device described in technical solution 1.

As described above, the random number generators have the same type and have no regularity, correlation, or periodicity, so the overall probability distribution is the same.

<Second Embodiment>

As described above, a D-type flip-flop is known as a flip-flop that determines an output state (0 or 1) based on a phase difference between signals input to two input units. As shown in Figure 13, the D-type flip-flop has a clock terminal CLK and a data terminal D as the input part, and the output Q and Q are determined according to the state (0 or 1) of the data terminal D when the rising edge of CLK is input (Q: Q The state of the inverted output) is a so-called edge-triggered flip-flop.

Here, when the difference (phase difference) Δt between the rising edge time of the CLK signal and the rising edge time of the D signal is approached to 0 from the state of FIG. 14(a) or FIG. 14(b), as shown in FIG. 14(c), There is a phase difference range in which the flip-flop outputs Qn and /Qn are uncertain. In addition, the uncertain operation range of the flip-flop expands when the jitter of the input signal increases, making it easier to generate random numbers.

The present invention increases the jitter of the above-mentioned input signal, and actively utilizes the uncertain operation of the flip-flop at this time to generate a natural random number.

That is, according to the random number generator described in claim 12, a flip-flop outputting a 1-bit serial random number RND, a 2-system delay circuit providing a phase difference between the flip-flop inputs (CLK signal), and a measurement The specified repetition period of the CLK signal, and monitor the number of 1s or 0s of the trigger output (random number data RND) in the specified period, and automatically perform an automatic operation to maintain its occurrence rate at a certain value (for example, 50%). The feedback control phase control circuit configuration for adjusting the delay time of the above-mentioned delay circuit is characterized in that a noise generating source, an amplifying circuit for amplifying the noise, and a device for jittering the input signal by the amplified noise signal are added to the input line of the above-mentioned trigger. A jitter generating circuit composed of a mixing circuit.

The random number generating device according to technical solution 13 is characterized in that the above-mentioned jitter generating circuit is added to the two input lines of the above-mentioned flip-flop.

The random number generator according to claim 14 is characterized in that the jitter generating circuit is added to one input line of the flip-flop, and an integrating circuit for delay time correction is added to the other input line.

Here, in the structures described in the technical solution 12 to the technical solution 14, the input signal input to the flip-flop generates jitter, which expands the uncertain action range of the flip-flop. Thus, it is easy to generate completely natural random numbers that have identity and do not have regularity, correlation, and periodicity.

The random number generator according to claim 15 is characterized in that it includes a latch means for latching the output of the jitter generating circuit at a repetition period of the input signal.

In this configuration, one input signal is obtained in one random number generation, and the random number generation operation is stabilized.

According to the random number generating device described in technical solution 16, a flip-flop outputting a 1-bit serial random number RND and a 2-system delay circuit providing a phase difference between the flip-flop inputs (CLK signal), the above-mentioned flip-flop input line Above, the jitter generating circuit is composed of a noise source, an amplifying circuit for amplifying the noise, a mixing circuit for jittering the input signal by amplifying the noise signal, and measuring the specified repetition cycle of the CLK signal, and monitoring the specified cycle The number of 1s or 0s in the flip-flop output (random number data RND), and the phase control of the feedback control that automatically adjusts the delay time of the above-mentioned delay circuit in order to maintain its occurrence rate at a constant value (for example, 50%) The circuit configuration is characterized in that on the data input line of the above-mentioned flip-flop, a gate circuit for detecting the phase difference of the above-mentioned two input signals, a P-channel transistor and an N-channel transistor for turning on/off the outputs of each gate circuit are added. A phase-voltage conversion circuit composed of a series circuit of transistors and an RC integrating circuit connected to its output side.

In this structure, the output of the phase-voltage conversion circuit generates a voltage approximately equal to the threshold voltage of the semiconductor element (such as the buffer in Figure 39) connected to it, and automatically adjusts the phase difference between the two input signals (that is, the phase-voltage The output of the conversion circuit) makes the occurrence rate of 1 or 0 output by the flip-flop constant.

The random number generator according to claim 17 is characterized in that the phase-voltage conversion circuit has an enabling unit that operates only when operation is permitted.

In this structure, an action permission signal is issued only when a random number is needed, so that the activation period of the circuit can be freely controlled, thereby realizing power saving.

According to the random number generator described in technical solution 18, it is characterized in that the output of the above-mentioned phase-voltage conversion circuit is added with a noise generating source, an amplifying circuit for amplifying the noise, and a frequency mixing device for dithering the input signal through the amplified noise signal. The circuit constitutes the jitter generation circuit.

In this structure, the uncertainty factor of the occurrence probability of 1 or 0 of the flip-flop output is positively increased. Therefore, it is easy to generate more stable natural random numbers that have the same type and do not have regularity, correlation, and periodicity.

The random number generator according to claim 19 is characterized in that it includes enabling means that operates only when the operation is permitted.

In this structure, an action permission signal is issued only when a random number is needed, so that the activation period of the circuit can be freely controlled, thereby realizing power saving.

According to the random number generating device described in technical solution 20, it is characterized in that the above-mentioned mixing circuit is composed of an integrating circuit, a series-connected P-channel transistor circuit and a series-connected N-channel transistor circuit which respectively use the integral output signal and the above-mentioned amplified noise signal as inputs The series connection circuit constitutes.

According to the random number generator described in technical solution 21, it is characterized in that the above-mentioned mixing circuit is composed of a series transistor circuit of an N-channel transistor circuit and a P-channel transistor circuit that takes the composite signal of the above-mentioned amplified noise signal and the above-mentioned input signal as an input. constitute.

According to the random number generator described in claim 22, an R-S flip-flop that outputs a 1-bit serial random number RND, a delay circuit of two systems that gives a phase difference between the inputs of the R-S flip-flop, and a measurement CLK The specified repetition period of the signal, and monitor the number of 1 or 0 of the trigger output (random number data RND) in the specified period, and automatically adjust to maintain its occurrence rate at a certain value (for example, 50%) The phase control circuit configuration of the feedback control of the delay time of the above-mentioned delay circuit is characterized in that a P-channel transistor is connected in series on the power supply side of the R-side gate circuit or the S-side gate circuit of the internal transistor circuit constituting the above-mentioned R-S flip-flop, An N-channel transistor is connected in series on the GND side, and a noise generating source and an amplifying circuit for amplifying the noise are connected to the input of the above-mentioned P-channel transistor and the N-channel transistor, and the noise signal is changed by the amplified side of the above-mentioned gate circuit. threshold voltage.

According to the random number generator described in claim 23, an R-S flip-flop that outputs a 1-bit serial random number RND, a delay circuit of two systems that gives a phase difference between the inputs of the R-S flip-flop, and a measurement CLK signal The specified repetition period, and monitor the number of 1 or 0 of the trigger output (random number data RND) in the specified period, and automatically adjust the above-mentioned The phase control circuit configuration of the feedback control of the delay time of the delay circuit is characterized in that a P-channel transistor is connected in series on the power supply side of the R-side gate circuit or the S-side gate circuit of the internal transistor circuit constituting the above-mentioned R-S flip-flop respectively, An N-channel transistor is connected in series on the GND side, and a noise generating source and an amplifying circuit for amplifying the noise are connected to the input of the above-mentioned P-channel transistor and N-channel transistor, and the threshold value of the above-mentioned gate circuit of both sides is changed by the amplified noise signal. Voltage.

In the R-S flip-flop, when the phase difference between the rising edges of the R-side input signal and the S-side input signal is close to 0, a metastable phenomenon occurs. When this phenomenon occurs, it takes time until the trigger output is confirmed, and the output state after a certain period of time remains 0 or 1 or the threshold voltage, or is in an oscillating state. Here, in the structures described in the technical solution 22 and the technical solution 23, by changing the threshold voltage of the R-side and/or S-side gate circuit, the metastable state can be instantly entered into a stable state of 1 or 0. Moreover, the phase difference between the two input signals is automatically adjusted so that the occurrence rate of 1 or 0 output by the flip-flop remains constant.

According to the random number generator described in technical solution 24, it is characterized in that the above-mentioned amplifying circuit is composed of a series input circuit composed of a capacitor and a resistor and a series circuit of a P-channel transistor and an N-channel transistor, and the input-output of the transistor circuit Insert a resistor between them.

According to the random number generator described in technical solution 25, it is characterized in that the amplifying circuit is composed of a series input circuit composed of a capacitor and a resistor and a series circuit of a P-channel transistor and an N-channel transistor, and the input-output of the transistor circuit A capacitor and a resistor are inserted in parallel between them.

According to the random number generating device described in technical solution 26, it is characterized in that the amplifier circuits are connected in series in multiple stages.

The random number generator according to claim 27 is characterized in that the noise generating source is configured by connecting a P-channel transistor and an N-channel transistor in series, and short-circuiting between an input and an output.

The random number generator according to claim 28 is characterized in that the noise generator is configured by connecting a P-channel transistor and an N-channel transistor in series, and inserting a resistor between the input and the output.

According to the random number generating device described in technical solution 29, it is characterized in that the above-mentioned noise generating source is connected in series with a P-channel transistor and an N-channel transistor, and a resistor is inserted between the input and the output while inserting a resistor between the input and GND. A series circuit composed of a capacitor and a capacitor is formed.

According to the random number generating device described in technical solution 30, it is characterized in that the above-mentioned noise generating source is connected in series with a P-channel transistor and an N-channel transistor, and a resistor is inserted between the input and the output while a resistor is inserted between the input and the power supply. A series circuit composed of a capacitor and a capacitor is formed.

The random number generator according to claim 31 is characterized in that the noise generating source is configured by short-circuiting between the input and the output of the N-channel transistor and inserting a resistor between the output and the power supply.

The random number generator according to claim 32 is characterized in that the noise generators are configured by inserting resistors between the input and output of the N-channel transistor and between the output and the power supply.

The random number generator according to claim 33 is characterized in that the noise generating source short-circuits between the input and output of the P-channel transistor and inserts a resistor between the output and GND.

The random number generating device according to claim 34 is characterized in that the noise generating sources are configured by inserting resistors between input and output and between output and GND of the P-channel transistor, respectively.

Here, in the structures described in the above-mentioned technical solution 27 to technical solution 34, weak thermal noise generated by circuit elements (transistors, resistors, capacitors, or combinations thereof) in an active state is used as a noise generation source, so by simply The circuit structure can be realized very cheaply.

The probability generating device according to technical solution 35 is characterized in that it is composed of the random number generating device according to technical solution 12.

In this structure, the random number generating device can realize an ideal probability generating device by having identity, irregularity, correlation and periodicity. If used for encrypted communication, etc., it becomes possible to perform communication which is advantageous in terms of security.

<The third form of invention>

As described above, a D-type flip-flop is known as a flip-flop that determines an output state (0 or 1) based on a phase difference between signals input to two input units.

As shown in Figure 13, the D-type flip-flop has a clock terminal CLK and a data terminal D as the input part, and the output Q and Q are determined according to the state (0 or 1) of the data terminal D when the rising edge of CLK is input (Q: Q The state of the inverted output) is a so-called edge-triggered flip-flop.

Here, when the difference (phase difference) Δt between the rising edge time of the CLK signal and the rising edge time of the D signal is approached to 0 from the state of FIG. 14(a) or FIG. 14(b), as shown in FIG. 14(c), There is a phase difference range in which the flip-flop outputs Qn and /Qn are uncertain. In addition, the uncertain operation range of the flip-flop expands when the jitter of the input signal increases, making it easier to generate random numbers.

The present invention is a random number generator that positively utilizes the uncertain operation of such triggers.

That is, according to the random number generator described in claim 36, a flip-flop that determines an output state (0 or 1) based on a phase difference between two input signals, a phase adjustment unit that adjusts the phase of the input signal, and a feedback circuit The part has a first counter that measures a value (m) of 1/2 of a predetermined repetition period [number of clocks (2×m)] from the input signal clock; a second counter that measures the value (m) in each repetition period , the number of occurrences of "1" (or "0") of the output of the above-mentioned flip-flop; the register, in each repetition cycle, fetches the count value of the above-mentioned second counter and saves; the constant setter is used for When the count value is set in the register, the second counter above is cleared, and the occurrence rate of "1" (or "0") output by the flip-flop is set; the comparator saves the data (n) Make a comparison output corresponding to the comparison result n>m or n=m or n<m with the comparison data (m) from the above-mentioned constant setter; the third counter operates in the operation mode set by the above-mentioned comparison output , outputting the above-mentioned count data as the selection signal of the selector; and controlling the above-mentioned phase difference so that the above-mentioned selector outputs a specified delay signal of the clock signal selected by the selection signal, and the occurrence rate of 0 or 1 output by the above-mentioned flip-flop is within the specified Converging to a constant value in the repeated cycle, it is characterized in that the above-mentioned phase adjustment part is provided with a first delay and a second delay for delaying the output of the input signal step by step, and a first delay for selecting one of the delay outputs according to the selection input. A phase adjustment circuit composed of a delayer and a third counter that controls the above-mentioned selection input is used as a fine adjustment part, and at each of the above-mentioned delayed outputs, a rough adjustment part composed of a third delay and a second selector, and a fourth delay, The coarse adjustment part constituted by the third selector is provided with a fourth counter indicating the selection operation of the above-mentioned second selector and third selector, and a delay of each stage of the first delay and the second delay for fine adjustment. The time is set to less than about 1/20 of the delay time of the third delay and the fourth delay for rough adjustment, so that the phase adjustment range can be enlarged and the phase adjustment time can be shortened.

The random number generator according to technical solution 37 is characterized in that the rough adjustment unit and the fine adjustment unit are respectively composed of a delay circuit that delays and outputs the input signal in multiple stages, a selection circuit that selects one of the delayed outputs according to the selection input, and An up-down counter that controls the above-mentioned selection input based on the above-mentioned phase difference is configured.

In the structure described in the technical solution 36 or the technical solution 37, the phase adjustment range can be enlarged and the phase adjustment can be effectively performed by performing rough phase adjustment and fine adjustment.

According to the random number generator described in claim 38, a flip-flop that determines an output state (0 or 1) based on a phase difference between two input signals, a phase adjustment unit that adjusts the phase of the input signal, and a feedback circuit unit, It has a first counter that measures a value (m) of 1/2 of a predetermined repetition period [number of clocks (2×m)] from an input signal clock; a second counter that measures the above-mentioned The number of occurrences of "1" (or "0") of the output of the flip-flop; the register, in each repetition cycle, fetches the count value of the above-mentioned second counter and saves it; the constant setter is used for setting the When the count value is set in the register, the above-mentioned second counter is cleared, and the occurrence rate of "1" (or "0") output by the trigger is set; the comparator compares the saved data (n) of the above-mentioned register with the In the comparison data (m) of the above-mentioned constant setter, make a comparison output corresponding to the comparison result n>m or n=m or n<m; the third counter operates in the operation mode set by the above-mentioned comparison output, and The above-mentioned counting data is output as the selection signal of the selector; and the above-mentioned phase difference is controlled so that the above-mentioned selector outputs the specified delay signal of the clock signal selected by the selection signal, and the occurrence rate of 0 or 1 output by the above-mentioned flip-flop is within the specified repetition period A feedback circuit whose inner convergence is a constant value is characterized in that the phase adjustment unit is composed of a delay circuit that delays the input signal in multiple stages and outputs it, a selection circuit that selects one of the delayed outputs based on the selection input, and controls the selection based on the phase difference. The input reversible counter is composed, and has a normal distribution comparing the occurrence rate of 0 or 1 and the number of occurrences of 0 or 1 in the above-mentioned repeated cycle, and the above-mentioned reversible counter can be changed according to the position of the above-mentioned normal distribution corresponding to the number of occurrences The counting control circuit shortens the phase adjustment time.

In this configuration, the switching width of the delayed output is increased in a region where the number of occurrences of 0 or 1 is small, and the phase is roughly adjusted, and the phase is finely adjusted by decreasing the switching width of the delayed output as it approaches the center of the normal distribution. This enables efficient phase adjustment.

The random number generator according to claim 39 is characterized in that it includes an initial control circuit for making the repetition period shorter than the repetition period during normal operation for a certain period after the power is turned on.

Thereby, the period from when the voltage is turned on to when an appropriate random number is generated can be shortened.

The random number generating device according to technical solution 40 is characterized in that a noise generating source and a noise/phase converter are added to the two input lines of the flip-flop.

The random number generating device according to claim 41 is characterized in that a noise generating source and a noise/phase converter are added to one input line of the flip-flop.

In the structure described in the technical solution 40 or the technical solution 41, the signal input to the flip-flop generates jitter, and the uncertain operation range of the flip-flop expands. As a result, more stable natural random numbers that have identity and do not have regularity, correlation, or periodicity can be generated at high speed and with high precision.

<Fourth Form of Invention>

In the present invention, the built-in function of improving the reliability as a 1-bit random number generator, multi-bit random number generator, and probability generator and allowing self-checking of the same type of occurrence of random number data is focused on.

That is, according to the 1-bit random number generating device described in technical solution 42 of the present invention, it is characterized in that there is a random number generator outputting 0 and 1 as random number data, and a first counter and a counter for counting a certain number of times are provided. The second counter that counts the number of appearances of the random number data output from the above-mentioned random number generator and generates the number of times data has a register that holds the number of times data of the second counter in each cycle of counting by the first counter, and has the The number of times data held by the register is used as an output circuit for checking data output.

According to the 1-bit random number generator described in technical solution 43 in the present invention, it is characterized in that it replaces the above-mentioned output circuit of technical solution 42, and has the function of comparing the preset upper limit comparison data and lower limit comparison data with the data held in the register and outputting A comparator that checks the signal.

According to the 1-bit random number generating device described in technical solution 44 in the present invention, it is characterized in that it has a random number generator that outputs 0 and 1 as random number data, and is equipped with the last random number output from the random number generator. The data holder of the number data is prepared to compare the current random number data output by the above random number generator with the last random number data held in the above data holder, and output a count increase signal when the two are the same, and at the same time When the two are different, the comparator that outputs the count clear signal is equipped with a counter that performs count clear when receiving the count clear signal from the comparator while counting up when receiving the count increase signal from the above-mentioned comparator. An output circuit that outputs the data held by the counter as check data.

According to the 1-bit random number generating device described in technical solution 45 in the present invention, it is characterized in that it has a random number generator that outputs 0 and 1 as random number data, and is equipped with a device that maintains the last random number output from the random number generator. The data holder of the number data is prepared to compare the current random number data output by the above random number generator with the last random number data held in the above data holder, and output a count increase signal when the two are the same, and at the same time When the two are not the same, the first comparator outputting the count clear signal is equipped with counting up when receiving the count increase signal from the first above-mentioned comparator, and performs count clearing when receiving the count clear signal from the first comparator. A counter with a register that holds the output data of the counter, and a data that compares the data of the register with the output data of the above-mentioned counter, writes a data rewrite signal when the latter is larger than the former, and outputs data in other cases A second comparator holding a signal, provided with control to write the output data of the above-mentioned counter into the above-mentioned register when receiving a data rewriting signal from the second comparator, while holding the above-mentioned register when receiving a data hold signal from the second comparator A control circuit for the data; an output circuit for outputting the data held by the above-mentioned registers as test data is provided.

According to the 1-bit random number generator described in technical solution 46 in the present invention, it is characterized in that it replaces the above-mentioned output circuit of technical solution 45, and has a third device that compares the preset comparison data with the data held in the register and outputs the verification signal. Comparators.

According to a kind of 1-bit random number generating device described in technical solution 47 in the present invention, it is characterized in that it has a random number generator that outputs 0 and 1 as random number data, and is equipped with a first counter that counts a certain number of times. There is a data holder for holding the last random number data output from the above random number generator, and a data holder for comparing the current random number data output by the above random number generator with the last random number held in the above data holder Data, when the two are the same, output the count increase signal, and at the same time, when the two are different, the comparator that outputs the count clear signal. A second counter for counting and clearing when the counter receives a count clear signal, a decoder for decoding the output data of the second counter and outputting it according to the length of each signal, and a device for separately counting the output data of the decoder according to the length of each signal A plurality of third counters are provided with a plurality of registers for respectively holding the output data of each of the third counters every certain number of times counted by the first counter, and are provided with signals and The output data of the above-mentioned comparator is a control circuit for outputting verification data from each of the above-mentioned registers.

The 1-bit random number generator according to claim 48 of the present invention is characterized in that a selection circuit for selecting and outputting the output data of the register is added.

According to the multi-bit random number generator described in technical solution 49 in the present invention, it is characterized in that a plurality of 1-bit random number generators described in technical solution 42 are connected in parallel, and additionally select and output from these 1-bit random numbers by every 1 bit. The selection circuit of the test data output by the digital generator.

According to the multi-bit random number generator described in technical solution 50 in the present invention, it is characterized in that a plurality of 1-bit random number generators described in technical solution 42 are connected in parallel, additionally select and output from these 1-bit random numbers by every 1 bit The selection circuit of the test signal output by the digital generator.

According to the probability generating device described in technical solution 51 in the present invention, it is characterized in that it has the 1-bit random number generating device described in technical solution 42, and is equipped with the random number data output from the 1-bit random number generating device from the serial A shift register for converting data into parallel data, a counter for counting the bit length of certain parallel data, a register for holding the parallel data of the above-mentioned shift register for each cycle counted by the counter, and a comparison pre-set The set probability upper limit data and probability lower limit data and the parallel data held in the above-mentioned registers are used to output the comparator of the probability signal.

According to the probability generating device described in technical solution 52 in the present invention, it is characterized in that it has the multi-bit random number generating device described in technical solution 49, and it is equipped with the probability upper limit data and probability lower limit data set in advance to compare with the above-mentioned multi-bit random number generating device. Random number data output by the random number generator and a comparator that outputs a probability signal.

Among these structures, a typical example of a data holder is a D-type flip-flop, and a typical example of a comparator is an exclusive-OR logic sum element (EXCLUSIVE-OR element). Furthermore, by adopting such a structure, the appearance identity of the random number data can be checked by itself, and the user does not need to perform statistical processing.

For convenience, symbols in parentheses indicate corresponding components in the figure, so the present invention is not limited to the description in the figure.

Brief description of the drawings

1 to 14 show a first form of the present invention. In these figures,

Fig. 1 is the circuit diagram representing the first embodiment of the random number generator of the present invention;

Fig. 2 is identical with Fig. 1, but represents the circuit diagram of the second embodiment of random number generator;

Fig. 3 is a circuit diagram representing a third embodiment of a random number generator;

Fig. 4 is a circuit diagram representing a fourth embodiment of a random number generator;

Fig. 5 is a circuit diagram representing a fifth embodiment of a random number generator;

Fig. 6 is a component circuit diagram showing the random number generator of the present invention to which a waveform shaping circuit is added;

FIG. 7 is a diagram showing a specific waveform shaping circuit;

Fig. 8 is a diagram showing input and output waveforms of the waveform shaping circuit of Fig. 7;

Fig. 9 is a component circuit diagram of the random number generating device of the present invention representing an additional initial control circuit;

Fig. 10 is a component circuit diagram showing the random number generator of the present invention using an R-S flip-flop;

Fig. 11 is a block diagram of the parallel type random number generator of the present invention;

Fig. 12 is a diagram showing the probability distribution of the probability generating device of the present invention;

FIG. 13 is a diagram showing a D-type flip-flop;

Fig. 14 is a diagram showing input and output waveforms of the D-type flip-flop of Fig. 13;

15 to 47 show a second embodiment of the present invention. In these figures,

Fig. 15 is a diagram showing a first embodiment of a second form of random number generator of the present invention;

Fig. 16 is a diagram showing a configuration different from that of the above-mentioned random number generator (Fig. 15);

FIG. 17 is a diagram showing the configuration of the jitter generating circuit of the present invention;

FIG. 18 is a diagram showing a configuration different from FIG. 17 of the jitter generating circuit of the present invention;

FIG. 19 is a diagram showing input and output waveforms during jitter generation;

Fig. 20 is a diagram showing the structure of the noise generating source of the present invention;

Fig. 21 is a diagram showing a structure different from that of Fig. 20 of the noise generating source of the present invention;

Fig. 22 is a diagram showing a structure different from that of Fig. 21 of the noise generating source of the present invention;

Fig. 23 is a diagram showing a structure different from that of Fig. 22 of the noise generating source of the present invention;

Fig. 24 is a diagram showing a structure different from that of Fig. 23 of the noise generating source of the present invention;

Fig. 25 is a diagram showing a structure different from that of Fig. 24 of the noise generating source of the present invention;

Fig. 26 is a diagram showing a structure different from that of Fig. 25 of the noise generating source of the present invention;

Fig. 27 is a diagram showing a structure different from that of Fig. 26 of the noise generating source of the present invention;

Fig. 28 is a diagram showing the structure of the amplifier circuit of the present invention;

Fig. 29 is a diagram showing a structure different from that of Fig. 28 of the amplifier circuit of the present invention;

FIG. 30 is a diagram showing a dither generating circuit of the present invention;

FIG. 31 is a diagram showing a configuration different from FIG. 30 of the jitter generating circuit of the present invention;

FIG. 32 is a diagram showing a configuration different from FIG. 31 of the jitter generation circuit of the present invention;

FIG. 33 is a diagram showing a configuration different from FIG. 32 of the jitter generation circuit of the present invention;

FIG. 34 is a diagram showing a configuration different from FIG. 33 of the jitter generation circuit of the present invention;

FIG. 35 is a diagram showing a configuration different from FIG. 34 of the jitter generation circuit of the present invention;

FIG. 36 is a diagram showing a configuration different from FIG. 35 of the jitter generation circuit of the present invention;

Fig. 37 is a component circuit of the random number generator of the present invention showing an additional latch circuit;

FIG. 38 is a circuit diagram of parts different from FIG. 37 of the random number generator of the present invention with a latch circuit added;

Fig. 39 represents the figure of the second embodiment of the random number generator of the second form of the present invention;

Fig. 40 is a diagram showing a phase-voltage conversion circuit of the present invention;

FIG. 41(a) and FIG. 41(b) are diagrams representing the phase-voltage conversion circuit of FIG. 40;

Fig. 42 is a diagram showing a configuration different from that of Fig. 40 of the phase-voltage conversion circuit of the present invention;

FIG. 43 is a structural diagram different from FIG. 39 showing the random number generator of the second embodiment of the present invention;

Fig. 44 is a diagram showing a third embodiment of the random number generator of the present invention;

Fig. 45 is a diagram showing the internal structure of the R-S flip-flop;

Fig. 46 is a diagram showing the internal structure of the R-S flip-flop of the third embodiment of the above-mentioned second form of the present invention;

FIG. 47 is a diagram showing the internal structure of an R-S flip-flop different from FIG. 46 according to the third embodiment of the present invention;

48 to 54 show a third embodiment of the present invention. In these figures,

Fig. 48 is a block diagram showing the random number generator of the first embodiment of the third embodiment of the present invention;

FIG. 49 is a diagram showing a configuration different from that of FIG. 48 of the random number generator of the first embodiment;

Fig. 50 is a structural diagram showing a random number generator of the second embodiment;

Fig. 51 is a diagram showing the operating ranges of rough adjustment and fine adjustment during phase adjustment;

Fig. 52 is a structural diagram showing a random number generator of the third embodiment;

Fig. 53 is a graph representing a normal distribution of random numbers having identity;

Figure 54 is a graph of the normal distribution of the segmentation weighted map 53;

55 to 67 show a fourth form of the present invention. In these figures,

Fig. 55 is a circuit diagram showing the first embodiment of the 1-bit random number generator of the present invention;

Fig. 56 is a circuit diagram showing the second embodiment of the 1-bit random number generator of the present invention;

Fig. 57 is a circuit diagram showing a third embodiment of the 1-bit random number generator of the present invention;

Fig. 58 is a circuit diagram showing a fourth embodiment of the 1-bit random number generator of the present invention;

Fig. 59 is a circuit diagram showing a fifth embodiment of the 1-bit random number generator of the present invention;

Fig. 60 is a circuit diagram representing the sixth embodiment of the 1-bit random number generator of the present invention;

Fig. 61 is a circuit diagram showing the seventh embodiment of the 1-bit random number generator of the present invention;

Fig. 62 is a circuit diagram showing the first embodiment of the multi-bit random number generator of the present invention;

Fig. 63 is a circuit diagram representing the second embodiment of the multi-bit random number generator of the present invention;

Fig. 64 is a circuit diagram showing the first embodiment of the probability generating device of the present invention;

Fig. 65 is a circuit diagram representing the second embodiment of the probability generating device of the present invention;

Fig. 66 is a circuit diagram showing the third embodiment of the probability generating device of the present invention;

Fig. 67 is a circuit diagram showing a fourth embodiment of the probability generating device of the present invention.

Best form for carrying out the invention

<Example of the first form>

Firstly, the implementation forms of the random number generator and the probability generator of the present invention will be described with reference to FIGS. 1 to 12 .

FIG. 1 is a circuit diagram showing a random number generator.

As shown in FIG. 1 , the random number generator 110 of the first embodiment is composed of a flip-flop 101 , a delay section 102 and a feedback circuit 103 .

Here, as the above-mentioned flip-flop 101, a flip-flop having a function of determining the output state (0 or 1) according to the phase difference of the input signal (CLOCK) input to the two input parts can be used. In this embodiment, the signal input is used A D-type flip-flop shown in FIG. 13 having a clock terminal CLK and a data terminal D.

The delay section 102 has a plurality of delay output terminals, and is composed of two delay circuits 117, 118 (delay lines) connected in series and a selection circuit 119 (selector) for selecting one of the delay outputs according to a selection input. The connection point (delay intermediate point) of the circuits 117, 118 is connected to the clock terminal CLK of the above-mentioned D-type flip-flop 101, while the output of the selection circuit 119 is connected to the data terminal D, and the rise of the two signals input in the D-type flip-flop 101 The phase difference along the time can be adjusted arbitrarily.

The feedback circuit 103 described above is constituted by a first counter 111, a second counter 112, a register 114, a constant setter 116, a comparator 115, and an up/down counter 113 (up/down counter).

The first counter 111 counts a predetermined repetition period (CLOCK number (2×m)) of the input signal CLOCK, and the second counter 112 counts the number of occurrences of 1 (or 0) output by the above-mentioned flip-flop in each repetition period. . The register 114 fetches and holds the count value of the second counter 112 every iteration cycle. In addition, the second counter 112 is cleared every time the count value is set in the register 114 . The constant setter 116 outputs comparison data for setting the occurrence rate of flip-flop output 1 (or 0). In this embodiment, it is preset to output a value (m) of 1/2 of the above-mentioned repetition period (number of clocks (2×m)). The comparator 115 compares the hold data (n) of the register 114 with the comparison data (m) from the constant setter 116, and generates a comparison output corresponding to the comparison result (n>m) or (n=m) or (n<m). The up-down counter 113 operates in an operation mode set based on the comparison output from the comparator 115 , and outputs the count data as a selection signal s of the lower-stage selection circuit 119 . Furthermore, as described above, the selection circuit 119 outputs a predetermined delay signal of the original CLOCK signal selected by the selection signal s.

That is, according to the above-mentioned structure, the comparison output of the output data (n) of the up-down counter corresponding to the register 114 and the output data (m) from the constant setter 116 performs an up/down operation in each repetition cycle (for example, when n>m Carry out counting up, carry out counting down when n＜m), automatic correction is input to the rising edge time of the CLOCK signal of the data terminal D of D-type flip-flop 101 so that the comparison output of comparator 115 converges on n=m (n= The counting action stops at m, and the phase difference of the CLOCK signal remains constant). Specifically, as shown in FIG. 14( c ), the phase difference Δt between the rising edge of the CLK signal and the rising edge of the D signal is controlled to be close to zero. As a result, the output of the D-type flip-flop 101 obtains 1-bit serial random number data OUT in which the occurrence rate of 0 and 1 is always maintained at 50%.

In this embodiment, the comparison data set in the constant setter 116 is set to 1/2 (namely, m) of the repetition period of the first counter 111, but by changing the value of m, the D-type flip-flop can output The occurrence rate of 0 or 1 is set outside 50%. For example, if m is set at 1/5 of the repetition period, then the occurrence rate of 0 or 1 is 20%.

However, in the first embodiment described above, the repetition cycle of the first counter 111 is always fixed (2×m), so the generated random number may show a tendency of several cycles. Next, the second to fourth embodiments shown in FIGS. 2 to 5 are methods for completely losing the periodicity of such random numbers.

First of all, the second embodiment shown in FIG. 2 replaces the above-mentioned constant setter 116 and newly installs a shift register 121, an adder 122, a comparator 123, etc., and the random number sequence output in each repetition cycle is used as the next iteration. Example of cycle setting data (2×m) and comparison data (m) of the comparator 115 . The 122-bit adder adds 1 to the range of the output random number (0 to m-1) and changes it to the range of (1 to m) using the random number sequence as the setting data and comparison data. The new comparator 123 generates a repetition period (2×m) from the count data (A) of the first counter 111 and the output data (m) of the adder 122 .

Next, the third embodiment shown in FIG. 3 is an embodiment in which an encryption circuit 124 is added to the above-mentioned second embodiment, and the output random number is encrypted and used as the above-mentioned setting data and comparison data. In addition, the so-called encryption is to transform any data of multiple data lines of mutual logical operation (for example, XOR logic sum, XOR logic sum and XOR logic sum between XOR logic sum, etc.) into data different from the original data, In FIG. 3 , the 16-bit output data of the shift register 121 is converted into 8-bit data by the encryption circuit 124 .

According to these second and third embodiments, the repetition cycle is gradually changed when generating random numbers, so that the periodicity of the generated random numbers is completely eliminated.

Next, the fourth embodiment shown in FIG. 4 is an auxiliary random number generator 104 that additionally corrects the random number generator of the above-mentioned second embodiment, and the random number sequence generated by the auxiliary random number generator 104 is used as an iterative In the embodiment of the setting data (2×m) of the period and the comparison data (m) of the comparator 115, the fifth embodiment shown in FIG. 5 is to add the random number generator of the third embodiment above as an auxiliary random number The generator 105 is an embodiment of encrypting the output of the auxiliary random number generator 105 and the output of the random number generator 110 itself.

According to these fourth and fifth embodiments, the random numbers of the auxiliary random number generators 104, 105 used as the above-mentioned setting data and comparison data are used in the internal circuit of the random number generator 110, and are not output to the outside, so the third party It is impossible to predict the nature, tendency, and periodicity of random numbers, so as to obtain completely natural random numbers.

FIG. 6 is a circuit diagram showing components of the random number generator with the waveform shaping circuit 125 added. In this way, when the waveform shaping circuit 125 is added to the input lines (D terminal and CLK terminal) of the D-type flip-flop 101 to forcibly blunt the edges of each input signal, it is easier to generate random numbers.

FIG. 7 shows the above-mentioned waveform shaping circuit 125 configured by inserting an integrating circuit composed of a resistor R and a capacitor C between input and output gates. As with the input and output waveforms shown in FIG. 8( a ), jitter Δj occurs in the output waveform at the intersection of the threshold voltage of the gate and the integral waveform. FIG. 8( b ) shows the relationship between the slope λ and the jitter Δj at the intersection of the threshold voltage and the integrated waveform. However, when the slope λ (that is, signal blunting) increases, the jitter Δj also increases. That is, the magnitude of the jitter Δj increases the uncertain operation range of the flip-flop, and as a result, it becomes easier to generate random numbers.

The waveform shaping circuit 125 is not only composed of the above-mentioned resistor R and capacitor C, but may be composed of, for example, a coil and a capacitor.

As shown in FIG. 9, in the above-mentioned second to fifth embodiments, the initial control circuit 126 composed of an initialization period setting circuit 126a and a gate circuit 126b is added to the random number output line used for comparison data. This comparison data is forcibly set to 0 during the specified repetition period. By initialization of such comparison data, the phase correction operation of the input signal can be effectively performed when the power is turned on, and the transition period from power-on to obtaining an appropriate random number is minimized.

In the embodiments described above, a D-type flip-flop was used as a flip-flop for random number generation, but the present invention is not limited thereto, and a flip-flop having the same function as this can be used. For example, FIG. 10 shows a structure using an R-S flip-flop as another example. According to FIG. 10 , the connection point of the delay circuits 117 and 118 is connected to the set input of the R-S flip-flop 101 , and the output of the selection circuit 119 is connected to the reset input of the R-S flip-flop 101 .

As shown in FIG. 11 , P pieces of the aforementioned serial type random number generators 110 are arranged in parallel, so that a parallel random number generator 120 with a P-bit structure can be formed. There is no relationship between each random number generator 110 in the parallel random number generator 120 .

Next, a probability generating device constructed using the random number generating device of the present invention will be described.

FIG. 12 shows the probability distribution of the probability generating means constituted by P (bits). The above-mentioned parallel type random number generator often corrects the occurrence rate of 1 or 0 in each random number generator to, for example, 50%. Each random number generating device 110 has identity but not regularity, correlation and periodicity, so the overall probability distribution is the same.

Here, the arbitrary range data (r1, r2) indicated by hatching in FIG. 12 is set for the same output data of the random number generator as a whole, so that the probability can be generated by the following equation.

P0＝(r2-r1+1)/ ^2P

Therefore, arbitrary probabilities can be obtained by appropriately setting the range data (r1 to r2).

As explained above, a natural random number generator and a probability generator having identity without regularity, correlation and periodicity can be realized by using digital circuits. If it is a digital circuit structure, it is easy to adapt to LSI, which is beneficial to production, and can provide a large amount of random numbers and probability data at high speed and low cost for applications in a wide range of fields such as scientific and technical calculations, game machines, and encryption processing.

Stable operation can be obtained because external factors such as external noise, temperature, and power fluctuation are small. Furthermore, it contributes to the safety of the environment, and there is no problem with discarded parts due to discarding after a single use.

<Example of the second form>

Embodiments of the random number generating device and the probability generating device of the second form of the present invention will be described below with reference to FIGS. 15 to 47 .

First, the first embodiment of the present invention is described. As shown in FIG. 15 , the random number generator 210 of the first embodiment is input (CLK signal) Two system delay circuits 202, 203 for providing a phase difference, jitter generation circuits 204, 204 added to the respective delay circuits 202, 203, and a phase control circuit 205 for adjusting the delay time of the delay circuit 203 are constituted.

The phase control circuit 205 measures a predetermined repetition period of the CLK signal, simultaneously performs feedback control for automatically adjusting the delay time of the delay circuit 203, and monitors the number of 1s or 0s output by the flip-flop (random number RND) within the predetermined period. , so that its occurrence rate is maintained at a certain value (for example, 50%). As a result, regarding the first embodiment of the present invention, as shown in FIG. 0 to act.

Also, the flip-flop 206 added at the final stage is a latch circuit for synchronizing the output timing of the random number data RND with the CLK signal.

Here, as the above-mentioned flip-flop 201, an edge trigger type flip-flop having an output state (0 or 1) determined according to a phase difference of an input signal can be used. In this embodiment, a D-type flip-flop having a CLK terminal and a D terminal is used. device while actively causing indeterminate behavior by inducing phase jitter in the input signal through the jitter generation circuit 204 described below.

As shown in FIG. 17, the jitter generating circuit 204 is composed of a noise generating source 207, an amplifier circuit 208 for amplifying the generated weak noise power, and a mixing circuit 209 for dithering an input signal by the amplified noise signal.

The mixer circuit 209 mounted on the jitter generation circuit 204 in FIG. 17 is configured by connecting a circuit of P-channel MOS transistors Q4 and Q3 connected in series and a circuit of N-channel MOS transistors Q2 and Q1 connected in series (cascaded). In each series transistor circuit, the gates of transistors Q4 and Q1 are connected to the output of the amplifying circuit 208, while the gates of transistors Q3 and Q2 are connected to the output of the integration circuit 212 composed of resistor R and capacitor C. In addition, the output of the above-mentioned delay circuit 202 or delay circuit 203 is connected to the input IN.

In the above circuit structure, as shown in Figure 19, the amplified noise signal is input to the gates of transistors Q4 and Q1, so that the threshold voltages of transistors Q3 and Q2 are changed relative to the integrated output waveform of the delayed CLK signal, causing the output OUT to jitter Δj. The magnitude of this jitter Δj extends to the uncertain operation range of the flip-flop 201 in the subsequent stage.

As the mixing circuit 209, in addition to the embodiment shown in Fig. 17, the configuration shown in Fig. 18 can be employed. The embodiment of FIG. 18 is composed of a series circuit of P-channel MOS transistor Q2 and N-channel transistor Q1. The output of each gate amplifier circuit 208 and the delayed CLK signal from input IN are respectively connected through capacitor C and resistor R.

Therefore, in the above circuit structure, the amplified noise signal and the phase-adjusted CLK signal passed through the delay circuit are synthesized by the capacitor C and input to the gates of the transistors Q2 and Q1, which is the same as the situation in Figure 17, and the output OUT with the same jitter Δj is obtained .

Next, the configuration of the above-mentioned noise generating source 207 will be described.

20 to 27 show specific circuit configurations of the noise generating source 207 .

FIG. 20 shows a structure in which a P-channel MOS transistor Q2 and an N-channel MOS transistor Q1 are connected in series, and the gate-output is short-circuited. FIG. 21 is the resistor R2 inserted between the gate and the output in FIG. 20 . Figure 22 is a structure of connecting a P-channel MOS transistor Q2 and an N-channel MOS transistor Q1 in series, inserting a resistor R2 between the gate and the output, and inserting a resistor R1 and a capacitor C1 between the gate and GND. . FIG. 23 is a structure in which the above-mentioned RC series circuit in FIG. 22 is inserted between the gate and the power supply. FIG. 24 is a structure in which the gate-output of the N-channel MOS transistor Q1 is short-circuited, and a resistor R1 is inserted between the output and the power supply. FIG. 25 is a structure in which a resistor R2 is inserted between the gate and the output in FIG. 24 . FIG. 26 is a structure in which the gate-output of the P-channel MOS transistor Q1 is short-circuited, and a resistor R1 is inserted between the output and GND. FIG. 27 is a structure in which a resistor R2 is inserted between the gate and the output in FIG. 26 .

In the above embodiments, an inexpensive noise source can be realized by utilizing the weak thermal noise generated by the active circuit elements (transistors, resistors, capacitors or combinations thereof). While obtaining stable operation with little influence from external noise and power supply fluctuations, it does not use a radiation source, so it is beneficial to environmental safety, and there is no problem with scrapped parts due to scrapping after one use.

The amplifying circuit 208 shown in FIG. 28 is composed of a series input circuit (high-pass filter) composed of a capacitor C1 and a resistor R1, and a series circuit of a P-channel MOS transistor Q2 and an N-channel MOS transistor Q1. The amplifying circuit shown in FIG. 29 208 is a configuration in which a capacitor C2 is connected in parallel to the return resistor R2 in FIG. 28 to form a low-pass filter. Although not shown, the input IN of these amplifier circuits 208 is connected to the output of the noise generator 207 , and the output OUT is connected to the mixer circuit 209 .

In the amplifier circuit 208 configured as described above, the characteristics of the high-pass filter and the low-pass filter described above are set corresponding to the respective configurations of the noise generating source 207 described above, thereby realizing an amplifier with appropriate characteristics.

Next, a specific circuit configuration of the jitter generation circuit 204 will be described with reference to FIGS. 30 to 36 . These are also constituted by combinations of the above-described noise generating source 207, amplifier circuit 208, and frequency mixing circuit 209, of which representative examples are shown below. Therefore, the present invention is not limited to these circuit examples.

FIG. 30 shows that the jitter generating circuit 204 having the configuration shown in FIG. 17 is composed of a combination of the noise generating source 207 shown in FIG. 20 and the amplifier circuit 208 shown in FIG. 28 . FIG. 31 is a circuit example in FIG. 30 in which amplifier circuits 208 are connected in series in two stages.

Fig. 32 is in Fig. 31, connects the switch circuit 214 that P channel MOS transistor Q14, Q24, Q34, Q46 constitute on each power supply side of noise generation source 207 and amplifier circuit 208 and mixer circuit 209. Connect on each ground side The switch circuit 215 composed of N-channel MOS transistors Q11, Q21, Q31, and Q41 turns on/off these switch circuits 214, 215 according to the operation permission signal ENABLE from the outside, and specifically, supplies power to each circuit only when a random number is required. A configuration for operating the dither generation circuit 204 .

In this way, the activation period of the circuit can be freely limited through the enabling function, so that useless power is not wasted, and low power consumption of the random number generator is realized.

33 to 36 show the jitter generating circuit 204 based on the configuration of FIG. 18 , and the combinations of the noise generating sources 207 and the amplifier circuits 208 are the same as those in FIGS. 30 to 32 described above, so descriptions are omitted here.

The embodiment of the jitter generation circuit 204 has been described above, but in the present invention, the jitter generation circuit 204 is divided into the structure of the random number generator 210 of FIG. In addition, the structure of FIG. 16 in which the jitter generating circuit 204 is added to only one input line of the flip-flop 201 (the D terminal side in this embodiment) may be used, thereby obtaining the same effect as the structure of FIG. 15 .

At this time, in order to match the input timing of the two input terminals, an RC integration circuit 213 (equivalent to the integration in FIG. time constant of circuit 212).

However, in the jitter generating circuit 204, the following inappropriateness occurs: the output of the mixing circuit 209 generates vibration due to the input of the integral waveform, and the input terminal of the flip-flop 201 inputs a number of times in one random number generation cycle. input signal.

Therefore, in this embodiment, as shown in FIGS. 37 and 38 , an R-S flip-flop 211 that operates (sets/resets) on both edges (rising edge/falling edge) of the CLK signal is provided on the rear stage of the jitter generating circuit 204, mixing The output OUT of the frequency circuit 209 is latched with the CLK signal. Accordingly, a signal without vibration can be input to the flip-flop 201, and stable random number generation can be performed. In addition, in the configuration of FIG. 38 , since the integrating circuit 213 also oscillates at the buffer output of the subsequent stage, an R-S flip-flop 211 is added.

In the embodiment described above, the D-type flip-flop 201 is used as the random number generating flip-flop 211, but the present invention is not limited to this, and a flip-flop having the same function as this may be used, for example, an R-S flip-flop may be used.

Next, a second embodiment of the second form of the present invention will be described.

As shown in FIG. 39, the random number generator 210 of the second embodiment consists of a D-type flip-flop 218 that outputs a 1-bit serial random number RND, and 2 system delay circuits 202, 203, and a phase-voltage conversion circuit 217. The shown phase control circuit 205 (refer to FIGS. 15 and 16 ) is configured.

Here, the above-mentioned phase-voltage conversion circuit 217 is a circuit that converts the phase difference of the delayed output signals of the delay circuits 202, 203 into a voltage. As shown in the internal circuit of FIG. 40, the detection input IN (CLK) and the input IN (D ), a series circuit of a P-channel MOS transistor Q2 and an N-channel MOS transistor Q1 that output ON/OFF through each gate circuit, and an RC integrating circuit connected to the output side thereof.

In the phase-voltage conversion circuit 217 having the above-mentioned structure, as shown in FIG. Turn on the N-channel MOS transistor Q1), charge the capacitor C through the resistor R, and increase the input voltage v(th) of the buffer to operate. As shown in FIG. 41(b), when the phase of IN(D) lags behind IN(CLK), the N-channel MOS transistor Q1 is turned on only at this phase difference (while the P-channel MOS transistor Q2 is turned off). The resistor R discharges the capacitor C to lower the input voltage v(th) of the buffer to operate.

Therefore, a voltage v(th) substantially equal to the threshold voltage of the buffer connected thereto is generated at the output of the phase-voltage conversion circuit 217, which is generated by the phase difference between two inputs, IN(CLK) and IN(D). The fluctuation of the output voltage is converted into a digital signal based on the relationship with the threshold voltage of the buffer, and input to the D terminal of the flip-flop 218, and 1-bit random number data RND synchronized with the CLK signal is outputted. Then, the random number data RND is monitored by the above-mentioned phase control circuit 205, and the phase difference between the two input signals (that is, the output of the phase-voltage conversion circuit 217) is automatically adjusted so that the occurrence rate of the flip-flop output 1 or 0 is constant (for example, 50%).

Although not shown, in FIG. 39 , by connecting a resistor in series behind the RC integrating circuit, the noise generated by the resistor can more effectively perform the threshold value operation of the lower-stage element caused by the fluctuation of v(th).

In addition, in FIG. 39 , a buffer is inserted between the phase-voltage conversion circuit 217 and the flip-flop 218 , but it may be directly connected to the D terminal of the flip-flop 218 without interposing a buffer. At this time, the output voltage v(th) of the phase-voltage conversion circuit 217 is almost automatically adjusted to the threshold voltage of the D terminal.

A comparator may be used instead of the above buffer, and a digital signal may be obtained by comparing the output voltage v(th) with a reference voltage.

As shown in FIG. 42, a P-channel MOS transistor Q4 and an N-channel MOS transistor Q5 are added to the series transistor circuit of the phase-voltage conversion circuit 217, and the operation of the circuit is stopped outside the necessary time by the operation permission signal ENABLE from the outside. low power consumption.

FIG. 43 shows a configuration in which the jitter generation circuit 204 is connected to the output side of the phase-voltage conversion circuit 217 . The jitter generating circuit 204 has the configurations shown in FIGS. 17 and 18 composed of a noise generating source 207, an amplifier circuit 208, and a frequency mixing circuit 209, and description thereof will be omitted here.

Connect the jitter generating circuit 204 to jitter the threshold voltage V(th), so that the probability of occurrence of 0 or 1 in the flip-flop output is positively increased, and thus it is easy to generate an identity without regularity, correlation, and cycle. A stable natural random number.

Next, a third embodiment of the second form of the present invention will be described.

As shown in Figure 44, the random number generator of the third embodiment consists of an R-S type flip-flop 216 that outputs a 1-bit serial random number RND and a delay circuit 202 that connects the S terminal and the R terminal of the R-S type flip-flop 216, 203 and an unshown phase control circuit 205 (refer to FIGS. 15 and 16).

Here, FIG. 45 shows the internal circuit of the above-mentioned R-S flip-flop composed of N-channel MOS transistors and P-channel MOS transistors. The NAND gate circuit on the S side is formed by transistors Q1-Q4, and the NAND gate circuit on the R-side is formed by transistors Q5-Q8. NAND gate circuit.

For example, in an edge-triggered flip-flop such as an R-S flip-flop, when the phase difference between the rising edges of the S-side input signal and the R-side input signal is close to 0, it is known that metastable phenomenon occurs. When this phenomenon occurs, the flip-flop It takes time before the output is determined, and the output state after a certain period of time remains 0 or 1 or the threshold voltage or is one of the oscillating states. This embodiment actively utilizes this metastable phenomenon to generate natural random numbers.

That is, in this embodiment, as shown in FIG. 46, in the circuit structure of FIG. 45, a P-channel MOS transistor Q10 is connected in series to the power supply Vcc side of the NAND gate circuit on the S side, and an N-channel MOS transistor Q10 is connected in series to the GND side. At the same time as the transistor Q9, the gates of these transistors Q9 and Q10 are connected with a noise generator 207 and an amplifier circuit 208, and the threshold voltage of the NAND gate circuit on the S side is changed by the amplified noise signal. In addition, the output of the delay circuit 202 is connected to the terminal S, and the output of the delay circuit 203 is connected to the terminal R. FIG. 47 shows a structure in which the above-mentioned circuit is added to the NAND gate circuits of both the S side and the R side, and the amplified noise signals are respectively input.

In the above structure, by changing the threshold voltage of the NAND gate circuit, the flip-flop output can be instantly changed from a metastable state to a stable state of 1 or 0. In addition, the random number data RND is monitored by the phase control circuit 205, and the phase difference between the two input signals is automatically adjusted so that the occurrence rate of flip-flop output 1 or 0 is constant (for example, 50%).

In the third embodiment described above, the R-S flip-flop 216 is used as a flip-flop (a flip-flop causing a metastable phenomenon) for random number generation, but the present invention is not limited thereto. Trigger, etc.) can achieve the same function.

Although not shown, the serial random number generators 210 of the above-mentioned first to third embodiments can be arranged in parallel, so as to form a parallel arrangement of P-bit structures without any mutual relationship among the random number generators 210 random number generator.

By using the above-mentioned serial type random number generator and parallel type random number generator to form a probability generator, it is possible to generate ideal probabilities that have identity but do not have regularity, correlation, and periodicity.

As mentioned above, each circuit of the present invention uses MOS transistors to form a digital structure, so it is easy to adapt to LSI, which is beneficial to production, and can provide a large number of random numbers at high speed and low cost for applications in a wide range of fields such as scientific and technical calculations, game machines, and encryption processing. and probability data.

As explained above, according to the present invention, the jitter generation circuit is added to the input line of the flip-flop that generates the random number, so the uncertain operation range of the flip-flop is expanded by the jitter of the input signal, and the random number is easily generated. A more stable natural random number generator that does not have regularity, correlation, and periodicity.

As another structure, the phase adjustment is converted into a voltage, and the voltage variation is digitized using the threshold voltage of the circuit element to generate a random number, so that a more stable natural randomness with identity rather than regularity, correlation, and periodicity can be realized. number generator.

As another configuration, by utilizing the metastable phenomenon of flip-flops to generate random numbers, a more stable natural random number generator having identity without regularity, correlation, and periodicity can be realized.

By using the random number generating device of this structure, an ideal probability generating device can be realized, and it can actively and effectively participate in high-tech industries with confidentiality such as scientific and technical calculations, game machines, and encryption processing.

<The third form of invention>

An example of a random number generating device according to the third embodiment of the present invention will be described below with reference to the drawings.

As shown in FIG. 48 , the random number generator 310 of the first embodiment basically includes a flip-flop 301 , a phase adjustment section 302 and a feedback circuit 303 .

Here, as the above-mentioned flip-flop 301, a flip-flop having a function of determining the state (0 or 1) of the output by the phase difference of the input signal (CLOCK) input to the two input parts can be used. In this embodiment, it is a signal input Instead, the D-type flip-flop shown in FIG. 13 of the above-described embodiment having a clock terminal CLK and a data terminal D is used.

The phase adjustment unit 302 is composed of two delay circuits 317, 318 (first delay 317, second delay 318) that are connected in series and generate a plurality of delay outputs that increase the delay amount in stages, and select one of the delay outputs according to the selection input. The selection circuit 319 (selector 319) and the up-down counter 313 (third counter 313) controlling the selection input are constituted. While the converter 320 is connected to the clock terminal CLk of the flip-flop 301, the output of the selector 319 is connected to the data terminal D through the second noise/phase converter 321, and the rising edge time of the two input signals input to the flip-flop 301 is The phase difference can be adjusted arbitrarily.

The above-mentioned two noise/phase converters 320 and 321 are to generate jitter in the input of the above-mentioned flip-flop, and generate noise from weak thermal noise generated by active circuit elements (such as transistors, resistors, capacitors, etc.) 322,323 noise and delay output synthesis circuit. Therefore, expanding the uncertain operation range of the flip-flop 301 makes it easy to generate completely natural random numbers that have identity but do not have regularity, correlation, and periodicity.

This noise/phase converter is not necessarily added to both the CLK terminal and the D terminal of the flip-flop 301. As shown in the random number generator 310 shown in FIG. D terminal) to get the same effect.

The above-mentioned feedback circuit 303 is composed of a first counter 311 , a second counter 312 , a register 314 , a comparator 315 and a constant setter 316 .

The first counter 311 measures a predetermined repetition period (number of CLOCKs (2×m)) from the input signal CLOCK, and the second counter 312 counts the number of occurrences of 1 (or 0) output by the above-mentioned flip-flop in each repetition period. . The register 314 fetches and holds the count value of the second counter 312 in each iteration cycle. In addition, the second counter 312 is cleared every time the count value is set in the register 314 . The constant setter 316 outputs comparison data for setting the occurrence rate of flip-flop output 1 (or 0). In this embodiment, it is preset to output a value (m) of 1/2 of the above-mentioned repetition period (number of clocks (2×m)). The comparator 315 compares the hold data (n) of the register 314 with the comparison data (m) from the constant setter 316, and generates a comparison output corresponding to the comparison result (n>m) or (n=m) or (n<m). The third counter 113 operates in an operation mode set based on the comparison output from the comparator 315 , and outputs the count data as a selection signal of the selection circuit 319 . Also, as described above, the selection circuit 319 outputs a predetermined delay signal of the CLOCK signal selected by the selection signal.

That is, according to the above-mentioned structure, the comparison output of the output data (n) of the corresponding register 314 of the third counter 313 and the output data (m) from the constant setter 316 carries out an up/down action (such as n> Count up (+1) when m, and count down (-1) when n<m), and automatically correct the rising edge time of the CLOCK signal input to the data terminal D of the flip-flop 301 to make the comparison output of the comparator 15 Converge at n=m (when n=m, the counting operation stops (±0), and the phase difference of the CLOCK signal remains constant). Specifically, as shown in FIG. 14( c ), the phase difference Δt between the rising edge of the CLK signal and the rising edge of the D signal is controlled to be close to zero. As a result, the output of the flip-flop 301 is obtained as 1-bit serial random number data OUT in which the occurrence rate of 0 and 1 is always maintained at 50%.

The above is the basic operation of the random number generator 310, but in this embodiment, the initial control circuit 324 is connected to the above-mentioned first counter 311, and the counting during the normal operation of the first counter 311 is forced to be set from the power supply to a certain number of clocks. The fixed value (2×m) is set to m=1. Therefore, when the power is turned on, the probability can be effectively converged to 1/2, and the phase adjustment period can be shortened.

Next, a second embodiment will be described based on FIG. 50 .

The basic structure of the random number generator 310 of this embodiment is the same as that of FIG. 48 , consisting of a flip-flop 301 , a phase adjustment unit 302 and a feedback circuit 303 , but the structure of the phase adjustment unit 302 is different from that of FIG. 48 .

That is, in this structure, the phase adjustment circuit composed of the third counter 313, the first selector 319, the first delay 317, and the second delay 318 is used as a fine-tuning component, and the third delay 331, the second selector The coarse adjustment unit constituted by the controller 332 and the coarse adjustment unit constituted by the fourth delay 333 and the third selector 334, the selection actions of the second selector 332 and the third selector 334 are specified by the output of the fourth counter 330. Therefore, the delay time per step of the first delay 317 and the second delay 318 for fine adjustment is set at about 1 compared with the delay time of the third delay 331 and the fourth delay 333 for rough adjustment. /20 or less. The fourth counter 330 is controlled by the comparison output of the comparator 315 , and its counting operation is the same as that of the third counter 313 .

Next, the rough adjustment operation and the fine adjustment operation of the phase performed by the random number generator 310 shown in FIG. 50 will be described with reference to FIG. 51 and Table 1. FIG. In addition, FIG. 51 shows the operation ranges of rough adjustment and fine adjustment during phase adjustment, and Table 1 shows the operation table of the third counter 313 and the fourth counter 330 at this time. Here, the fine adjustment range is (0˜r×(g−1)), and the rough adjustment range is (−s×(h)˜s×(h−1)).

In the initial state, the count value (SN) of the fourth counter 330 for rough adjustment and the count value (RN) of the third counter 313 for fine adjustment are both zero. The (m) of the first counter 311 is forcibly controlled within a certain number of clocks (the phase adjustment width tdw in FIG. 51 , that is, 2×(2×g+h) number of clocks) by the initial control circuit 324 when the power is turned on. Since m=1, the third counter 313 performs a counting operation (+1 or ±0 or −1) every two clocks based on the comparison output of the comparator 315 during a certain period. Meanwhile, the fourth counter 330 performs a counting operation (+1 or ±0 or −1) according to the comparison output of the comparator 315 and the state of the above-mentioned third counter 313 .

First, (1) when the final adjusted phase point is at a1 in Figure 51, when the power is turned on, the third counter 313 counts up from 0 to (g -1).

When the 3rd counter 313 counts up to RN=(g-1), the 4th counter 330 in every 2 clocks with the comparative output (n＜m) of comparator 315 and above-mentioned 3rd counter 313 The condition of RN=(g-1) counts up from 0 to (h-1), and becomes SN=(h-2). Here, the state of SN=(h-2) is the coarse adjustment pitch position corresponding to the phase set point a1 in Fig. 51, and the corresponding fine adjustment range is the range (A) in Fig. 51 (0～r× (g-1)). In this counting operation, the state of RN=(g−1) of the third counter 313 is forcibly maintained under the control of the initial control circuit 324 .

Then the third counter 313 is RN=(g-1), the fourth counter 330 is under the state of SN=(h-2), by the comparison output (n>m) of the comparator 315, the third counter 313 every 2 clocks Count up, gradually approach the phase set point a1, automatically adjust the phase so that the occurrence rate of 1 of the flip-flop output converges to 1/2, and finally stay at the phase before and after the above phase set point a1.

(2) When the final adjusted phase is a2, in the initial state, SN=(0), RN=(0). The third counter 313 counts down from (0) to (-2) in the next 2 clocks by the comparison output (n>m) of the comparator 315 when RN=(0), which is SN=(-2) . Here, the state of SN=(-2) is the coarse adjustment pitch position (-s×2) corresponding to the phase set point a2 in Figure 51, and the fine adjustment range is the range (B) in Figure 51 (0～r ×(g-1)). In this counting operation, the state of RN=(0) of the third counter 313 is forcibly held under the control of the initial control circuit 324 .

Then from the state that the third counter 313 is RN=(0), the fourth counter 330 is SN=(-2), the third counter 313 counts up every 2 clocks by the comparison output (n＜m) of the comparator 315 , gradually approaching the phase setpoint a2, and automatically adjusting so that the occurrence rate of 1 of the final flip-flop output converges to 1/2, staying before and after the phase of the above-mentioned phase setpoint a2.

Then (3) through the initial control action to adjust to the normal action after the phase set point is a1 or a2, as shown in Table 1, the third counter 313 is at a value other than RN=(0) or RN=(g-1). At this time, the counting operation (+1, ±0, -1) is performed based on the comparison output of the comparator 315 within a certain period (per clock of 2×m) set by the first counter 311 of m (for example, m=250).

When RN=(0), the third counter 313 carried out the counting action of (+1, ± 0, RN=(g-1)) according to the comparison output of the comparator 315, and the fourth counter 330 moved to RN at the third counter 313 =(g-1) is set to -1.

During RN=(g-1), the 3rd counter 313 carries out (+1,±0, RN=(g-1)) counting operation according to the comparative output of comparator 315, and the 4th counter 330 moves in the 3rd counter 313 Set to +1 when RN=(0).

As described above, the phase is first roughly adjusted to the specified phase (coarse adjustment), followed by fine adjustment at the final adjusted phase set point. Thus, high-precision phase adjustment is effectively performed, and high-speed phase adjustment can be performed by feedback control. By providing a rough adjustment part, a wide phase adjustment width can be obtained with a structure having a small delay pitch, and the number of circuit parts constituting the phase adjustment unit 302 can be reduced.

Table 1

Next, a third embodiment will be described with reference to FIGS. 52 to 54 .

Here, FIG. 53 is a graph obtained by plotting the number of occurrences of 1 or 0 when random numbers are output 1,000 times by an identical random number generator, and shows a normal distribution. FIG. 54 shows the case where the normal distribution is divided into 8 equal intervals based on the center, and the center is ±0. A total of 10 division positions are weighted from +5 to -5 from the left end in FIG. 54 .

The random number generator 310 shown in FIG. 52 is configured by changing the comparison form of the comparator 315 of the random number generator 310 in FIG. 48 in various ways, and connecting the control circuit 340 to the output. In this embodiment, the comparison data of the comparator 315 compared with the content (n) of the register 314 is multi-segmented position data (m+4×k)～(m-4×k) shown in FIG. 54 , immediately output which split position of the normal distribution the above count of occurrences corresponds to.

The control circuit 340 judges the weight (-5 to +5) corresponding to the divided position data from the comparison output ((n>m+4*k)~(n>(m-4*k)) of the comparator 315, and sets The count corresponding to this is respectively set in the third counter 313. The third counter 313 carries out the counting action of corresponding weighting, controls the switching width (switching pitch number) of delay output by the selector 319. For example, weighting is (-4 ), the third counter 313 repeatedly counts down 4 times with one action, and counts up three times with one action when the weight is (+3). When the weight is (0), stop the counting action.

In this way, in this structure, in the normal distribution area where the number of occurrences of 0 or 1 is small (for example, the number of occurrences in Figure 54 is around 450 or 550), the switching width of the delayed output is increased by weighting, and the phase is roughly adjusted. Close to the center of the normal distribution (the number of occurrences in Figure 54 is around 500), reduce the switching width of the delayed output, and perform fine adjustment of the phase. This enables efficient phase adjustment.

In the first to third embodiments described above, as the flip-flop used for random number generation, a D-type flip-flop is used, but the present invention is not limited thereto, and a flip-flop with the same function as this can be used, such as an R-S trigger device etc.

P serial random number generators 310 of the present invention can be arranged in parallel to form a parallel random number generator with a P-bit structure.

A high-speed, high-performance probability generator that does not have regularity, correlation, and periodicity can be realized by using the above-mentioned serial random number generator and parallel random number generator.

As described above, according to the present invention, in performing phase adjustment by feedback control, the phase adjustment unit is provided with rough adjustment means and fine adjustment means, so phase adjustment can be effectively performed and random number generation can be performed at a higher speed. By setting the rough adjustment part, a wide phase adjustment width can be obtained with a small delay pitch structure, thereby reducing circuit parts.

According to the present invention, comparing the normal distribution of the occurrence rate of the random number 0 or 1 with the actual number of occurrences, the position of the normal distribution corresponding to the corresponding number of occurrences can change the phase adjustment width, thereby effectively performing phase adjustment as above, and realizing Speed up random number generation.

<Fourth Embodiment of the Invention>

55 to 67 show a fourth embodiment of the present invention. A fourth embodiment of the present invention will be described below with reference to the drawings.

Fig. 55 is a circuit diagram showing a first embodiment of the 1-bit random number generator of the present invention.

As shown in Figure 55, the 1-bit random number generator 401 is a test data output type composed of a random number generator 402, a first counter 403, a second counter 404, a register 405 and an output circuit 406, and the random number generator 402 When a synchronization signal is input, 0 or 1 is output from the random number generator 402 as random number data. At this time, the input signal of the random number generator 402 is also input into the first counter 403 , and the first counter 403 counts a certain number of times and outputs it to the second counter 404 and the register 405 . On the other hand, the second counter 404 counts the number of occurrences of the random number data output from the random number generator 402 and generates the number data. And the register 405 holds the count data of the second counter 404 for each cycle counted by the first counter 403 , and the output circuit 406 outputs the count data held in the register 405 as verification data serially or in parallel.

Therefore, in the 1-bit random number generator 401, the user can check the appearance identity of the random number data by himself without performing troublesome and complicated statistical processing.

Fig. 56 is a circuit diagram showing a second embodiment of the 1-bit random number generator of the present invention.

As shown in Figure 56, the 1-bit random number generator 424 is a test signal output type composed of a random number generator 402, a first counter 403, a second counter 404, a register 405 and a comparator 407. In the random number generator 402 When a synchronization signal is input, 0 or 1 is output from the random number generator 402 as random number data. At this time, the input signal of the random number generator 402 is also input into the first counter 403, and the first counter 403 counts a certain number of times. On the other hand, the second counter 404 counts the number of occurrences of the random number data output from the random number generator 402 and generates the number data. And the register 405 holds the data of the number of times of the second counter 404 for each cycle counted by the first counter 403 . In addition, the comparator 407 compares the data held in the register 405 with the predetermined upper limit comparison data and lower limit comparison data, and when the data in the register 405 is between the upper limit comparison data and the lower limit comparison data, the output represents the occurrence identity of the random number data If the check signal is high, otherwise, a check signal indicating that the occurrence identity of the random number data is low is output.

Therefore, in the 1-bit random number generator 424, the user can check the appearance identity of the random number data by himself without performing troublesome and complicated statistical processing.

Fig. 57 is a circuit diagram showing a third embodiment of the 1-bit random number generator of the present invention.

The principle that this 1-bit random number generator 401 is based on is as follows: because if the output of the random number generator 402 is the same, the probability of outputting 0 or 1 is 1/2, so the probability that each number appears k times in a row is (1/2) ^k , for example, the probability that the same number appears 30 times in a row is 1/1073741824 (that is, almost zero), so if the same number appears 30 times in a row, it is determined that the random number generator 2 is abnormal.

That is, as shown in FIG. 57, the 1-bit random number generator 401 is a random number generator 402, a data holder 408 such as a D-type flip-flop, a comparator 409 such as an exclusive OR logic sum element, a counter 410, and an output circuit The verification data output type constituted by 406, when a synchronization signal is input to the random number generator 402, 0 or 1 is output from the random number generator 402 as random number data. At this time, the input signal and output signal of the random number generator 402 are also input to the data holder 408 , and the data holder 408 holds the last random number data output from the random number generator 402 and outputs it to the comparator 409 . The output signal of the random number generator 402 is also input in the comparator 409, and the comparator 409 compares the current random number data output from the random number generator 402 with the last random number data held by the data holder 408, and between the two When they are the same, they output a count-up signal to the counter 410 , and at the same time, they do not output a count-clear signal to the counter 410 at the same time. Then the input signal of the random number generator 402 is also input into the counter 410, and the counter 410 outputs the data to the output circuit 406, and the output circuit 406 sequentially outputs the data as verification data of the same signal length serially or in parallel.

Therefore, in the 1-bit random number generator 401, the statistical processing for checking the identity of random numbers can be easily performed by outputting the check data of the same signal length.

Fig. 58 is a circuit diagram showing a fourth embodiment of the 1-bit random number generator of the present invention.

As shown in FIG. 58, the 1-bit random number generator 401 is a random number generator 402, a data holder 408 such as a D-type flip-flop, a first comparator 411 such as an XOR logic sum element, a counter 410, and a register 412. , the second comparator 413, the control circuit 414 and the output circuit 415 constituted by the exclusive OR logic and elements, etc., when the synchronization signal is input in the random number generator 402, it is output from the random number generator 402 as random number data 0 or 1. At this time, the input signal and output signal of the random number generator 402 are also input into the data holder 408 , and the data holder 408 holds the last random number data output from the random number generator 402 and outputs it to the first comparator 411 . The output signal of the random number generator 402 is also input in the first comparator 411, and the first comparator 411 compares the current random number data output from the random number generator 402 with the last random number data held by the data holder 408 , output a count up signal to the counter 410 when the two are the same, and simultaneously output a count clear signal to the counter 410 when the two are not at the same time. Then the input signal of the random number generator 402 is also input in the counter 410, and the counter 410 outputs the data to the second comparator 413, and the second comparator 413 compares the data of the register 412 and the output data of the counter 410, and the latter compares the former When it is large, a data rewrite signal is output to the control circuit 414 , and a data hold signal is output to the control circuit 414 at other times. The control circuit 414 is controlled to write the output data of the counter 410 into the register 412 when receiving the data rewriting signal, and hold the data of the register 412 when receiving the data hold signal, and the output circuit 415 uses the data held in the register 412 as the last Long test data of the same signal length are sequentially output in series or in parallel.

Therefore, in the 1-bit random number generator 401, statistical processing for checking the identity of random numbers can be easily performed by the longest output check data of the same signal length.

Fig. 59 is a circuit diagram showing a fifth embodiment of the 1-bit random number generator of the present invention.

As shown in FIG. 59 , the 1-bit random number generator 524 is a random number generator 402, a data holder 408 such as a D-type flip-flop, a first comparator 411, a counter 410, and a register 412 such as an XOR logic sum element, etc. , the second comparator 413 of XOR logic and elements, the control circuit 414 and the third comparator 416 of XOR logic and elements, etc. constitute the inspection signal output type, when the synchronization signal is input in the random number generator 402, as a random The number data is output from the random number generator 402 as 0 or 1. At this time, the input signal and output signal of the random number generator 402 are also input into the data holder 408 , and the data holder 408 holds the last random number data output from the random number generator 402 and outputs it to the first comparator 411 . The output signal of the random number generator 402 is also input in the first comparator 411, and the first comparator 411 compares the current random number data output from the random number generator 402 with the last random number data held by the data holder 408 , output a count up signal to the counter 410 when the two are the same, and simultaneously output a count clear signal to the counter 410 when the two are not at the same time. Then the input signal of the random number generator 402 is also input in the counter 410, and the counter 410 outputs the data to the second comparator 413, and the second comparator 413 compares the data of the register 412 and the output data of the counter 410, and the latter compares the former When it is large, a data rewrite signal is output to the control circuit 414 , and a data hold signal is output to the control circuit 414 at other times. The control circuit 414 is controlled to write the output data of the counter 410 into the register 412 while receiving the data rewriting signal, and hold the data of the register 412 when receiving the data hold signal, and the third comparator 416 compares the data held in the register 412 Compare the data with the predetermined one and output the longest inspection signal with the same signal length in sequence.

Therefore, in the 1-bit random number generator 424, the user can check the appearance identity of the random number data by himself without performing troublesome and complicated statistical processing.

Fig. 60 is a circuit diagram showing a sixth embodiment of the 1-bit random number generator of the present invention.

As shown in FIG. 60, the 1-bit random number generator 401 is a random number generator 402, a data holder 408 such as a D-type flip-flop, a comparator 409 such as an XOR logic sum element, a first counter 417, a second Counter 418, decoder 419, a plurality of (n) the 3rd counter 420, a plurality of (n) register 421 and the check data output type that control circuit 422 forms, when input synchronous signal in random number generator 402, as random The number data is output from the random number generator 402 as 0 or 1. At this moment, the occurrence rate of each identical signal length (1～n) counted by the first counter 417 is counted, every fixed number of times counted by the first counter 417 is written into the register 421, and each identical signal length is output sequentially. Distribution.

That is, the input signal and output signal of the random number generator 402 are also input to the data holder 408 , and the data holder 408 holds the last random number data output from the random number generator 402 and outputs it to the comparator 409 . The output signal of the random number generator 402 is also input in the comparator 409, and the comparator 409 compares the current random number data output from the random number generator 402 with the last random number data held by the data holder 408, and between the two When they are the same, they output a count-up signal to the control circuit 422 , and at the same time, they output a count-clear signal to the control circuit 422 at the same time. On the other hand, the input signal of the random number generator 402 is also input into the first counter 417 and the control circuit 422 , and the first counter 417 counts a certain number of times and outputs it to the control circuit 422 . In addition, the input signal of the random number generator 402 is also input in the second counter 418, and the second counter 418 counts up when receiving the count-up signal from the comparator 409 and outputs it to the decoder 419. signal, the count is cleared and output to the decoder 419 . The receiving decoder 419 decodes the output data of the second counter 418 and outputs it to each of the third counters 420 for each signal length, and each counter 420 counts the output data and outputs it to each register 421 . Then, under the control of the control circuit 422 , each register 421 sequentially outputs verification data of the same signal length in series or in parallel according to the output data of the comparator 409 and the signal counted by the first counter 417 every certain number of times.

Therefore, in the 1-bit random number generator 424, statistical processing for checking the identity of random numbers can be easily performed by each output count (check data).

Fig. 61 is a circuit diagram showing a seventh embodiment of the 1-bit random number generator of the present invention.

As shown in FIG. 61, the 1-bit random number generator 1 is a random number generator 402, a data holder 408 such as a D-type flip-flop, a comparator 409 such as an XOR logic sum element, a first counter 417, a second Counter 418, decoder 419, multiple (n) third counters 420, multiple (n) registers 421, control circuit 422 and selection circuit 423 constitute the inspection data output type, input synchronous signal in random number generator 402 , 0 or 1 is output from the random number generator 402 as random number data. At this time, count the occurrence rates of each identical signal length (1-n) counted by the first counter 417 for a certain number of times, write the register 421 for every certain number of times counted by the first counter 417, and sequentially send to the selection from the outside. The selection circuit 423 for data selection outputs distributions of the same signal lengths.

That is, the input signal and output signal of the random number generator 402 are also input to the data holder 408 , and the data holder 408 holds the last random number data output from the random number generator 402 and outputs it to the comparator 409 . The output signal of the random number generator 402 is also input in the comparator 409, and the comparator 409 compares the current random number data output from the random number generator 402 with the last random number data held by the data holder 408, and between the two When they are the same, they output a count-up signal to the control circuit 422 , and at the same time, they output a count-clear signal to the control circuit 422 at the same time. On the other hand, the input signal of the random number generator 402 is also input into the first counter 417 and the control circuit 422 , and the first counter 417 counts a certain number of times and outputs it to the control circuit 422 . In addition, the input signal of the random number generator 402 is also input in the second counter 418, and the second counter 418 counts up when receiving the count-up signal from the comparator 409 and outputs it to the decoder 419. signal, the count is cleared and output to the decoder 419 . The receiving decoder 419 decodes the output data of the second counter 418 and outputs it to each of the third counters 420 for each signal length, and each counter 420 counts the output data and outputs it to each register 421 . Then, under the control of the control circuit 422 , each register 421 sequentially outputs check data of the same signal length to the selection circuit 423 in series or in parallel according to the output data of the comparator 409 and the signal counted by the first counter 417 every certain number of times. When selection data is input to the selection circuit 423 from the outside, the selection circuit 423 appropriately selects and outputs the output data of the register 421 based on the selection data.

Therefore, in the 1-bit random number generator 401, statistical processing for checking the identity of random numbers can be easily performed by outputting distribution data of the same signal length.

Fig. 62 shows a circuit diagram of the first embodiment of the multi-bit random number generator of the present invention.

As shown in FIG. 62, this multi-bit random number generator 425 is a structure in which a plurality (n) of the 1-bit random number generators 401 of the test data output type are connected in parallel and a selection circuit 426 is added to it. In the selection circuit 426 When selection data is input from the outside, the selection circuit 426 selects and outputs the check data output from the 1-bit random number generator 401 bit by bit based on the selection data.

Therefore, in this multi-bit random number generator 425, statistical processing for checking the identity of random numbers can be easily performed by the output identity check data.

Fig. 63 shows a circuit diagram of the second embodiment of the multi-bit random number generator of the present invention.

As shown in FIG. 63, this multi-bit random number generator 425 is a structure in which a plurality (n) of the 1-bit random number generators 424 of the test signal output type are connected side by side and a selection circuit 427 is added to it. In the selection circuit 427 When selection data is input from the outside, the selection circuit 427 selects and outputs the check signal output from the 1-bit random number generator 424 bit by bit based on the selection data.

Therefore, in the multi-bit random number generator 425, the user can check the appearance identity of the random number data by himself without performing troublesome and complicated statistical processing.

Fig. 64 shows a circuit diagram of the first embodiment of the probability generating device of the present invention.

As shown in FIG. 64, the probability generating device 430 is composed of the above-mentioned 1-bit random number generating device 401 of the test data output type, a shift register 431, a counter 432, a register 433, and a comparator 434. From the 1-bit random number generating device 401 The output random number data is input to the shift register 431 , and the shift register 431 converts the random number data from serial data to parallel data and outputs it to the register 433 . On the other hand, the input signal of the 1-bit random number generator 401 is also input to the counter 432 , and the counter 432 counts the bit length of certain parallel data and outputs it to the register 433 . Thus, the register 433 holds the parallel data of the shift register 431 every cycle counted by the counter 432 . Afterwards, the comparator 434 compares the data held in the register 433 with predetermined probability upper limit data and probability lower limit data, and outputs "hit" when the data in the register 433 is between the probability upper limit data and the probability lower limit data, in other cases A probability signal of "deviation" is output.

Therefore, in the probability generating device 430, the user can check the appearance identity of the random number data without performing troublesome and complicated statistical processing, thereby easily evaluating the reliability of the probability.

Fig. 65 shows a circuit diagram of the second embodiment of the probability generating device of the present invention.

As shown in FIG. 65, the probability generator 430 is composed of the above-mentioned 1-bit random number generator 424 of the check signal output type, a shift register 431, a counter 432, a register 433, and a comparator 434. From the 1-bit random number generator 424 The output random number data is input to the shift register 431 , and the shift register 431 converts the random number data from serial data to parallel data and outputs it to the register 433 . On the other hand, the input signal of the 1-bit random number generator 424 is also input to the counter 432 , and the counter 432 counts the bit length of certain parallel data and outputs it to the register 433 . Thus, the register 433 holds the parallel data of the shift register 431 every cycle counted by the counter 432 . Afterwards, the comparator 434 compares the data held in the register 433 with predetermined probability upper limit data and probability lower limit data, and outputs "hit" when the data in the register 433 is between the probability upper limit data and the probability lower limit data, in other cases A probability signal of "deviation" is output.

Therefore, in the probability generating device 430, the user can check the appearance identity of the random number data without performing troublesome and complicated statistical processing, thereby easily evaluating the reliability of the probability.

Fig. 66 shows a circuit diagram of the third embodiment of the probability generating device of the present invention. Fig. 67 shows a circuit diagram of the fourth embodiment of the probability generating device of the present invention.

As shown in FIG. 66 and FIG. 67, these probability generators 430 are composed of the above-mentioned multi-bit random number generator 425 and a comparator 435, and the random number data (parallel data) output from the multi-bit random number generator 425 is input to the comparator In 435, the comparator 435 compares these random number data with the predetermined upper limit data of probability and the lower limit data of probability, and outputs "hit" when the random number data is between the upper limit data of probability and the lower limit data of probability, and outputs "deviation" in other cases. "Probability signal.

Therefore, in the probability generating device 430, the user can check the appearance identity of the random number data without performing troublesome and complicated statistical processing, thereby easily evaluating the reliability of the probability.

As described above, according to the above-described embodiments of the present invention, the identity of appearance of random number data can be checked by itself, and the user does not need to perform statistical processing, thereby providing a method for easily checking the identity of appearance of random number data and improving reliability. 1 bit random number generator.

The appearance identity of the random number data can be checked by itself, and the user does not need to perform statistical processing, thereby providing a multi-bit random number generator that can easily check the appearance identity of the random number data and can improve reliability.

In addition, according to the invention of technical solution 51 in the present invention, the appearance identity of the random number data can be checked by itself, and the user does not need to perform statistical processing, thereby providing a method for easily checking the appearance identity of the random number data and improving reliability. Probability Generator.

Claims (13)

1. random number generator is characterized in that comprising:

Trigger, correspondence are input to the phase differential of the signal of 2 input parts and determine output state 0 or 1;

Delay portion possesses by above-mentioned input signal being postponed several grades of delay circuits of exporting and corresponding selection and imports the selection circuit of one of selection delay output, and makes 2 input signals produce phase differential; With

Feedback circuit wherein, has:

First counter in the cycle repeatedly of the regulation of the above-mentioned input signal of instrumentation,

Instrumentation each repeatedly second counter of 0 or 1 of above-mentioned trigger output appearance number in the cycle,

By cycle repeatedly keep the instrumentation output of this second counter register,

Generation be used to set above-mentioned trigger output 0 or 1 occurrence rate comparing data the constant setting apparatus,

The comparer of the output data of more above-mentioned register and the size of above-mentioned comparing data,

Produce the up-down counter of the selection signal of above-mentioned selection circuit, also according to the relatively output of this comparer

By above-mentioned input signal control above-mentioned phase differential so that 0 or 1 occurrence rate of trigger output in accordance with regulations repeatedly the cycle certain.

2. random number generator according to claim 1, it is characterized in that as the setting data in the cycle of setting in above-mentioned first counter repeatedly and the comparing data of above-mentioned comparer, use the random number of above-mentioned trigger output or encrypt the random number that this random number constitutes.

3. random number generator according to claim 1, it is characterized in that having auxiliary random number generator with the described random number generator same structure of claim 1, as the setting data in the cycle of setting in above-mentioned first counter repeatedly and the comparing data of above-mentioned comparer, the random number of using above-mentioned auxiliary random number generator to produce.

4. random number generator according to claim 1, it is characterized in that having auxiliary random number generator with the described random number generator same structure of claim 1, as the setting data in the cycle of setting in above-mentioned first counter repeatedly and the comparing data of above-mentioned comparer, use random number that above-mentioned auxiliary random number generator produces and the random number of the random number that above-mentioned random number generator produces being encrypted formation.

5. random number generator according to claim 1 is characterized in that constituting to the additional waveform shaping circuit of the input signal cable of above-mentioned trigger.

6. random number generator according to claim 1 is characterized in that having the initial control circuit that the comparing data of above-mentioned comparer is set at specified time limit 0 when energized.

7. random number generator according to claim 1 is characterized in that as above-mentioned trigger, uses D flip-flop or R-S trigger.

8. random number generator according to claim 1 is characterized in that disposing side by side the described random number generator of a plurality of claims 1.

9. a probability generator is characterized in that having the described random number generator of claim 1.

10. random number generator as claimed in claim 1 is characterized in that,

The additional shake generative circuit that constitutes by noise-producing source, the amplifying circuit that amplifies this noise, the mixting circuit that input signal produced shake by this amplifications noise signal on above-mentioned trigger incoming line.

11. random number generator according to claim 10 is characterized in that additional above-mentioned shake generative circuit on two incoming lines of above-mentioned trigger.

12. random number generator according to claim 10 is characterized in that additional above-mentioned shake generative circuit on some incoming lines of above-mentioned trigger, the integrating circuit that the additional delay time adjustment is used on another incoming line.

13. random number generator according to claim 10 is characterized in that having the latching sections by the output of the above-mentioned shake generative circuit of the breech lock of cycle repeatedly of above-mentioned input signal.

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