CN100416492C - Random number generator and probability generator - Google Patents

Abstract

A random number generator characterized by comprising a flip-flop for determining an output state (0 or 1) according to a phase difference between two signals input to an input unit, a delay unit for producing a phase difference between the two input signals, and a feedback circuit for controlling the phase difference so that an occurrence frequency of 0 or 1, an output from the flip-flop by the input signals, is constant within a specified repetition cycle.

Description

Random number generator and probability generator

Technical field

The present invention relates to a kind of probability generator that is suitable for being used for the random number generator of scientific and technical calculating, game machine or encryption etc. and uses this random number generator to constitute.And, the present invention relates to automatically adjust 2 phase of input signals differences being input to trigger so that 0 or 1 the certain random number generator of occurrence rate of trigger output relates in particular to effective phase place adjustment component.

Background technology

The use of random number is indispensable in the science and technology calculating of height and game machine or the encryption etc., in recent years, to having homogeneity (because random number, on occurrence rate, not producing the situation of difference) and not having the generation device of the natural random number of high-performance (intrinsic random number) of correlativity, periodicity etc. of regularity that random number occurs, front and back and the needs of probability generator increase day by day.

And,, be well known that utilization for example utilizes the situation of the pulse at random that the thermonoise of faint radioactive ray, resistance and diode or the vibration of quartz (controlled) oscillator etc. obtain as above-mentioned natural random number/probability generator.

But, in the random number/probability generation circuit of utilization according to the random pulses of above-mentioned spontaneous phenomenon, the simulation key element that comprises obstruction device, the wave shaping of generation source, the signal of the above-mentioned random pulses of a lot of pictures, suitableization circuit of homogeneity etc., therefore circuit scale becomes big, complicate, thereby being difficult to they are loaded as the logic LSI of subject under discussion, is disadvantageous for using in the microminiatures such as IC-card that more need expect from now on, the slim high-tech equipment.Because the LSIization difficulty, productivity worsens, cost up.

Especially, utilize the situation of thermonoise to be subjected to the influence of external noise and power supply change or temperature etc. easily, shortcoming is the action stability shortcoming, also worry that owing to it is very faint radioactive ray exert an influence to environment even utilize the situation of radioactive ray, therefore spendable quantity of radiation is restricted, thus, be difficult to deal with the purposes that the short time produces a large amount of random numbers.

Summary of the invention

The purpose of this invention is to provide a kind of high-performance and safe random number generator and probability generator, by realize the generation of nature random number by the structure of digital circuit, problems such as homogeneity as the problem of above-mentioned prior art, regularity, correlativity, periodicity have been solved.

Another object of the present invention provides a kind of high performance random number generator and probability generator, solved the problem of above-mentioned prior art, small-sized, the slimming that realizes that LSI loads and be beneficial to production, at aspect of performance, do not produce problems such as homogeneity, regularity, correlativity, periodicity simultaneously yet.

A further object of the present invention provides at a high speed and high performance random number generator.

Another purpose of the present invention provides a kind of 1 bit random number generator and many bits random number generator and probability generator, can check the appearance homogeneity of random number data simply and improve reliability.

Here, as the trigger of determining the state (0 or 1) of output according to the phase differential of the signal that is input to 2 input parts, known have a D flip-flop.

This D flip-flop as shown in figure 13, be clock terminal CLK and the data terminal D that has as input part, input and output waveform shown in Figure 14 (a), 14 (b) is such, and the state (0 or 1) of data terminal D is determined the so-called edge-triggered D-flip flop of the state of output Q and Q (the counter-rotating output of Q:Q) during according to CLK input rising edge.

Here, poor (phase differential) Δ t of rising edge time that makes rising edge time of CLK signal and D signal from the state of Figure 14 (a) or Figure 14 (b) is near 0 o'clock, shown in Figure 14 (c), exist trigger output Qn ,/the uncertain phase range of Qn.

The present invention actively utilizes the uncertain action of this trigger to generate the nature random number.

＜first form of the present invention 〉

That is, technical scheme 1 described random number generator is characterized in that having the trigger that phase differential that correspondence is input to the signal of 2 input parts is determined output state (0 or 1); By above-mentioned input signal being postponed the selection circuit that several grades of delay circuits of exporting and corresponding selection input select to postpone one of output, make the delay portion that produces phase differential in these 2 input signals; And feedback circuit, have: first counter in the cycle repeatedly of the regulation of the above-mentioned input signal of instrumentation; Each second counter of 0 or 1 of above-mentioned trigger output appearance number in the cycle repeatedly of instrumentation; By the cycle keeps the register of the instrumentation output of this second counter repeatedly; Generation is used to set the constant setting apparatus of comparing data of 0 or 1 occurrence rate of above-mentioned trigger output; The comparer of the output data of more above-mentioned register and the size of above-mentioned comparing data; Produce the up-down counter of the selection signal of above-mentioned selection circuit according to the relatively output of this comparer, and control above-mentioned phase differential so that 0 or 1 occurrence rate of trigger output certain feedback circuit of cycle repeatedly in accordance with regulations by above-mentioned input signal.

In the described structure of technique scheme, about the generation of random number, all realize having same type with digital circuit and have not regulation, the generating means of correlativity, periodic natural random number.The resolution of the cycle repeatedly by suitable setting input signal and the setting phase differential of delay portion can generate a large amount of random numbers at a high speed.And, be digital circuit structure, tackle LSIization easily.

According to technical scheme 4 described random number generators, it is characterized in that as the setting data in the cycle of setting in above-mentioned first counter repeatedly and the comparing data of above-mentioned comparer, use the random number of above-mentioned trigger output or encrypt the random number that this random number constitutes.

In this structure, the periodicity relevant with the generation of random number completely loses.

According to technical scheme 5 described random number generators, it is characterized in that having auxiliary random number generator with technical scheme 3 described random number generator same structures, as the setting data in the cycle of setting in above-mentioned first counter repeatedly and the comparing data of above-mentioned comparer, the random number of using above-mentioned auxiliary random number generator to produce.

According to technical scheme 6 described random number generators, it is characterized in that having auxiliary random number generator with technical scheme 3 described random number generator same structures, as the setting data in the cycle of setting in above-mentioned first counter repeatedly and the comparing data of above-mentioned comparer, use random number that above-mentioned auxiliary random number generator produces and the random number of the random number that above-mentioned random number generator produces being encrypted formation.

In technical scheme 5 and the technical scheme 6 described structures, random number data from auxiliary random number generator does not output to outside (beyond the random number generator), therefore the character of the random number that generates, tendency, periodicity etc. are unpredictable, are entirely the nature random number thus.

According to technical scheme 7 described random number generators, it is characterized in that constituting to the additional waveform shaping circuit of the input signal cable of above-mentioned trigger.

By the input signal that the passivation wave shaping generates, enlarge the uncertain actuating range of trigger, generate random number easily.

According to technical scheme 8 described random number generators, it is characterized in that having the initial control circuit that when energized, the comparing data of above-mentioned comparer is set at specified time limit 0.

Thus, power connection begins to shorten during the suitable random number of generation.

According to technical scheme 9 described random number generators, it is characterized in that as above-mentioned trigger, use D flip-flop or R-S trigger.

According to technical scheme 10 described random number generators, it is characterized in that disposing side by side a plurality of technical scheme 1 described random number generators.Constitute between each random number generator of random number generator of this parallel type and have no relation.Each random number generator does not have regularity, correlativity, periodically yet.

According to technical scheme 11 described probability generators, it is characterized in that the scheme of possessing skills 1 described random number generator.

As mentioned above, this random number generator has same type and does not have regularity, correlativity, periodically, and therefore whole probability distribution is identical.

＜the second form of implementation 〉

As mentioned above, as the trigger of determining the state (0 or 1) of output according to the phase differential of the signal that is input to 2 input parts, known have a D flip-flop.This D flip-flop as shown in figure 13, be clock terminal CLK and the data terminal D that has as input part, the state (0 or 1) of data terminal D is determined the so-called edge-triggered D-flip flop of the state of output Q and Q (the counter-rotating output of Q:Q) during according to CLK input rising edge.

Here, poor (phase differential) Δ t of rising edge time that makes rising edge time of CLK signal and D signal from the state of Figure 14 (a) or Figure 14 (b) is near 0 o'clock, shown in Figure 14 (c), exist trigger output Qn ,/the uncertain phase range of Qn.And the uncertain actuating range of this trigger enlarges easier generation random number when the shake of input signal increases.

The present invention increases the shake of above-mentioned input signal, actively utilizes the uncertain action of the trigger of this moment to generate the nature random number.

Promptly, according to technical scheme 12 described random number generators, import the 2 system delay circuit that phase differential is provided between (CLK signal) by the trigger of the serial random number R ND that exports 1 bit with at this trigger, with the regulation of instrumentation CLK signal cycle repeatedly, and monitor 1 or 0 number of trigger output (random number data RND) in this specified period, and for making its occurrence rate (for example be maintained certain value, 50%) phase-control circuit of FEEDBACK CONTROL of adjusting the time delay of above-mentioned delay circuit and automatically constitutes, and it is characterized in that on above-mentioned trigger incoming line additional by noise-producing source, amplify the amplifying circuit of this noise, the shake generative circuit that the mixting circuit that makes input signal produce shake by this amplification noise signal constitutes.

According to technical scheme 13 described random number generators, it is characterized in that additional above-mentioned shake generative circuit on two incoming lines of above-mentioned trigger.

According to technical scheme 14 described random number generators, it is characterized in that additional above-mentioned shake generative circuit on some incoming lines of above-mentioned trigger, the integrating circuit that the additional delay time adjustment is used on another incoming line.

Here technical scheme 12 is in technical scheme 14 described structures, and the input signal that is input to trigger produces shake, enlarges the uncertain actuating range of trigger.Thus, generate easily have homogeneity and have not regulation, correlativity and periodic complete natural random number.

According to technical scheme 15 described random number generators, it is characterized in that having latching sections by the output of the above-mentioned shake generative circuit of the breech lock of cycle repeatedly of above-mentioned input signal.

In this structure, 1 time random number obtains 1 time input signal in generating, and stablizes the generation action of random number.

Import the 2 system delay circuit that phase differential is provided between (CLK signal) by the trigger of the serial random number R ND of output 1 bit with at this trigger according to technical scheme 16 described random number generators, on above-mentioned trigger incoming line, by noise-producing source, amplify the amplifying circuit of this noise, the shake generative circuit that the mixting circuit that makes input signal produce shake by this amplification noise signal constitutes, with the regulation of instrumentation CLK signal cycle repeatedly, and monitor 1 or 0 number of trigger output (random number data RND) in this specified period, and for making its occurrence rate (for example be maintained certain value, 50%) phase-control circuit of FEEDBACK CONTROL of adjusting the time delay of above-mentioned delay circuit and automatically constitutes, it is characterized in that on the Data In-Line of above-mentioned trigger the additional grid circuit that above-mentioned 2 phase of input signals differences are detected, phase place-the voltage conversion circuit that constitutes by the series circuit of the p channel transistor of each grid circuit output connections/cut-out and N channel transistor and the RC integrating circuit that is connected in its outgoing side.

In this structure, produce in the output of phase place-voltage conversion circuit and the threshold voltage voltage about equally that is connected in its semiconductor element (for example impact damper among Figure 39), adjust 2 phase of input signals poor (being the output of phase place-voltage conversion circuit) automatically and make that 1 or 0 occurrence rate of trigger output is certain.

According to technical scheme 17 described random number generators, it is characterized in that above-mentioned phase place-voltage conversion circuit has the parts that enable that only move when allowing action.

In this structure, only when the needs random number, send the action enabling signal, make can the active period of free control circuit between, thereby realize economize on electricity.

According to technical scheme 18 described random number generators, it is characterized in that the additional shake generative circuit that constitutes by noise-producing source, the amplifying circuit that amplifies this noise, the mixting circuit that input signal produced shake by this amplifications noise signal in the output of above-mentioned phase place-voltage conversion circuit.

In this structure, actively increase the uncertain factor of 1 or 0 probability of occurrence of trigger output.Therefore, generate easily have same type and have not regulation, correlativity and periodic more stable natural random number.

According to technical scheme 19 described random number generators, it is characterized in that having the parts that enable that only when allowing action, move.

In this structure, only when the needs random number, send the action enabling signal, make can the active period of free control circuit between, thereby realize economize on electricity.

According to technical scheme 20 described random number generators, it is characterized in that above-mentioned mixting circuit is by integrating circuit, the circuit that is connected in series with this integral output signal and above-mentioned amplification noise signal series connection p channel transistor circuit that is input and series connection N channel transistor circuit constitutes respectively.

According to technical scheme 21 described random number generators, it is characterized in that above-mentioned mixting circuit is that the N channel transistor circuit of input and the cascade transistor circuit of p channel transistor circuit constitute by the composite signal with above-mentioned amplification noise signal and above-mentioned input signal.

According to technical scheme 22 described random number generators, by the R-S trigger of the serial random number R ND of output 1 bit with between the input of this R-S trigger, give the delay circuit of 2 systems of phase differential, with the regulation of instrumentation CLK signal cycle repeatedly, and monitor 1 or 0 number of trigger output (random number data RND) in this specified period, and for making its occurrence rate (for example be maintained certain value, 50%) phase-control circuit of FEEDBACK CONTROL of adjusting the time delay of above-mentioned delay circuit and automatically constitutes, it is characterized in that respectively the p channel transistor that on the mains side of the R side grid circuit of the internal transistor circuit that constitutes above-mentioned R-S trigger or S side grid circuit, is connected in series, the N channel transistor is connected in series on the GND side, and in the input of above-mentioned p channel transistor and N channel transistor, be connected noise-producing source and the amplifying circuit that amplifies this noise, change the threshold voltage of above-mentioned grid circuit of the side by this amplification noise signal.

According to technical scheme 23 described random number generators, by the R-S trigger of the serial random number R ND of output 1 bit with between the input of this R-S trigger, give the delay circuit of 2 systems of phase differential, with the regulation of instrumentation CLK signal cycle repeatedly, and monitor 1 or 0 number of trigger output (random number data RND) in this specified period, and for making its occurrence rate (for example be maintained certain value, 50%) phase-control circuit of FEEDBACK CONTROL of adjusting the time delay of above-mentioned delay circuit and automatically constitutes, it is characterized in that respectively the p channel transistor that on the mains side of the R side grid circuit of the internal transistor circuit that constitutes above-mentioned R-S trigger or S side grid circuit, is connected in series, the N channel transistor is connected in series on the GND side, and in the input of above-mentioned p channel transistor and N channel transistor, be connected the amplifying circuit of noise-producing source and this noise of amplification, amplify the threshold voltage that noise signal changes both sides' above-mentioned grid circuit by this.

In the R-S trigger, the phase differential of the rising edge of R side input signal and S side input signal approached 0 o'clock, produced metastable phenomenon.When producing this phenomenon, trigger output needs the time before determining, the output state behind the certain hour keeps 0 or 1 or threshold voltage, perhaps is oscillatory regime.Here, in technical scheme 22 and the technical scheme 23 described structures,, can enter into 1 or 0 steady state (SS) immediately from metastable state by changing the threshold voltage of R side and/or S side grid circuit.And 1 or 0 the occurrence rate of adjusting automatically that 2 phase of input signals official posts must the output of this trigger keeps certain.

According to technical scheme 24 described random number generators, it is characterized in that the series connection input circuit that above-mentioned amplifying circuit is made of capacitor and resistance and the series circuit of p channel transistor and N channel transistor constitute, and insert resistance between the input-output of this transistor circuit.

According to technical scheme 25 described random number generators, it is characterized in that the series connection input circuit that above-mentioned amplifying circuit is made of capacitor and resistance and the series circuit of p channel transistor and N channel transistor constitute, and capacitor and the resistance of inserting in parallel between the input-output of this transistor circuit.

According to technical scheme 26 described random number generators, it is characterized in that plural serial stage connects above-mentioned amplifying circuit and constitutes.

According to technical scheme 27 described random number generators, when it is characterized in that above-mentioned noise-producing source is connected in series p channel transistor and N channel transistor, make short circuit between the input-output and constitute.

According to technical scheme 28 described random number generators, when it is characterized in that above-mentioned noise-producing source is connected in series p channel transistor and N channel transistor, between input-output, insert resistance and constitute.

According to technical scheme 29 described random number generators, it is characterized in that above-mentioned noise-producing source be connected in series p channel transistor and N channel transistor, between input-output, insert in the resistance, between input-GND, insert the series circuit of resistance and capacitor formation and constitute.

According to technical scheme 30 described random number generators, it is characterized in that above-mentioned noise-producing source be connected in series p channel transistor and N channel transistor, between input-output, insert in the resistance, between input-power supply, insert the series circuit of resistance and capacitor formation and constitute.

According to technical scheme 31 described random number generators, it is characterized in that above-mentioned noise-producing source between the input-output that makes the N channel transistor in the short circuit, between output-power supply, insert resistance and constitute.

According to technical scheme 32 described random number generators, it is characterized in that above-mentioned noise-producing source constitutes inserting resistance between the input-output of N channel transistor and between the output-power supply respectively.

According to technical scheme 33 described random number generators, when it is characterized in that above-mentioned noise-producing source makes between the input-output of p channel transistor short circuit, insert resistance between the output-GND and constitute.

According to technical scheme 34 described random number generators, it is characterized in that above-mentioned noise-producing source constitutes inserting resistance between the input-output of p channel transistor and between the output-GND respectively.

Here, in technique scheme 27 in technical scheme 34 described structures, utilization is in the faint thermonoise of circuit component (transistor, resistance, capacitor or their the combination) generation of state of activation as noise-producing source, therefore can realize by simple circuit structure with being dirt cheap.

According to technical scheme 35 described probability generators, it is characterized in that using according to technical scheme 12 described random number generators constituting.

In this structure, random number generator by have homogeneity, have not regulation, correlativity, the probability generator that periodically can realize ideal.If be used for coded communication etc., then can carry out favourable communication aspect secret.

The 3rd form of＜invention 〉

As mentioned above, as the trigger of determining the state (0 or 1) of output according to the phase differential of the signal that is input to 2 input parts, known have a D flip-flop.

This D flip-flop as shown in figure 13, be clock terminal CLK and the data terminal D that has as input part, the state (0 or 1) of data terminal D is determined the so-called edge-triggered D-flip flop of the state of output Q and Q (the counter-rotating output of Q:Q) during according to CLK input rising edge.

Here, poor (phase differential) Δ t of rising edge time that makes rising edge time of CLK signal and D signal from the state of Figure 14 (a) or Figure 14 (b) is near 0 o'clock, shown in Figure 14 (c), exist trigger output Qn ,/the uncertain phase range of Qn.And the uncertain actuating range of this trigger enlarges easier generation random number when the shake of input signal increases.

The present invention is the random number generator that actively utilizes the uncertain action of this trigger.

Promptly, according to technical scheme 36 described random number generators, phase place adjustment part and feedback circuit portion by the trigger of determining the state (0 or 1) of output according to 2 phase of input signals differences, the above-mentioned phase of input signals of adjustment, has first counter, from 1/2 the value (m) in cycle repeatedly that input signal clock instrumentation is predetermined [clock number (2 * m)]; Second counter, instrumentation at each this repeatedly in the cycle, the occurrence number of " 1 " of the output of above-mentioned trigger (or " 0 "); Register is taken into the count value of above-mentioned second counter repeatedly in the cycle and preserves at each; The constant setting apparatus is used for when this count value being set in register at every turn, with above-mentioned the 2nd counter O reset, and the occurrence rate of " 1 " (or " 0 ") of set flip-flop output; Comparer with the preservation data (n) of above-mentioned register and the comparing data (m) of coming comfortable above-mentioned constant setting apparatus, is done and comparative result n＞m or n=m or the corresponding relatively output of n＜m; The 3rd counter is with the pattern action of being set by above-mentioned relatively output, with the selection signal of above-mentioned enumeration data output as selector switch; And control above-mentioned phase differential and make the inhibit signal of above-mentioned selector switch output by the regulation of the clock signal of selecting signal to select, 0 or 1 occurrence rate of above-mentioned trigger output converges to certain value and constitutes in the cycle repeatedly of regulation, it is characterized in that above-mentioned phase place adjustment part will postpone by being provided with the 1st delay and the 2nd that the signal class ground delay of input is exported, be provided with according to selecting input to select to postpone the 1st delayer of one of output, control phase-adjusting circuit that the 3rd counter of above-mentioned selection input constitutes as the inching parts, and in above-mentioned each delay output, additional by the 3rd delay, the coarse regulation parts that the 2nd selector switch constitutes, with postpone by the 4th, the coarse regulation parts that the 3rd selector switch constitutes, be provided with the 4th counter of the selection action of pointing out to export above-mentioned the 2nd selector switch and the 3rd selector switch, with inching use the 1st postpone and be set at for the 2nd per 1 grade time delay that postpones with coarse regulation use the 3rd postpone and compare for the 4th time delay that postpones about below 1/20, the expansion of realization phase place adjusting range and the shortening of phase place adjustment time.

According to technical scheme 37 described random number generators, it is characterized in that above-mentioned coarse regulation parts and inching parts are respectively by with the delay circuit of above-mentioned input signal multilevel delay and output, constitute according to the selection circuit of selecting input to select to postpone one of output with according to the up-down counter that above-mentioned phase differential is controlled above-mentioned selection input.

In technique scheme 36 or the technical scheme 37 described structures, by carry out the phase place coarse regulation, inching can enlarge the scope of phase place adjustment and effectively carry out the phase place adjustment.

According to technical scheme 38 described random number generators, phase place adjustment part and feedback circuit portion by the trigger of determining the state (0 or 1) of output according to 2 phase of input signals differences, the above-mentioned phase of input signals of adjustment, has first counter, from 1/2 the value (m) in cycle repeatedly that input signal clock instrumentation is predetermined [clock number (2 * m)]; Second counter, instrumentation at each this repeatedly in the cycle, the occurrence number of " 1 " of the output of above-mentioned trigger (or " 0 "); Register is taken into the count value of above-mentioned second counter repeatedly in the cycle and preserves at each; The constant setting apparatus is used for when this count value being set in register at every turn, with above-mentioned the 2nd counter O reset, and the occurrence rate of " 1 " (or " 0 ") of set flip-flop output; Comparer with the preservation data (n) of above-mentioned register and the comparing data (m) of coming comfortable above-mentioned constant setting apparatus, is done and comparative result n＞m or n=m or the corresponding relatively output of n＜m; The 3rd counter is with the pattern action of being set by above-mentioned relatively output, with the selection signal of above-mentioned enumeration data output as selector switch; And control above-mentioned phase differential and make the inhibit signal of above-mentioned selector switch output by the regulation of the clock signal of selecting signal to select, 0 or 1 occurrence rate of above-mentioned trigger output converges to certain value in the cycle repeatedly of regulation feedback circuit constitutes, it is characterized in that above-mentioned phase place adjustment part is by the delay circuit with above-mentioned input signal multilevel delay and output, according to selecting to import the up-down counter formation of selecting to postpone the selection circuit of one of output and controlling above-mentioned selection input according to above-mentioned phase differential, and, the normal distribution and the occurrence number in 0 or 1 in the above-mentioned cycle repeatedly with occurrence rate of contrast 0 or 1, can change the control circuit of the counting of above-mentioned up-down counter according to the position of the above-mentioned normal distribution of this occurrence number correspondence, realize that phase place adjusts the shortening of time.

In this structure, in the few zone of 0 or 1 occurrence number, the switching width that postpones output increases, and carries out the coarse regulation of phase place, and the switching width that will postpone to export along with the central authorities near normal distribution reduces to come the inching phase place.Can effectively carry out the phase place adjustment thus.

According to technical scheme 39 described random number generators, begin when it is characterized in that having from power connection certain during, the initial control circuit that the cycle repeatedly when above-mentioned period ratio is repeatedly moved usually is short.

Thus, can shorten voltage be switched to generate suitable random number during.

According to technical scheme 40 described random number generators, it is characterized in that source and noise/phase transformer take place additional noise on two incoming lines of above-mentioned trigger.

According to technical scheme 41 described random number generators, it is characterized in that source and noise/phase transformer take place additional noise on an incoming line of above-mentioned trigger.

In technical scheme 40 or the technical scheme 41 described structures, the signal that is input to trigger produces shake, and the uncertain actuating range of trigger enlarges.Thus, can be at a high speed and generate accurately and have homogeneity and have not regulation and correlativity and periodic more stable natural random number.

The 4th form of＜invention 〉

Among the present invention, be conceived to the built-in reliability that will improve, can oneself check the function of the same type of appearance of random number data as 1 bit random number generator, many bits random number generator and probability generator.

Promptly, technical scheme 42 described 1 bit random number generators in according to the present invention, it is characterized in that having output 0 and 1 randomizer as random number data, have first counter that certain number of times is counted and to count and generate second counter of time logarithmic data from the occurrence number of the random number data of above-mentioned randomizer output, have the register that in each cycle of first rolling counters forward, keeps the inferior logarithmic data of second counter, have the output circuit that the inferior logarithmic data of this register maintenance is exported as check data.

Among the present invention according to technical scheme 43 described 1 bit random number generators, the above-mentioned output circuit that it is characterized in that alternate embodiments 42 has data that keep in more predefined upper limit comparing data and lower limit comparing data and the register and the comparer of exporting the check signal.

Among the present invention according to technical scheme 44 described 1 bit random number generators, it is characterized in that having output 0 and 1 randomizer as random number data, have the data retainer of maintenance from the random number data of the last time of this randomizer output, have the output of more above-mentioned randomizer this random number data and above-mentioned data retainer in the random number data of last time of keeping, the output counting increases signal when the two is identical, not not simultaneously simultaneously at the two, the comparer of output counting clear signal, have when when above-mentioned comparer count pick up increases signal, increasing counting, from above-mentioned comparer count pick up clear signal the time, count the counter of removing, have data that this counter is kept output circuit as check data output.

Among the present invention according to technical scheme 45 described 1 bit random number generators, it is characterized in that having output 0 and 1 randomizer as random number data, have the data retainer of maintenance from the random number data of the last time of this randomizer output, have the output of more above-mentioned randomizer this random number data and above-mentioned data retainer in the random number data of last time of keeping, the output counting increases signal when the two is identical, not not simultaneously simultaneously at the two, first comparer of output counting clear signal, have when when the first above-mentioned comparer count pick up increases signal, increasing counting, from the first comparer count pick up clear signal time, count the counter of removing, have the register of the output data that keeps this counter, have the relatively data of this register and the output data of above-mentioned counter, when the latter is bigger than the former, write out the data rewrite signal, second comparer of while output data holding signal under situation in addition, have the output data that is controlled to when receiving the data rewrite signal above-mentioned counter and write above-mentioned register, simultaneously at the control circuit that when second comparer receives the data holding signal, keeps the data of above-mentioned register from second comparer; Have the output circuit that the data of above-mentioned register maintenance are exported as check data.

Among the present invention according to technical scheme 46 described 1 bit random number generators, the above-mentioned output circuit that it is characterized in that alternate embodiments 45 has data that keep in more predefined comparing data and the register and the 3rd comparer of exporting the check signal.

Among the present invention according to technical scheme 47 described a kind of 1 bit random number generators, it is characterized in that having output 0 and 1 randomizer as random number data, have first counter that certain number of times is counted, have the data retainer of maintenance from the random number data of the last time of above-mentioned randomizer output, have the output of more above-mentioned randomizer this random number data and above-mentioned data retainer in the random number data of last time of keeping, the output counting increases signal when the two is identical, not not simultaneously simultaneously at the two, the comparer of output counting clear signal, have when when above-mentioned comparer count pick up increases signal, increasing counting, from above-mentioned comparer count pick up clear signal the time, count second counter of removing, have the output data of decoding second counter and the demoder of exporting by each signal length, have a plurality of the 3rd counters of the output data of this demoder being counted respectively by each signal length, have by each of first rolling counters forward and decide each a plurality of registers of output data that number of times keeps the 3rd counter respectively, have and be controlled to according to the output data of the signal of deciding number of times by each of first rolling counters forward and above-mentioned comparer control circuit from above-mentioned each register output check data.

According to technical scheme 48 described 1 bit random number generators, it is characterized in that the output data of additional mask register and the selection circuit of output among the present invention.

Among the present invention according to technical scheme 49 described many bits random number generators, it is characterized in that connecting side by side a plurality of technical scheme 42 described 1 bit random number generators, additional by per 1 bit select and output from the selection circuit of the check data of these 1 bit random number generators outputs.

Among the present invention according to technical scheme 50 described many bits random number generators, it is characterized in that connecting side by side a plurality of technical scheme 42 described 1 bit random number generators, additional by per 1 bit select and output from the selection circuit of the check signal of these 1 bit random number generators outputs.

Among the present invention according to technical scheme 51 described probability generators, it is characterized in that the scheme of possessing skills 42 described 1 bit random number generators, have and to be transformed to the shift register of parallel data from the random number data of this 1 bit random number generator output from serial data, have the counter that the bit length of certain parallel data is counted, have the register that keeps the parallel data of above-mentioned shift register by each cycle of this rolling counters forward, have the parallel data that keeps in more predefined probability upper limit data and probability lower limit data and the above-mentioned register and the comparer of output probability signal.

Among the present invention according to technical scheme 52 described probability generators, it is characterized in that the scheme of possessing skills 49 described many bits random number generators, have more predefined probability upper limit data and probability lower limit data and the random number data of exporting from above-mentioned many bits random number generator and the comparer of output probability signal.

In these structures, enumerate D flip-flop as the typical example of data retainer, the typical example of device is enumerated XOR and element (EXCLUSIVE-OR element) as a comparison.And, by adopting this structure, can oneself check the appearance homogeneity of random number data, the user does not need to carry out statistical treatment.

For simplicity, therefore corresponding components in the parenthetic symbol table diagrammatic sketch the invention is not restricted to the record among the figure.

Brief description of drawings

Fig. 1～Figure 14 represents first form of the present invention.Among these figure,

Fig. 1 is the circuit diagram of first embodiment of expression random number generator of the present invention;

Fig. 2 is identical with Fig. 1, but the circuit diagram of second embodiment of expression random number generator;

Fig. 3 is the circuit diagram of the 3rd embodiment of expression random number generator;

Fig. 4 is the circuit diagram of the 4th embodiment of expression random number generator;

Fig. 5 is the circuit diagram of the 5th embodiment of expression random number generator;

Fig. 6 is the component circuitry figure that expression has added the random number generator of the present invention of waveform shaping circuit;

Fig. 7 is the figure of the concrete waveform shaping circuit of expression;

Fig. 8 is the figure of input and output waveform of the waveform shaping circuit of presentation graphs 7;

Fig. 9 is the component circuitry figure of the random number generator of the present invention of the additional initial control circuit of expression;

Figure 10 is the component circuitry figure that the random number generator of the present invention of R-S trigger is used in expression;

Figure 11 is the block diagram of parallel type random number generator of the present invention;

Figure 12 is the figure of the probability distribution of expression probability generator of the present invention;

Figure 13 is the figure of expression D flip-flop;

Figure 14 is the figure of input and output waveform of the D flip-flop of expression Figure 13;

Figure 15～Figure 47 represents second form of implementation of the present invention.Among these figure,

Figure 15 is the figure of first embodiment of the random number generator of expression second form of the present invention;

Figure 16 is the figure of the expression formation different with above-mentioned random number generator (Figure 15);

Figure 17 is the figure of the structure of expression shake generative circuit of the present invention;

Figure 18 is the figure of the structure different with Figure 17 of expression shake generative circuit of the present invention;

Figure 19 is the figure of the input and output waveform during the expression shake generates;

Figure 20 is the figure of the formation of expression noise-producing source of the present invention;

Figure 21 is the figure of the structure different with Figure 20 of expression noise-producing source of the present invention;

Figure 22 is the figure of the structure different with Figure 21 of expression noise-producing source of the present invention;

Figure 23 is the figure of the structure different with Figure 22 of expression noise-producing source of the present invention;

Figure 24 is the figure of the structure different with Figure 23 of expression noise-producing source of the present invention;

Figure 25 is the figure of the structure different with Figure 24 of expression noise-producing source of the present invention;

Figure 26 is the figure of the structure different with Figure 25 of expression noise-producing source of the present invention;

Figure 27 is the figure of the structure different with Figure 26 of expression noise-producing source of the present invention;

Figure 28 is the figure of the structure of expression amplifying circuit of the present invention;

Figure 29 is the figure of the structure different with Figure 28 of expression amplifying circuit of the present invention;

Figure 30 is the figure of expression shake generative circuit of the present invention;

Figure 31 is the figure of the structure different with Figure 30 of expression shake generative circuit of the present invention;

Figure 32 is the figure of the structure different with Figure 31 of expression shake generative circuit of the present invention;

Figure 33 is the figure of the structure different with Figure 32 of expression shake generative circuit of the present invention;

Figure 34 is the figure of the structure different with Figure 33 of expression shake generative circuit of the present invention;

Figure 35 is the figure of the structure different with Figure 34 of expression shake generative circuit of the present invention;

Figure 36 is the figure of the structure different with Figure 35 of expression shake generative circuit of the present invention;

Figure 37 is the component circuitry of the random number generator of the present invention of the additional latch cicuit of expression;

Figure 38 is the component circuitry figure different with Figure 37 of the random number generator of the present invention of the additional latch cicuit of expression;

Figure 39 represents the figure of second embodiment of the random number generator of second form of the present invention;

Figure 40 is the figure of expression phase place-voltage conversion circuit of the present invention;

Figure 41 (a) and Figure 41 (b) are the figure of phase place-voltage conversion circuit of expression Figure 40;

Figure 42 is the figure of the structure different with Figure 40 of expression phase place-voltage conversion circuit of the present invention;

Figure 43 is the structural drawing different with Figure 39 of the random number generator of expression above-mentioned second embodiment of the present invention;

Figure 44 is the figure of the 3rd embodiment of expression random number generator of the present invention;

Figure 45 is the figure of the inner structure of expression R-S trigger;

Figure 46 is the figure of inner structure of R-S trigger of the 3rd embodiment of expression above-mentioned second form of the present invention;

Figure 47 is the figure of inner structure of the R-S trigger different with Figure 46 of the expression third embodiment of the present invention;

Figure 48～Figure 54 represents the 3rd form of implementation of the present invention.Among these figure,

Figure 48 is the structural drawing of random number generator of first embodiment of expression the 3rd form of implementation of the present invention;

Figure 49 is the figure of the structure different with Figure 48 of the random number generator of above-mentioned first embodiment of expression;

Figure 50 is the structural drawing of the random number generator of expression second embodiment;

The figure of the coarse regulation when Figure 51 is the adjustment of expression phase place and the actuating range of inching;

Figure 52 is the structural drawing of the random number generator of expression the 3rd embodiment;

Figure 53 is the figure of normal distribution that expression has the random number of homogeneity;

Figure 54 is the figure of cutting apart the normal distribution of weighting Figure 53;

Figure 55～Figure 67 represents the 4th form of the present invention, among these figure,

Figure 55 is the circuit diagram of first embodiment of expression 1 bit random number generator of the present invention;

Figure 56 is the circuit diagram of second embodiment of expression 1 bit random number generator of the present invention;

Figure 57 is the circuit diagram of the 3rd embodiment of expression 1 bit random number generator of the present invention;

Figure 58 is the circuit diagram of the 4th embodiment of expression 1 bit random number generator of the present invention;

Figure 59 is the circuit diagram of the 5th embodiment of expression 1 bit random number generator of the present invention;

Figure 60 is the circuit diagram of the 6th embodiment of expression 1 bit random number generator of the present invention;

Figure 61 is the circuit diagram of the 7th embodiment of expression 1 bit random number generator of the present invention;

Figure 62 is the circuit diagram of first embodiment of expression many bits random number generator of the present invention;

Figure 63 is the circuit diagram of second embodiment of expression many bits random number generator of the present invention;

Figure 64 is the circuit diagram of first embodiment of expression probability generator of the present invention;

Figure 65 is the circuit diagram of second embodiment of expression probability generator of the present invention;

Figure 66 is the circuit diagram of the 3rd embodiment of expression probability generator of the present invention;

Figure 67 is the circuit diagram of the 4th embodiment of expression probability generator of the present invention.

The optimised form that carries out an invention

The embodiment of＜the first form 〉

The form of implementation of random number generator of the present invention and probability generator at first is described to Figure 12 according to Fig. 1.

Fig. 1 is the circuit diagram of expression random number generator.

As shown in Figure 1, the random number generator 110 of first embodiment is made of trigger 101 and delay portion 102 and feedback circuit 103.

Here, can use as above-mentioned trigger 101 and to have the trigger of function of determining the state (0 or 1) of output according to the phase differential of the input signal (CLOCK) that is input to 2 input parts, in the present embodiment, use D flip-flop shown in Figure 13 in the signal input with clock terminal CLK and data terminal D.

Above-mentioned delay portion 102 has a plurality of delay lead-out terminals, by 2 delay circuits 117 that are connected in series, 118 (lag lines) and according to selecting input to select this selection circuit 119 (selector switch) that postpones one of output to constitute, above-mentioned 2 delay circuits 117,118 tie point (delay intermediate point) is connected in the clock terminal CLK of above-mentioned D flip-flop 101, select the output of circuit 119 to be connected in data terminal D simultaneously, the rising edge time phase difference of 2 signals of input can be adjusted arbitrarily in the D flip-flop 101.

Above-mentioned feedback circuit 103 is made of first counter 111, second counter 112, register 114, constant setting apparatus 116, comparer 115 and up-down counter 113 (on/following counter).

The predetermined cycle repeatedly of first counter, 111 instrumentation input signal CLOCK, (CLOCK number (2 * m)), second counter 112 be this appearance number of 1 (or 0) of the above-mentioned trigger output of instrumentation in cycle repeatedly at each.Cycle is taken into and keeps the count value of second counter 112 to register 114 repeatedly at each.When in addition, each count value is arranged in the register 114 just with 112 zero clearings of second counter.116 outputs of constant setting apparatus are used for the comparing data of the occurrence rate of set flip-flop output 1 (or 0).In the present embodiment, be redefined for (1/2 value (m) of CLOCK number (2 * m)) of above-mentioned cycle repeatedly of output.The maintenance data (n) of comparer 115 comparand registers 114 and from the comparing data (m) of constant setting apparatus 116, corresponding comparative result (n＞m) or (n=m) or (n＜m) produces relatively output.Up-down counter 113 is selected this enumeration data the selection signal s output of circuit 119 by according to the pattern action of setting from the relatively output of above-mentioned comparer 115 as subordinate.And, as mentioned above, select circuit 119 outputs to select the regulation inhibit signal of the former CLOCK signal of signal s selection.

Promptly, according to said structure, the output data (n) of the corresponding register 114 of up-down counter and from the relatively output of the output data (m) of this constant setting apparatus 116 each repeatedly the cycle carry out on/(counting for example makes progress during n＞m in action down, when n＜m, count downwards), the rising edge time of CLOCK signal that is input to the data terminal D of D flip-flop 101 from normal moveout correction makes the relatively output of comparer 115 be converged in n=m (the counting action stops during n=m, and the phase differential of CLOCK signal is kept necessarily).Specifically, shown in Figure 14 (c), the phase difference t of rising edge that is controlled to be the rising edge of CLK signal and D signal is near 0.Thus, obtain the serial random number data OUT that 0 and 1 occurrence rate is usually kept 50% 1 bit that homogeneity is arranged in the output of D flip-flop 101.

In the present embodiment, the comparing data of setting in the constant setting apparatus 116 be set at first counter 111 cycle repeatedly 1/2 (that is, m), but by changing this m value, 0 or 1 the occurrence rate that D flip-flop can be exported is set in beyond 50%.For example, m is set in repeatedly 1/5 of the cycle, then 0 or 1 occurrence rate is 20%.

But therefore, among above-mentioned first embodiment, usually be fixed as necessarily that (2 * m), the random number that generates might be expressed the tendency in several cycles the cycle repeatedly of first counter 111.Below, Fig. 2 is the method that the periodicity of this random number is completely lost to second to the 4th embodiment shown in Figure 5.

Second embodiment at first shown in Figure 2 substitutes above-mentioned constant setting apparatus 116 and shift register 121, totalizer 122, comparer 123 etc. newly is set, will each repeatedly the random number series of cycle output as next setting data in cycle (2 * m) and the embodiment of the comparing data (m) of comparer 115 repeatedly.122 of above-mentioned totalizers will be exported random number with random number series as above-mentioned setting data and comparing data, and (0～m-1) scope adds 1 and changes to (1～m) scope.New comparer 123 produces repeatedly the cycle (2 * m) from the enumeration data (A) of first counter 111 and the output data (m) of totalizer 122.

Then, the 3rd embodiment shown in Figure 3 appends encrypted circuit 124 to above-mentioned second embodiment, and the random number of output is encrypted the embodiment of back as above-mentioned setting data and comparing data.Also have, so-called encrypt be a plurality of data lines of mutual logical operation arbitrary data (for example XOR and, XOR and and XOR and between XOR with etc.) be transformed to the data different with former data, among Fig. 3, output data 16 bits of shift register 121 are transformed to the data of 8 bits by encrypted circuit 124.

According to these second, third embodiment, change the cycle repeatedly when producing random number gradually, therefore the periodicity of the random number that generates is eliminated fully.

Then, the 4th embodiment shown in Figure 4 is the auxiliary random number generator 104 of the random number generator of above-mentioned second embodiment of additive correction, the random number series that this auxiliary random number generator 104 is generated with above-mentioned same as the setting data in cycle repeatedly (2 * m) with the embodiment of the comparing data (m) of comparer 115, the 5th embodiment shown in Figure 5 is auxiliary random number generator 105 with the random number generator of above-mentioned the 3rd embodiment is additional, the embodiment that the output of the output of auxiliary random number generator 105 and random number generator 110 self is encrypted.

According to these the 4th, the 5th embodiment, the random number that becomes the auxiliary random number generator 104,105 of above-mentioned setting data and comparing data is used for the internal circuit of random number generator 110, do not export to the outside, therefore the character that the third party can not the prediction random number, tendency, periodically, thus natural completely random number obtained.

Fig. 6 is the component circuitry of the random number generator of the additional waveform shaping circuit 125 of expression.Like this, when the incoming line of D flip-flop 101 (D terminal and CLK terminal) is gone up the edge of additional waveform shaping circuit 125 each input signal of pressure passivation, easier generation random number.

Fig. 7 represents to insert between the grid of input and output the integrating circuit that resistance R and capacitor C constitute and the above-mentioned waveform shaping circuit 125 that constitutes.Input and output waveform shown in Fig. 8 (a) is such, produces shake Δ j on the threshold voltage of grid and the intersection point of integrated waveform in output waveform.The relation of the slope λ of the intersection point portion of Fig. 8 (b) expression threshold voltage and integrated waveform and shake Δ j, but this slope λ (being the signal passivation) is when increasing, and shake Δ j also increases.That is, the uncertain actuating range of the expanded in size trigger of this shake Δ j, the easier generation random number of result.

As the waveform shaping circuit 125 that relates to, be not only above-mentioned resistance R and capacitor C and constitute, for example can constitute by coil and capacitor.

As shown in Figure 9, among second to the 5th above-mentioned embodiment, the initial control circuit 126 that initialization circuit 126a and grid circuit 126b constitute during the additional initialization on the random number output line that comparing data is used is only forced this comparing data to be made as 0 during the cycle repeatedly of regulation during power connection.By the initialization of this comparing data, can effectively carry out the phase of input signals corrective action during power connection, be minimum from power connection to the transition period that obtains suitable random number.

More than among Shuo Ming the embodiment,, use D flip-flop, but the invention is not restricted to this, can use to have the trigger of identical function therewith as the trigger of random number generation usefulness.For example, express the structure of using the R-S trigger as other examples Figure 10.According to Figure 10, delay circuit 117 is connected the input that is provided with of R-S trigger 101 with 118 tie point, selects the input that resets of the output connection R-S trigger 101 of circuit 119.

As shown in figure 11, configuration P is individual side by side for the random number generator 110 of above-mentioned serial type, the feasible parallel type random number generator 120 that can constitute the P bit architecture.There is not any relation between each random number generator 110 in this parallel type random number generator 120.

Then the probability generator that random number generator of the present invention constitutes is used in explanation.

The probability distribution of representing the probability generator that P (bit) constitutes among Figure 12.Above-mentioned parallel type random number generator is usually proofreaied and correct 1 or 0 occurrence rate in each random number generator and is for example 50%.Each random number generator 110 have homogeneity and have not regulation, correlativity and periodically, therefore whole probability distribution is identical.

Here, (r1 r2), but makes with the following formula generating probability the identical output data integral body of this random number generator all to be set any range data shown in the oblique line of Figure 12.

P0＝(r2-r1+1)/2 ^P

Therefore, by suitable setting range data (r1～r2) can obtain any probability.

As described above like that, with digital circuit can realize having homogeneity and have not regulation, correlativity and periodic natural random number generator and probability generator.If digital circuit structure is then tackled LSIization easily, help producing, can provide a large amount of random numbers and probability data at a high speed at an easy rate to the purposes of extensive fields such as science and technology calculating, game machine, encryption.

Because the influence of external factor such as external noise, temperature, power supply change is little, can obtain stable action.And, help environmentAL safety, do not have because of scrapping after once using to wait to make to scrap partly and have problems.

The embodiment of＜the second form 〉

According to Figure 15～Figure 47 the random number generator of second form of the present invention and the embodiment of probability generator are described below.

The first embodiment of the present invention at first is described, as shown in figure 15, the random number generator 210 of first embodiment provides 2 system delay circuit 202 of phase differential by the trigger 201 of the serial random number R ND of output 1 bit, to this trigger input (CLK signal), 203, to each delay circuit 202, the phase-control circuit 205 of the time delay of the 203 shake generative circuits 204,204 that add, the above-mentioned delay circuit 203 of adjustment constitutes.

The cycle repeatedly of the regulation of above-mentioned phase-control circuit 205 instrumentation CLK signals, automatically adjust the FEEDBACK CONTROL of the time delay of above-mentioned delay circuit 203 simultaneously, monitor 1 or 0 number of trigger output (random number R ND) in this specified period, make its occurrence rate maintain certain value (for example 50%), the result is about the first embodiment of the present invention, shown in Figure 14 (c), move near 0 by 2 phase of input signals difference Δ t that are input to trigger 201.

In addition, the upward additional trigger 206 of final level is to make the output timing of random number data RND and the latch cicuit of CLK signal Synchronization.

Here, as above-mentioned trigger 201, can use the trigger that has according to the edge-triggered type of the definite state of exporting (0 or 1) of phase of input signals difference, in the present embodiment, use has the D flip-flop of CLK terminal and D terminal, brings out phase jitter by shake generative circuit 204 described below in input signal simultaneously and actively causes uncertain action.

As shown in figure 17, the amplifying circuit 208 that amplified by noise-producing source 207, the faint noise power that will produce of above-mentioned shake generative circuit 204, the mixting circuit 209 that makes input signal produce shake by the noise signal of amplifying constitute.

The mixting circuit 209 that loads on the shake generative circuit 204 of Figure 17 is the P channel MOS transistor Q4 that will be connected in series, the circuit of Q3 and the N-channel MOS transistor Q2 that is connected in series, the circuit of Q1 be connected in series (cascade) constitute, in each cascade transistor circuit, be connected the output of above-mentioned amplifying circuit 208 on the grid of transistor Q4 and Q1, be connected the output of the integrating circuit 212 of resistance R and capacitor C formation simultaneously on the grid of transistor Q3 and Q2.In addition, input IN goes up the output that connects above-mentioned delay circuit 202 or delay circuit 203.

In the foregoing circuit structure, as shown in figure 19, the noise signal of amplification is input on the grid of transistor Q4 and Q1, thus the integration output waveform of relative delay CLK signal change transistor Q3, and the threshold voltage of Q2 makes output OUT produce shake Δ j.The expanded in size of this shake Δ j is to the uncertain actuating range of the trigger 201 of back level.

As mixting circuit 209, except that the embodiment of Figure 17, can adopt structure shown in Figure 180.The embodiment of Figure 18 is made of the series circuit of P channel MOS transistor Q2 and N channel transistor Q1, on each grid the output of amplifying circuit 208 with from the input IN delay CLK signal be connected with resistance R through capacitor C respectively.

Therefore, in the foregoing circuit structure, the noise signal of amplification and the CLK signal by the adjustment of delay circuit phase place are synthetic and be input to transistor Q2 by capacitor C, and be identical with the situation of Figure 17 on the grid of Q1, obtains having the output OUT of identical shake Δ j.

The formation of above-mentioned noise-producing source 207 then is described.

Figure 20～Figure 27 represents the particular circuit configurations of noise-producing source 207.

Figure 20 is be connected in series P channel MOS transistor Q2 and N-channel MOS transistor Q1, the structure of short circuit between grid-output.Figure 21 inserts resistance R 2 between grid-output among Figure 20.Figure 22 is be connected in series P channel MOS transistor Q2 and N-channel MOS transistor Q1, when inserting resistance R 2 between grid-output, inserts the structure of the RC series circuit that resistance R 1 and capacitor C1 constitute between grid-GND.Figure 23 is in the structure that the above-mentioned RC series circuit among Figure 22 is inserted between grid-power supply.Figure 24 is grid-output of short circuit N-channel MOS transistor Q1, inserts the structure of resistance R 1 between output-power supply.Figure 25 is a structure of inserting resistance R 2 in Figure 24 between grid-output.Figure 26 is between grid-output of short circuit P channel MOS transistor Q1, inserts the structure of resistance R 1 between output-GND.Figure 27 is a structure of inserting resistance R 2 in Figure 26 between grid-output.

In the foregoing description, utilize the faint thermonoise of circuit component (transistor, resistance, capacitor or its combination) generation that is in state of activation, can realize cheap noise source.When obtaining little, the stable action of the influence of external noise and power supply change etc., do not utilize radiation source, therefore favourable to environmentAL safety, can not have problems because of scrapping after once using to wait to make to scrap partly.

Series connection input circuit (Hi-pass filter) that amplifying circuit 208 shown in Figure 28 is made of capacitor C1 and resistance R 1 and the series circuit of P channel MOS transistor Q2 and N-channel MOS transistor Q1 constitute, and amplifying circuit 208 shown in Figure 29 is to return the structure that the capacitor C2 that is connected in parallel on the resistance R 2 forms low-pass filter in Figure 28.Though not shown, the input IN of these amplifying circuits 208 goes up the output that connects above-mentioned noise-producing source 207, output OUT connects above-mentioned mixting circuit 209.

In the amplifying circuit 208 of said structure, each structure of corresponding above-mentioned noise-producing source 207 is set the characteristic of above-mentioned Hi-pass filter and low-pass filter, realizes the amplifier of appropriate characteristics.

The particular circuit configurations of shake generative circuit 204 then is described according to Figure 30～Figure 36.These are also by the constituting of above-mentioned noise-producing source 207, amplifying circuit 208 and mixting circuit 209, below shown in be wherein sign example.Therefore, the invention is not restricted to these circuit example.

Figure 30 is shake generative circuit 204 the constituting by noise-producing source shown in Figure 20 207 and amplifying circuit 208 shown in Figure 28 of the structure of Figure 17.Figure 31 is the circuit example of 2 grades of formations of among Figure 30 amplifying circuit 208 being connected in series.

Figure 32 is that each mains side at noise-producing source 207 and amplifying circuit 208 and mixting circuit 209 is connected P channel MOS transistor Q14 in Figure 31, Q24, Q34, the on-off circuit 214. that Q46 constitutes connects N-channel MOS transistor Q11 on each ground connection side, Q21, Q31, the on-off circuit 215 that Q41 constitutes, by these on-off circuits 214 of action enabling signal ENABLE ON/OFF from the outside, 215, specifically, by only when needing random number, each circuit supply being made the structure of shake generative circuit 204 actions.

Like this, by ena-bung function can the active period of free restricting circuits between, do not waste useless power, realize the low-power consumption of random number generator.

Figure 33～Figure 36 is based on the shake generative circuit 204 of the structure of Figure 18, and the array configuration of each noise-producing source 207 and amplifying circuit 208 is identical with the situation of above-mentioned Figure 30～Figure 32, therefore omits explanation here.

The embodiment of shake generative circuit 204 has been described above, but should shake generative circuit 204 among the present invention except that to the structure of the random number generator 210 of the additional Figure 15 of two incoming lines (CLK terminal and D terminal) of above-mentioned trigger 201, it can be the structure that only will shake Figure 16 of the incoming line (being the D terminals side in the present embodiment) that generative circuit 204 is additional to trigger 201, thus, obtain the effect identical with the structure of Figure 15.

At this moment, for cooperating the two incoming timing of input terminal, another incoming line (being the CLK terminal in the present embodiment) is gone up the RC integrating circuit 213 (time constant that is equivalent to the integrating circuit 212 of Figure 17) of the time delay that additive correction causes by shake generative circuit 204.

But, in shake generative circuit 204, produces following incorrect: produce the vibration that the integrated waveform input produces in the output of mixting circuit 209, in 1 time random number generation cycle, import input signal repeatedly on the input terminal of trigger 201.

Therefore, in the present embodiment,, shown in 38, be arranged on the R-S trigger 211 of two edge (rising edge/negative edge) actions (being provided with/reset) of CLK signal on the back level of shake generative circuit 204, the output OUT of mixting circuit 209 CLK signal breech lock as Figure 37.Thus, can import the signal that does not have vibration on the trigger 201, can carry out stable random number and generate.In addition, in the structure of Figure 38,, also in the impact damper output of back level, produce vibration, therefore additional R-S trigger 211 for integrating circuit 213.

More than among Shuo Ming the embodiment, as the trigger 211 of random number generation usefulness, using D flip-flop 201, but the invention is not restricted to this, can be the trigger that has identical function therewith, for example can use the R-S trigger.

Second embodiment of second form of the present invention then is described.

As shown in figure 39, the random number generator 210 of second embodiment is by the D flip-flop 218 of the serial random number R ND of output 1 bit and the delay circuit 202 of 2 systems, 203 and phase place-voltage conversion circuit 217 constitute with unshowned phase-control circuit 205 (with reference to Figure 15,16).

Here, above-mentioned phase place-voltage conversion circuit 217 is with delay circuit 202, the phase difference variable of 203 delay output signal is changed to the circuit of voltage, shown in the internal circuit of Figure 40, export P channel MOS transistor Q2 and the series circuit of N-channel MOS transistor Q1 and the RC integrating circuit formation that on its outgoing side, is connected of on/off by the grid circuit that detects the phase differential of importing IN (CLK) and input IN (D), by each grid circuit.

Phase place-the voltage conversion circuit 217 of said structure is shown in Figure 41 (a), when the phase place of IN (D) is more forward than IN (CLK), only partly connect P channel MOS transistor Q2 (its separated N-channel MOS transistor Q1) at this phase differential, to capacitor C charging, input voltage v (th) rising of impact damper is moved through resistance R.Shown in Figure 41 (b), when the phase place of IN (D) lags behind than IN (CLK), only partly connect N-channel MOS transistor Q1 (its separated P channel MOS transistor Q2), to capacitor C discharge, input voltage v (th) decline of impact damper is moved through resistance R at this phase differential.

Therefore, produce in the output of this phase place-voltage conversion circuit 217 and the threshold voltage voltage v (th) about equally that is connected in its impact damper, by 2 inputs, the change of this output voltage that IN (CLK) and IN (D) phase differential generate is by the digital signalization and be input to the D terminal of trigger 218 with the relation of the threshold voltage of impact damper, obtains the random number data RND with 1 bit of CLK signal Synchronization in output.Then, this random number data RND is monitored by above-mentioned phase-control circuit 205, adjusts 2 phase of input signals poor (being the output of phase place-voltage conversion circuit 217) automatically, the occurrence rate certain (for example being 50%) that makes trigger output 1 or 0.

Though not shown, among Figure 39, by the RC integrating circuit back resistance that is connected in series, the noise that resistance sends more effectively carries out the threshold value action of subordinate's element that the change of v (th) causes.

In addition, among Figure 39, insert impact damper between phase place-voltage conversion circuit 217 and the trigger 218, but can not insert impact damper and be directly connected in the D terminal of trigger 218.At this moment, the output voltage v (th) of phase place-voltage conversion circuit 217 roughly adjusts to the threshold voltage of D terminal automatically.

Substituting above-mentioned impact damper and use comparer, can be the structure that can obtain digital signal by relatively this output voltage v (th) and reference voltage.

As shown in figure 42, additional P channel MOS transistor Q4 and N-channel MOS transistor Q5 on the cascade transistor circuit of phase place-voltage conversion circuit 217, by from the action enabling signal ENABLE of outside where necessary between beyond the halt circuit action, can realize low-power consumption.

Figure 43 is the structure that connects shake generative circuit 204 at the outgoing side of phase place-voltage conversion circuit 217.This shake generative circuit 204 is the Figure 17 that is made of noise-producing source 207, amplifying circuit 208 and mixting circuit 209, the structure of Figure 18, omits explanation here.

Connect shake generative circuit 204, make threshold voltage V (th) produce shake, make that occurring 0 or 1 the unstable key element of probability in the trigger output actively increases, generate easily thus have homogeneity and have not regulation, correlativity and periodic stable natural random number.

The 3rd embodiment of second form of the present invention then is described.

As shown in figure 44, the random number generator of the 3rd embodiment is by the R-S D-flip flop 216 of the serial random number R ND of output 1 bit and the delay circuit 202 of S terminal that is connected this R-S D-flip flop 216 and R terminal, 203 and unshowned phase-control circuit 205 (with reference to Figure 15,16) constitute.

Here, Figure 45 expresses the internal circuit of the above-mentioned R-S D-flip flop of N-channel MOS transistor and P channel MOS transistor formation, by the NAND grid circuit of transistor Q1～Q4 formation S side, constitutes the NAND grid circuit of R side by transistor Q5～Q8.

For example, in the trigger of this edge-triggered type of R-S D-flip flop, the phase differential of the rising edge of S side input signal and R side input signal was near 0 o'clock, the metastable phenomenon of known generation, when this phenomenon produces, needed the time before trigger output is determined, the output state behind the certain hour keeps 0 or 1 or threshold voltage or be one of oscillatory regime.Present embodiment is actively to utilize this metastable phenomenon to generate the nature random number.

Promptly, in the present embodiment, as shown in figure 46, in the circuit structure of Figure 45, the P channel MOS transistor Q10 that is connected in series on the power Vcc side of the NAND grid circuit of S side is when being connected in series N-channel MOS transistor Q9, at these transistors Q9 on the GND side, connect noise-producing source 207 and amplifying circuit 208 on the grid of Q10, amplify the threshold voltage that noise signal changes the NAND grid circuit of S side by this.In addition, terminal S goes up the output of connection delay circuit 202, the output that terminal R goes up connection delay circuit 203.Figure 47 is an additional foregoing circuit on the two NAND grid circuit of S side, R side, and the structure of noise signal is amplified in input respectively.

In the said structure,, trigger output immediately can be changed into 1 or 0 steady state (SS) from metastable state by changing the threshold voltage of NAND grid circuit.And random number data RND monitors that by above-mentioned phase-control circuit 205 it is poor to adjust 2 phase of input signals automatically, the occurrence rate certain (for example being 50%) that makes trigger output 1 or 0.

More than among Shuo Ming the 3rd embodiment, use R-S trigger 216 as the trigger (causing the trigger of metastable phenomenon) of random number generation usefulness, but the invention is not restricted to this, can realize said function with in addition trigger (for example D flip-flop etc.).

Though not shown, the serial random number generator 210 of first to the 3rd above-mentioned embodiment can dispose P side by side, thereby constitutes the parallel type random number generator that does not have the P bit architecture of any mutual relationship between each random number generator 210.

Use the random number generator of above-mentioned serial type and parallel type random number generator to constitute probability generator, then can generate have homogeneity and have not regulation, correlativity and periodic desirable probability.

As mentioned above, each circuit of the present invention uses MOS transistor to constitute numeric structure, therefore tackle LSIization easily, help producing, can provide a large amount of random numbers and probability data at a high speed at an easy rate the purposes of extensive fields such as science and technology calculating, game machine, encryption.

As above explanation, according to the present invention, additional dither generative circuit on the incoming line of the trigger of generation random number, therefore the shake by input signal, enlarged the uncertain actuating range of trigger, generate easily random number, its result can realize having homogeneity and have not regulation, the generating means of correlativity and periodic more stable natural random number.

As other structure, the phase place adjustment is transformed to voltage, the threshold voltage that utilizes circuit component produces random number with this variation in voltage digitizing, therefore can realize having homogeneity and have not regulation, the generating means of correlativity and periodic more stable natural random number.

As other structures, produce random number by the metastable phenomenon of utilizing trigger, thereby can realize having homogeneity and have not regulation, the generating means of correlativity and periodic more stable natural random number.

By utilizing the random number generator of this structure, the probability generator that can realize ideal can actively participate in the hi-tech industry that scientific and technical calculating, game machine or encryption etc. have confidentiality effectively.

The 3rd form of＜invention 〉

The embodiment of the random number generator of the 3rd form of implementation of the present invention is described below with reference to the accompanying drawings.

As shown in figure 48, the random number generator 310 of first embodiment comprises trigger 301, phase place adjustment part 302 and feedback circuit 303 substantially.

Here, as above-mentioned trigger 301, can use phase differential to determine the trigger of function of the state (0 or 1) of output with the input signal (CLOCK) by being input to 2 input parts, in the present embodiment, for the signal input is used, and use has the D flip-flop shown in Figure 13 of the foregoing description of clock terminal CLK and data terminal D.

Above-mentioned phase place adjustment part 302 is by being connected in series and producing 2 delay circuits 317 of a plurality of delays outputs that are classified to increase retardation, 318 (first delays 317, second postpones 318), according to selecting this selection circuit 319 (selector switch 319) and this up-down counter 313 (the 3rd counter 313) of selecting to import of control that postpones one of output of input selection to constitute, above-mentioned first postpones the tie point (become and postpone intermediate point) of 317 and second delay 318 when first noise/phase transformer 320 is connected in the clock terminal CLk of above-mentioned trigger 301, the output of selector switch 319 is connected in data terminal D through second noise/phase transformer 321, and the rising edge time phase difference that is input to 2 input signals of trigger 301 can be adjusted arbitrarily.

Above-mentioned 2 noise/phase transformers 320, the 321st, produce shake in order to make in the above-mentioned trigger input, to be in the noise circuit synthetic of the noise-producing source 322,323 of the faint thermonoise that the circuit component (for example transistor, resistance, capacitor etc.) of state of activation produces from utilization with postponing output.Therefore, enlarge the uncertain actuating range of trigger 301, generate easily have homogeneity and have not regulation, correlativity and the periodic random number of nature fully.

This noise/phase transformer may not be additional to the CLK terminal of trigger 301 and D terminal the two, shown in the random number generator 310 as shown in figure 49, can go up additionally at a certain incoming line (being the D terminal among Figure 49) of trigger 301, obtain effect same.

Above-mentioned feedback circuit 303 is made of first counter 311, second counter 312, register 314, comparer 315 and constant setting apparatus 316.

(CLOCK number (2 * m)), second counter 312 be this appearance number of 1 (or 0) of the above-mentioned trigger output of instrumentation in cycle repeatedly at each from the predetermined cycle repeatedly of input signal CLOCK instrumentation for first counter 311.Cycle is taken into and keeps the count value of second counter 312 to register 314 repeatedly at each.When in addition, each count value is arranged in the register 314 just with 312 zero clearings of second counter.316 outputs of constant setting apparatus are used for the comparing data of the occurrence rate of set flip-flop output 1 (or 0).In the present embodiment, be redefined for (1/2 value (m) of CLOCK number (2 * m)) of above-mentioned cycle repeatedly of output.The maintenance data (n) of comparer 315 comparand registers 314 and from the comparing data (m) of constant setting apparatus 316, corresponding comparative result (n＞m) or (n=m) or (n＜m) produces relatively output.The pattern action that the 3rd counter 113 is set from the relatively output of above-mentioned comparer 315 by basis is exported this enumeration data as the selection signal of selecting circuit 319.And, as mentioned above, select the regulation inhibit signal of circuit 319 outputs by the CLOCK signal of selection signal selection.

Promptly, according to said structure, the output data (n) of the 3rd counter 313 corresponding registers 314 and from the relatively output of the output data (m) of this constant setting apparatus 316 each repeatedly the cycle carry out on/(counting (+1) for example makes progress during n＞m in action down, when n＜m, count (1) downwards), the rising edge time of CLOCK signal that is input to the data terminal D of trigger 301 from normal moveout correction makes the relatively output of comparer 15 be converged in n=m (the counting action stops (± 0) during n=m, and the phase differential of CLOCK signal is kept necessarily).Specifically, shown in Figure 14 (c), the phase difference t of rising edge that is controlled to be the rising edge of CLK signal and D signal is near 0.Thus, obtain the serial random number data OUT that 0 and 1 occurrence rate is usually kept 50% 1 bit that homogeneity is arranged in the output of trigger 301.

Be the elemental motion of random number generator 310 above, but in the present embodiment, connect initial control circuit 324 on above-mentioned first counter 311, (2 * m) are made as m=1 to the counting setting value when forcing the common action with first counter 311 from power connection to certain clock number.Thereby during power connection, can be effectively with convergence in probability 1/2, the adjustment period of can shortening phase place between.

Then second embodiment is described according to Figure 50.

Basic structure and Figure 48 of the random number generator 310 of present embodiment are same, be made of trigger 301, phase place adjustment part 302 and feedback circuit 303, but the structure of phase place adjustment part 302 are different with Figure 48.

Promptly, this structure is the 3rd counter 313, first selector 319, first to be postponed 317, second postpone 318 phase-adjusting circuits that constitute as the inching parts, each postpone output go up the additional the 3rd postpone 331, coarse regulation parts and the 4th that second selector 332 constitutes postpone 333, third selector 334 constitutes coarse regulation parts, the selection action of above-mentioned second selector 332 and third selector 334 is specified by the output of four-counter 330.Therefore, inching use first postpone that 317 and second time delay that postpones each pitch (step) of 318 and coarse regulation use the 3rd postpone the 331 and the 4th postpone time delay of 333 and compare to be set in about below 1/20.This four-counter 330 is by the relatively output control of comparer 315, and its counting action is identical with the situation of the 3rd counter 313.

The coarse regulation action and the inching action of the phase place that random number generator 310 shown in Figure 50 carries out are described below with reference to Figure 51 and table 1.In addition, the coarse regulation when Figure 51 represents the phase place adjustment and the actuating range of inching, table 1 is represented the 3rd counter 313 of this moment and the action schedule of four-counter 330.Here, the inching scope is (0～r * (g-1)), and the coarse regulation scope is (s * (h)～s * (h-1)).

In original state, the count value (SN) of the four-counter 330 that coarse regulation is used and the count value (RN) of the 3rd counter 313 that inching is used all are 0.(phase place is adjusted width tdw among Figure 51 at certain clock number forcibly with (m) of first counter 311 when the power connection by initial control circuit 324, promptly be controlled to be m=1 in 2 * (2 * g+h) clock number), therefore certain during in the 3rd counter 313 count action (+1 or ± 0 or-1) according to per 2 the clock ground of the relatively output of comparer 315.Therebetween, four-counter 330 is counted action (+1 or ± 0 or-1) according to the relatively output of comparer 315 and the state of above-mentioned the 3rd counter 313.

At first, when (1) final phase point of adjusting was arranged in the a1 of Figure 51, during power connection, (n＜m) per 2 clocks upwards count down to (g-1) from 0 in the relatively output of the 3rd counter 313 by comparer 315.

When the 3rd counter 313 upwards count down to RN=(g-1), (n＜m) and the state of the RN=(g-1) of above-mentioned the 3rd counter 313 are that condition upwards count down to (h-1) from 0 to four-counter 330, become SN=(h-2) with the relatively output of comparer 315 in per 2 clocks in next 2 clock.Here, the state of SN=(h-2) is the coarse regulation pitch location corresponding to phase settings point a1 among Figure 51, and corresponding therewith inching scope is (A) scope (0～r * (g-1)) among Figure 51.In this counting action, the state of the RN=of the 3rd counter 313 (g-1) is forced to keep under the control of initial control circuit 324.

Then the 3rd counter 313 is that RN=(g-1), four-counter 330 are under the state of SN=(h-2), (the 3rd counter 313 per 2 clocks of n＞m) are counting upwards in relatively output by comparer 315, move closer to phase settings point a1, automatically adjust phase place and make 1 occurrence rate of trigger output be converged in 1/2, finally rest on the phase place front and back of above-mentioned phase settings point a1.

(2) the final phase place of adjusting is under the situation of a2, in the original state, and SN=(0), RN=(0).The 3rd counter 313 is when RN=(0), and (n＞m) count down to (2) downwards from (0) in next 2 clock is SN=(2) the relatively output by comparer 315.Here, the state of SN=(2) is corresponding to the coarse regulation pitch location of phase settings point a2 among Figure 51 (s * 2), and the inching scope is (B) scope (0～r * (g-1)) among Figure 51.In this counting action, the state of the RN=of the 3rd counter 313 (0) is forced to keep under the control of initial control circuit 324.

Be that RN=(0), four-counter 330 are the state of SN=(2) then since the 3rd counter 313, (the 3rd counter 313 per 2 clocks of n＜m) are counting upwards in relatively output by comparer 315, move closer to phase settings point a2, automatically adjust and make 1 occurrence rate of final trigger output be converged in 1/2, rest on the phase place front and back of above-mentioned phase settings point a2.

Then (3) to adjust to phase settings point by initial control action be in the later common action of a1 or a2, as shown in table 1, the 3rd counter 313 is when RN=(0) or RN=(g-1) are in addition, and (each clock of 2 * m) Rigen counts action (+1, ± 0 ,-1) according to the relatively output of comparer 315 during the m (for example m=250) that first counter 311 is set certain.

During RN=(0), the 3rd counter 313 according to the relatively output of comparer 315 carry out (+1, ± 0, RN=(g-1)) counting action, four-counter 330 is set at-1 when the 3rd counter 313 moves to RN=(g-1).

During RN=(g-1), the 3rd counter 313 according to the relatively output of comparer 315 carry out (+1, ± 0, RN=(g-1)) counting action, four-counter 330 is set at when the 3rd counter 313 moves to RN=(0)+1.

As mentioned above, at first phase place is roughly adjusted to prescribed phases (coarse regulation), on the final phase settings point of adjusting, carried out inching afterwards.Thus, effectively carry out high-precision phase place adjustment, can carry out the phase place adjustment at a high speed by FEEDBACK CONTROL.By the coarse regulation parts are set, can obtain wide phase place with the structure that postpones pitch less and adjust width, can reduce the circuit block that constitutes phase place adjustment part 302.

Table 1

Then the 3rd embodiment is described according to Figure 52～Figure 54.

Here, Figure 53 is the figure that the occurrence number of 1 or 0 during to 1,000 output of the random number generator by having homogeneity random number is drawn and obtained, and expresses normal distribution.Figure 54 equally spaced carries out 8 parts by center reference with this normal distribution to cut apart, and is ± 0 with the center, altogether to 10 split positions, carries out the situation of+5～-5 weighting from left end in Figure 54.

When the random number generator 310 shown in Figure 52 is the comparative pattern of comparer 315 of random number generator 310 of multiple change Figure 48, in this output, connects control circuit 340 and constitute.In the present embodiment, with the comparing data of the content (n) of register 314 comparer 315 relatively as many split positions data of the normal distribution shown in Figure 54 (m+4 * k)～(m-4 * k), export which split position of the counting of above-mentioned occurrence number at once corresponding to normal distribution.

The relatively output of above-mentioned control circuit 340 by comparer 315 ((n＞m+4 * k)～(n＞(m-4 * k)) judges the weighting (5～+ 5) corresponding with the split position data, with therewith respectively the counting of correspondence be set in the 3rd counter 313.The 3rd counter 313 carries out the counting action of corresponding weighting, by the switching width (switching pitch number) of selector switch 319 control lags output.For example, when being weighted to (4), the 3rd counter 313 usefulness are once moved and are counted downwards for 4 times repeatedly, when being weighted to (+3), with once moving the counting that makes progress for 3 times repeatedly.When being weighted to (0), stop the counting action.

Like this, in this structure, near the normal distribution zone that occurrence number 0 or 1 is few (for example occurrence number is 450 or 550 among Figure 54), increase the switching width that postpones output by weighting, carry out the coarse regulation of phase place, along with near the center of normal distribution (occurrence number among Figure 54 be 500 near), reduce the switching width that postpones to export, carry out the phase place inching.Can effectively carry out the phase place adjustment thus.

More than among Shuo Ming first to the 3rd embodiment, the trigger as random number generation usefulness uses D flip-flop, but the invention is not restricted to this, can use to have the trigger of identical function therewith, as using R-S trigger etc.

Serial random number generator 310 of the present invention can dispose P side by side, thereby constitutes the parallel type random number generator of P bit architecture.

Use that the random number generator of above-mentioned serial type and parallel type random number generator can be realized having not regulation, the probability generator of correlativity and periodic high-speed high-performance.

As mentioned above, according to the present invention, undertaken in the phase place adjustment by FEEDBACK CONTROL, the phase place adjustment part is provided with coarse regulation parts and inching parts, therefore can effectively carry out the phase place adjustment, realizes the high speed that random number produces.By the coarse regulation parts are set, obtain wide phase place with little delay pitch structure and adjust width, thereby can reduce circuit block.

According to the present invention, contrast the normal distribution and the actual occurrence number of the occurrence rate of random number 0 or 1, the position of the normal distribution of corresponding corresponding occurrence number correspondence can change phase place and adjust width, thereby equally effectively carries out the phase place adjustment with above-mentioned, realizes the high speed that random number takes place.

＜the 4th form of implementation of the present invention 〉

Figure 55～Figure 67 represents the 4th form of implementation of the present invention.Below with reference to description of drawings the 4th form of implementation of the present invention.

Figure 55 is the circuit diagram of first embodiment of expression 1 bit random number generator of the present invention.

Shown in Figure 55, this 1 bit random number generator 401 is check data output types that randomizer 402, first counter 403, second counter 404, register 405 and output circuit 406 constitute, in the randomizer 402 during input sync signal, as random number data from randomizer 402 outputs 0 or 1.At this moment, the input signal of randomizer 402 is also imported in first counter 403, and 403 pairs of certain time counting numbers of first counter also output to second counter 404 and register 405.On the other hand, second counter 404 pairs of occurrence number counting and generation time logarithmic datas from the random number data of randomizer 402 outputs.And each cycle that register 405 is counted by first counter 403 keeps the inferior logarithmic data of second counter 404, and output circuit 406 is exported the inferior logarithmic data that keeps in the register 405 as the check data serial or parallel.

Therefore, in this 1 bit random number generator 401, the user does not carry out trouble and complicated statistical treatment can oneself be checked the appearance homogeneity of random number data.

Figure 56 is the circuit diagram of second embodiment of expression 1 bit random number generator of the present invention.

Shown in Figure 56, this 1 bit random number generator 424 is check signal output types that randomizer 402, first counter 403, second counter 404, register 405 and comparer 407 constitute, in the randomizer 402 during input sync signal, as random number data from randomizer 402 outputs 0 or 1.At this moment, the input signal of randomizer 402 is also imported in first counter 403,403 pairs of certain time counting numbers of first counter.On the other hand, second counter 404 pairs of occurrence number counting and generation time logarithmic datas from the random number data of randomizer 402 outputs.And each cycle that register 405 is counted by first counter 403 keeps the inferior logarithmic data of second counter 404.In addition, the data and preset upper limit comparing data and the lower limit comparing data that keep in comparer 407 comparand registers 405, data in register 405 are between upper limit comparing data and lower limit comparing data the time, the high check signal of appearance homogeneity of output expression random number data, under the situation in addition, the low check signal of appearance homogeneity of output expression random number data.

Therefore, in this 1 bit random number generator 424, the user does not carry out trouble and complicated statistical treatment can oneself be checked the appearance homogeneity of random number data.

Figure 57 is the circuit diagram of the 3rd embodiment of expression 1 bit random number generator of the present invention.

The principle of these 1 bit random number generator, 401 bases is as follows: because if the same 0 or 1 the probability then exported of the output of randomizer 402 is 1/2, so each numeral continuously probability of k appearance be (1/2) ^k, for example continuous probability that occurs identical numeral for 30 times is 1/1073741824 (promptly almost nil), therefore if continuous 30 times identical numerals occur, it is undesired then to be judged as this randomizer 2.

Promptly, shown in Figure 57, the check data output type that the comparer 409 that this 1 bit random number generator 401 is data retainer 408, XOR and the element etc. of randomizer 402, D flip-flop etc., counter 410 and output circuit 406 constitute, in the randomizer 402 during input sync signal, as random number data from randomizer 402 outputs 0 or 1.At this moment, the input signal of randomizer 402 and output signal are also imported in the data retainer 408, and data retainer 408 keeps from the random number data of the last time of randomizer 402 outputs and outputs to comparer 409.Also import the output signal of randomizer 402 in the comparer 409, comparer 409 relatively from randomizer 402 output this random number data and the random number data of data retainer 408 last time of keeping, export upwards count signal to counter 410 when the two is identical, the two is simultaneously to counter 410 output counting clear signals simultaneously.Also import the input signal of randomizer 402 then in the counter 410, counter 410 outputs to output circuit 406 with these data, and output circuit 406 is exported these data successively as the check data serial or parallel ground of same signal length.

Therefore, in this 1 bit random number generator 401, by test the easily statistical treatment of homogeneity of random number of the check data of same signal length of output.

Figure 58 is the circuit diagram of the 4th embodiment of expression 1 bit random number generator of the present invention.

Shown in Figure 58, the check data output type that second comparer 413 of first comparer 411, counter 410, register 412, XOR and the element etc. of data retainer 408, XOR and element etc. that this 1 bit random number generator 401 is randomizer 402, D flip-flop etc., control circuit 414 and output circuit 415 constitute, in the randomizer 402 during input sync signal, as random number data from randomizer 402 outputs 0 or 1.At this moment, the input signal of randomizer 402 and output signal are also imported in the data retainer 408, and data retainer 408 keeps from the random number data of the last time of randomizer 402 outputs and outputs to first comparer 411.Also import the output signal of randomizer 402 in first comparer 411, first comparer 411 relatively from randomizer 402 output this random number data and the random number data of data retainer 408 last time of keeping, export upwards count signal to counter 410 when the two is identical, the two is simultaneously to counter 410 output counting clear signals simultaneously.Also import the input signal of randomizer 402 then in the counter 410, counter 410 outputs to second comparer 413 with these data, the output data of the data sum counter 410 of second comparer, 413 comparand registers 412, when the latter is bigger than the former, when control circuit 414 output datas rewrite signal, in addition to control circuit 414 output data holding signals.When control circuit 414 is controlled to when receiving the data rewrite signal output data with counter 410 and writes in the register 412, keep the data of register 412 when receiving the data holding signal, output circuit 415 is exported the data that keep in the register 412 successively as the check data serial or parallel ground of the longest same signal length.

Therefore, in this 1 bit random number generator 401, by test the easily statistical treatment of homogeneity of random number of the check data of the longest same signal length of output.

Figure 59 is the circuit diagram of the 5th embodiment of expression 1 bit random number generator of the present invention.

Shown in Figure 59, the check signal output type that the 3rd comparer 416 of second comparer 413, control circuit 414 and the XOR and the element etc. of first comparer 411, counter 410, register 412, XOR and the element etc. of data retainer 408, XOR and element etc. that this 1 bit random number generator 524 is randomizer 402, D flip-flop etc. constitutes, in the randomizer 402 during input sync signal, as random number data from randomizer 402 outputs 0 or 1.At this moment, the input signal of randomizer 402 and output signal are also imported in the data retainer 408, and data retainer 408 keeps from the random number data of the last time of randomizer 402 outputs and outputs to first comparer 411.Also import the output signal of randomizer 402 in first comparer 411, first comparer 411 relatively from randomizer 402 output this random number data and the random number data of data retainer 408 last time of keeping, export upwards count signal to counter 410 when the two is identical, the two is simultaneously to counter 410 output counting clear signals simultaneously.Also import the input signal of randomizer 402 then in the counter 410, counter 410 outputs to second comparer 413 with these data, the output data of the data sum counter 410 of second comparer, 413 comparand registers 412, when the latter is bigger than the former, when control circuit 414 output datas rewrite signal, in addition to control circuit 414 output data holding signals.When control circuit 414 is controlled to when receiving the data rewrite signal output data with counter 410 and writes in the register 412, the data of maintenance register 412 when reception data holding signal, data that keep in the 3rd comparer 416 comparand registers 412 and predetermined comparing data are also exported the check signal of the longest same signal length successively.

Therefore, in this 1 bit random number generator 424, the user does not carry out trouble and complicated statistical treatment can oneself be checked the appearance homogeneity of random number data.

Figure 60 is the circuit diagram of the 6th embodiment of expression 1 bit random number generator of the present invention.

Shown in Figure 60, the check data output type that the comparer 409 that this 1 bit random number generator 401 is data retainer 408, XOR and the element etc. of randomizer 402, D flip-flop etc., first counter 417, second counter 418, demoder 419, a plurality of (n) the 3rd counter 420, a plurality of (n) register 421 and control circuit 422 constitute, in the randomizer 402 during input sync signal, as random number data from randomizer 402 outputs 0 or 1.At this moment, to (1～n) occurrence rate is counted, and decides number of times by each of first counter, 417 countings and writes register 421, exports the distribution of each same signal length successively by each same signal length of certain number of times of first counter 417 counting.

That is, the input signal of randomizer 402 and output signal are also imported in the data retainer 408, and data retainer 408 keeps from the random number data of the last time of randomizer 402 outputs and outputs to comparer 409.Also import the output signal of randomizer 402 in the comparer 409, comparer 409 relatively from randomizer 402 output this random number data and the random number data of data retainer 408 last time of keeping, export upwards count signal to control circuit 422 when the two is identical, the two is simultaneously to control circuit 422 output counting clear signals simultaneously.On the other hand, the input signal of randomizer 402 is also imported in first counter 417 and the control circuit 422, and first counter, the 417 certain number of times of counting also output to control circuit 422.In addition, the input signal of randomizer 402 is also imported in second counter 418, demoder 419 upwards counted and outputs to by second counter 418 when comparer 409 receptions make progress count signal, count during simultaneously, from comparer 409 count pick up clear signals and remove and output to demoder 419.The output data of the demoder that receives 419 decodings second counter 418 also outputs to each of the 3rd counter 420 by each signal length, and 420 pairs of these output datas countings of individual count device also output in each register 421.Then, each register 421 is under the control of control circuit 422, and the signal serial or parallel of deciding number of times according to each of the output data of comparer 409 and first counter, 417 countings is exported the check data of same signal length successively.

Therefore, in this 1 bit random number generator 424, by test the easily statistical treatment of homogeneity of random number of each counting (check data) of output.

Figure 61 represents the circuit diagram of the 7th embodiment of 1 bit random number generator of the present invention.

Shown in Figure 61, the comparer 409 that this 1 bit random number generator 1 is data retainer 408, XOR and the element etc. of randomizer 402, D flip-flop etc., first counter 417, second counter 418, demoder 419, a plurality of (n) the 3rd counter 420, a plurality of (n) register 421 and control circuit 422 and the check data output type of selecting circuit 423 to constitute, in the randomizer 402 during input sync signal, as random number data from randomizer 402 outputs 0 or 1.At this moment, (1～n) occurrence rate is counted to each the same signal length by certain number of times of first counter 417 counting, decide number of times by each of first counter 417 counting and write register 421, successively to the distribution of selection circuit 423 each same signal length of output of selecting from the selection data of outside.

That is, the input signal of randomizer 402 and output signal are also imported in the data retainer 408, and data retainer 408 keeps from the random number data of the last time of randomizer 402 outputs and outputs to comparer 409.Also import the output signal of randomizer 402 in the comparer 409, comparer 409 relatively from randomizer 402 output this random number data and the random number data of data retainer 408 last time of keeping, export upwards count signal to control circuit 422 when the two is identical, the two is simultaneously to control circuit 422 output counting clear signals simultaneously.On the other hand, the input signal of randomizer 402 is also imported in first counter 417 and the control circuit 422, and first counter, the 417 certain number of times of counting also output to control circuit 422.In addition, the input signal of randomizer 402 is also imported in second counter 418, demoder 419 upwards counted and outputs to by second counter 418 when comparer 409 receptions make progress count signal, count during simultaneously, from comparer 409 count pick up clear signals and remove and output to demoder 419.The output data of the demoder that receives 419 decodings second counter 418 also outputs to each of the 3rd counter 420 by each signal length, and 420 pairs of these output datas countings of individual count device also output in each register 421.Then, each register 421 is decided the signal of number of times successively to the check data of selecting circuit 423 serial or parallels output same signal length according to the output data of comparer 409 and each of first counter, 417 countings under the control of control circuit 422.Import when selecting data from the outside in the selection circuit 423, select circuit 423 to select the output data of suitable selection of data and output register 421 according to this.

Therefore, in this 1 bit random number generator 401, by test the easily statistical treatment of homogeneity of random number of the distributed data of same signal length of output.

Figure 62 represents the circuit diagram of first embodiment of many bits random number generator of the present invention.

Shown in Figure 62, this many bits random number generator 425 is to connect the 1 bit random number generator 401 of a plurality of (n) above-mentioned check data output type side by side and it is added the structure of selecting circuit 426, select to import when selecting data from the outside in the circuit 426, select circuit 426 specially to select to export the check data of exporting from 1 bit random number generator 401 according to the every ratio of these selection data.

Therefore in this many bits random number generator 425, by the homogeneity check data of output, the statistical treatment of the homogeneity of the random number of testing easily.

Figure 63 represents the circuit diagram of second embodiment of many bits random number generator of the present invention.

Shown in Figure 63, this many bits random number generator 425 is to connect the 1 bit random number generator 424 of a plurality of (n) above-mentioned check signal output type side by side and it is added the structure of selecting circuit 427, select to import when selecting data from the outside in the circuit 427, select circuit 427 specially to select to export the check signal of exporting from 1 bit random number generator 424 according to the every ratio of these selection data.

Therefore in this many bits random number generator 425, the user does not carry out trouble and complicated statistical treatment can oneself be checked the appearance homogeneity of random number data.

Figure 64 represents the circuit diagram of first embodiment of probability generator of the present invention.

Shown in Figure 64, this probability generator 430 is made of 1 bit random number generator 401, shift register 431, counter 432, register 433 and the comparer 434 of above-mentioned check data output type, be input to the shift register 431 from the random number data of 1 bit random number generator, 401 outputs, shift register 431 is transformed to this random number data parallel data and outputs to register 433 from serial data.On the other hand, the input signal of 1 bit random number generator 401 also is input in the counter 432, and the bit length counting of 432 pairs of certain parallel datas of counter also outputs to register 433.Like this, register 433 is pressed the parallel data of each cycle maintenance shift register 431 of counter 432 countings.Afterwards, data that keep in comparer 434 comparand registers 433 and predetermined probability upper limit data and probability lower limit data, data in register 433 are time output " hitting " between probability upper limit data and probability lower limit data, the probability signal of output " departing from " under situation in addition.

Therefore in this probability generator 430, the user does not carry out trouble and complicated statistical treatment can be checked the appearance homogeneity of random number data, thereby estimates the reliability of probability easily.

Figure 65 represents the circuit diagram of second embodiment of probability generator of the present invention.

Shown in Figure 65, this probability generator 430 is made of 1 bit random number generator 424, shift register 431, counter 432, register 433 and the comparer 434 of above-mentioned check signal output type, be input to the shift register 431 from the random number data of 1 bit random number generator, 424 outputs, shift register 431 is transformed to this random number data parallel data and outputs to register 433 from serial data.On the other hand, the input signal of 1 bit random number generator 424 also is input in the counter 432, and the bit length counting of 432 pairs of certain parallel datas of counter also outputs to register 433.Like this, register 433 is pressed the parallel data of each cycle maintenance shift register 431 of counter 432 countings.Afterwards, data that keep in comparer 434 comparand registers 433 and predetermined probability upper limit data and probability lower limit data, data in register 433 are time output " hitting " between probability upper limit data and probability lower limit data, the probability signal of output " departing from " under situation in addition.

Therefore in this probability generator 430, the user does not carry out trouble and complicated statistical treatment can be checked the appearance homogeneity of random number data, thereby estimates the reliability of probability easily.

Figure 66 represents the circuit diagram of the 3rd embodiment of probability generator of the present invention.Figure 67 represents the circuit diagram of the 4th embodiment of probability generator of the present invention.

Shown in Figure 66 and Figure 67, these probability generators 430 are made of above-mentioned many bits random number generator 425 and comparer 435, be input to the comparer 435 from the random number data (parallel data) of many bits random number generator 425 outputs, comparer 435 is these random number datas and predetermined probability upper limit data and probability lower limit data relatively, output " hitting " when random number data is between probability upper limit data and probability lower limit data, the probability signal of output " departing from " under situation in addition.

Therefore in this probability generator 430, the user does not carry out trouble and complicated statistical treatment can be checked the appearance homogeneity of random number data, thereby estimates the reliability of probability easily.

As mentioned above, according to the abovementioned embodiments of the present invention, can oneself check the appearance homogeneity of random number data, the user does not need to carry out statistical treatment, thereby can provide the appearance homogeneity of checking random number data like a cork also can improve 1 bit random number generator of reliability.

Can oneself check the appearance homogeneity of random number data, the user does not need to carry out statistical treatment, thereby can provide the appearance homogeneity of checking random number data like a cork also can improve many bits random number generator of reliability.

In addition, the invention of technical scheme 51 in according to the present invention, can oneself check the appearance homogeneity of random number data, the user does not need to carry out statistical treatment, thereby can provide the appearance homogeneity of checking random number data like a cork also can improve the probability generator of reliability.

Claims (13)

1. random number generator is characterized in that comprising:

Trigger, correspondence are input to the phase differential of the signal of 2 input parts and determine output state 0 or 1;

Delay portion possesses by above-mentioned input signal being postponed several grades of delay circuits of exporting and corresponding selection and imports the selection circuit of one of selection delay output, and makes 2 input signals produce phase differential; With

Feedback circuit wherein, has:

First counter in the cycle repeatedly of the regulation of the above-mentioned input signal of instrumentation,

Instrumentation each repeatedly second counter of 0 or 1 of above-mentioned trigger output appearance number in the cycle,

By cycle repeatedly keep the instrumentation output of this second counter register,

Generation be used to set above-mentioned trigger output 0 or 1 occurrence rate comparing data the constant setting apparatus,

The comparer of the output data of more above-mentioned register and the size of above-mentioned comparing data,

Produce the up-down counter of the selection signal of above-mentioned selection circuit, also according to the relatively output of this comparer

By above-mentioned input signal control above-mentioned phase differential so that 0 or 1 occurrence rate of trigger output in accordance with regulations repeatedly the cycle certain.

2. random number generator according to claim 1, it is characterized in that as the setting data in the cycle of setting in above-mentioned first counter repeatedly and the comparing data of above-mentioned comparer, use the random number of above-mentioned trigger output or encrypt the random number that this random number constitutes.

3. random number generator according to claim 1, it is characterized in that having auxiliary random number generator with the described random number generator same structure of claim 1, as the setting data in the cycle of setting in above-mentioned first counter repeatedly and the comparing data of above-mentioned comparer, the random number of using above-mentioned auxiliary random number generator to produce.

4. random number generator according to claim 1, it is characterized in that having auxiliary random number generator with the described random number generator same structure of claim 1, as the setting data in the cycle of setting in above-mentioned first counter repeatedly and the comparing data of above-mentioned comparer, use random number that above-mentioned auxiliary random number generator produces and the random number of the random number that above-mentioned random number generator produces being encrypted formation.

5. random number generator according to claim 1 is characterized in that constituting to the additional waveform shaping circuit of the input signal cable of above-mentioned trigger.

6. random number generator according to claim 1 is characterized in that having the initial control circuit that the comparing data of above-mentioned comparer is set at specified time limit 0 when energized.

7. random number generator according to claim 1 is characterized in that as above-mentioned trigger, uses D flip-flop or R-S trigger.

8. random number generator according to claim 1 is characterized in that disposing side by side the described random number generator of a plurality of claims 1.

9. a probability generator is characterized in that having the described random number generator of claim 1.

10. random number generator as claimed in claim 1 is characterized in that,

The additional shake generative circuit that constitutes by noise-producing source, the amplifying circuit that amplifies this noise, the mixting circuit that input signal produced shake by this amplifications noise signal on above-mentioned trigger incoming line.

11. random number generator according to claim 10 is characterized in that additional above-mentioned shake generative circuit on two incoming lines of above-mentioned trigger.

12. random number generator according to claim 10 is characterized in that additional above-mentioned shake generative circuit on some incoming lines of above-mentioned trigger, the integrating circuit that the additional delay time adjustment is used on another incoming line.

13. random number generator according to claim 10 is characterized in that having the latching sections by the output of the above-mentioned shake generative circuit of the breech lock of cycle repeatedly of above-mentioned input signal.

Images