CN107957543A - A kind of test circuit for testing randomizer - Google Patents
A kind of test circuit for testing randomizer Download PDFInfo
- Publication number
- CN107957543A CN107957543A CN201711091415.4A CN201711091415A CN107957543A CN 107957543 A CN107957543 A CN 107957543A CN 201711091415 A CN201711091415 A CN 201711091415A CN 107957543 A CN107957543 A CN 107957543A
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- China
- Prior art keywords
- randomizer
- random number
- register
- processor
- logic gate
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Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/58—Random or pseudo-random number generators
- G06F7/588—Random number generators, i.e. based on natural stochastic processes
Abstract
The present invention provides a kind of test circuit for testing randomizer, randomizer produces first random number and stores it in first register, then the test pattern of random number generator circuit is enabled, randomizer produces one group of random number and stores it in time register again at the same time, then the random number being stored in first register and the random number being stored in time register are made comparisons, compare end, using the id signal whether the output signal of randomizer test circuit is abnormal as randomizer work is judged.Test method of the present invention possesses the ability continuously checked, and is realized with the mode of hardware, makes it have function-stable and possesses tamper-resistance；The present invention can realize the real-time testing to random number caused by random number generator, ensure, when randomizer operation irregularity, to be found in time, prevent the random number of mistake from being used by system.
Description
Technical field
The invention belongs to integrated circuit functional test field, more particularly, to a kind of test electricity for testing randomizer
Road.
Background technology
Randomizer produces the data (such as random digit) with random attribute.Randomizer generally has two
Kind operating mode：1. the random number non-correlation of the randomizer with uncertainty, i.e. its tandem generation；2. tool
There is deterministic randomizer, i.e. the random number of its tandem generation has correlation, but this correlation is usually great
Concealment is generally used for test purpose in order to provide enough random attributes, this operating mode.Since randomizer produces
The random attribute of data, causes to be difficult to judge that it is whether normal that randomizer works by the random data of generation.Therefore,
For most of application scenarios, it can only assume that randomizer work is normal, unless there occurs obvious exception.
The presentation of one of which operation irregularity is, " obstruction " phenomenon occurs in randomizer, i.e. the repeatedly random data of the output phase together.
Check the phenomenon of this randomizer operation irregularity, randomizer first produces one group of random data, Ran Houzai
The secondary random data for producing one group of same bit-width, then two groups of random data are compared, if two groups of random data not phase
Together, illustrate that " obstruction " phenomenon does not occur for randomizer；If identical, " obstruction " phenomenon, randomizer occurs
Operation irregularity.
Due to the random attribute of data produced by randomizer, thus pass through generated random data judge with
Whether the work of machine number generator is normally extremely difficult.U.S.'s connection of National Institute of Standards and Technology (NIST) issue
Nation criteria for information processing 140-2 (FIPS PUB 140-2) provides a kind of test mode, and FIPS PUB 140-2 regulations are random
The each group of random data that number generator is generated is all necessarily different from the random data of previous group generation, i.e., identical random number
According to will not continuously generate twice.Standard provides that randomizer must generate new random data every time, i.e., it is newly-generated with
Machine data are necessarily different from the upper one group of random data being sequentially generated.If continuous two groups of random data are identical, illustrate this with
Machine number generator operation irregularity.
In practical applications, randomizer provides the data with abundant randomness for system.This data are in reality
Border application includes, such as, the data such as key, authorization identifying information and integrated authentication information in encryption system.When with
When random data caused by machine number generator is used for use above, it is necessary to assure randomizer is in normal work shape
State.The randomness of the result that analysis randomizer is exported completely is difficult, and a kind of simple determination methods are exactly to compare
Whether the random number that more random number generator generates twice in succession is identical.If they differ, we can assume that random number
Generator work is normal.This test method possesses the ability continuously checked.And realized with the mode of hardware, make its tool
Functional stabilization and possesses tamper-resistance.Therefore, based on hardware mode realize and possess follow-on test ability it is random
Number generator test circuit has a extensive future.
The content of the invention
In view of this, the present invention is directed to propose a kind of test circuit for testing randomizer, is sent out with detecting random number
Whether raw device is abnormal.
To reach above-mentioned purpose, the technical proposal of the invention is realized in this way：
A kind of test circuit for testing randomizer, including randomizer subsystem and processor subsystem；
The randomizer subsystem includes randomizer, first register, secondary register and comparator, institute
State time register and also include gate, the processor subsystem includes processor and memory；
The processor connects randomizer, for asking randomizer to produce one group of random number, it is described with
Machine number generator exports connection processing device, is used for transmission the random number of its generation, and the randomizer output is also connected with head
Register, the head registers connect time register by gate, and the gate is also connected with randomizer；
The head registers connect two input terminals of comparator, the output of the comparator with the output terminal of time register
End is directly connected to processor, or an input terminal of the output terminal connection combinational logic gate of comparator, the combinational logic gate
Another input terminal connection sequential logic gate output terminal, the input terminal connection memory and processing of the sequential logic gate
Device, the output terminal connection processing device of the combinational logic gate；
The head registers, secondary register, memory are also connected with processor.
Further, the randomizer subsystem further includes combinational logic gate and sequential logic gate.
Further, the combinational logic gate includes OR gate.
Further, the sequential logic gate includes d type flip flop.
Relative to the prior art, a kind of test circuit for testing randomizer of the present invention has following excellent
Gesture：
(1) test method of the present invention possesses the ability continuously checked, and is realized with the mode of hardware, makes its tool
Functional stabilization and possesses tamper-resistance；
(2) present invention can realize the real-time testing to random number caused by random number generator, and random number is worked as in guarantee
It during generator operation irregularity, can in time be found, prevent the random number of mistake from being used by system.
Brief description of the drawings
The attached drawing for forming the part of the present invention is used for providing a further understanding of the present invention, schematic reality of the invention
Apply example and its explanation is used to explain the present invention, do not form inappropriate limitation of the present invention.In the accompanying drawings：
Fig. 1 is a kind of test circuit schematic diagram of test randomizer described in the embodiment of the present invention.
Description of reference numerals：
101- randomizer subsystems；102- processor subsystems；103- randomizers；The first deposits of 104-
Device；105- register；106- comparators；107- sequential logic gates；108- combinational logic gates；109- processors；110- is stored
Device.
Embodiment
It should be noted that in the case where there is no conflict, the feature in embodiment and embodiment in the present invention can phase
Mutually combination.
In the description of the present invention, it is to be understood that term " " center ", " longitudinal direction ", " transverse direction ", " on ", " under ",
The orientation or position relationship of the instruction such as "front", "rear", "left", "right", " vertical ", " level ", " top ", " bottom ", " interior ", " outer " are
Based on orientation shown in the drawings or position relationship, it is for only for ease of the description present invention and simplifies description, rather than instruction or dark
Show that the device of meaning or element there must be specific orientation, with specific azimuth configuration and operation, thus it is it is not intended that right
The limitation of the present invention.In addition, term " first ", " second " etc. are only used for description purpose, and it is not intended that instruction or hint phase
To importance or the implicit quantity for indicating indicated technical characteristic.Thus, the feature for defining " first ", " second " etc. can
To express or implicitly include one or more this feature.In the description of the present invention, unless otherwise indicated, " multiple "
It is meant that two or more.
In the description of the present invention, it is necessary to illustrate, unless otherwise clearly defined and limited, term " installation ", " phase
Even ", " connection " should be interpreted broadly, for example, it may be being fixedly connected or being detachably connected, or be integrally connected；Can
To be mechanical connection or be electrically connected；It can be directly connected, can also be indirectly connected by intermediary, Ke Yishi
Connection inside two elements.For the ordinary skill in the art, above-mentioned term can be understood by concrete condition
Concrete meaning in the present invention.
Below with reference to the accompanying drawings and the present invention will be described in detail in conjunction with the embodiments.
In use, random number caused by random number generator should can so ensure to work as by real-time testing
During randomizer operation irregularity, it can prevent the random number of mistake from being used by system in time by software discovery.Concrete application
Into encryption system, it is necessary to complete following operate：First when the operation such as circuit completes power initiation, initialization or circuit are restarted
Afterwards, randomizer produces one group of random data, this group of random data cannot use by system, but should be by
Store and be compared for the next group of random data produced with order.Randomizer often produces one group of random data
It will be compared with upper one group of random data, if two groups of random data are identical, failure signal is compared in generation, shows random
Number generator operation irregularity.The mode of operation between specific each component is described as follows as shown in Figure 1：One kind tests random number
The test circuit of device, including randomizer subsystem 101 and processor subsystem 102；The randomizer subsystem
System 101 includes randomizer 103, first register 104, secondary register 105 and comparator 106, the secondary register 105
Gate is also included, the processor subsystem 102 includes processor 109 and memory 110.
The output of processor 109 connects randomizer 103 by connecting line, for asking randomizer 103 to produce
Raw one group of random number.The output of randomizer 103 passes through connecting line connection processing device 109, is used for transmission the random of its generation
Number, the output of randomizer 103 connect first register 104 by connecting line and connect time register by gate
105.So in the normal mode of operation, random number is not only supplied to processor 109 caused by randomizer 103
(processor 109 by this value store in the memory 110), can also be stored in first register 104, and can selectivity storage
In secondary register 105.Gate is used to select which group random number to be stored in time register 105, wherein passing through company all the way
Wiring connects tandom number generator 103, and in addition connecting first register 104 by connecting line all the way (is stored in first register 104
A upper randomizer 103 generation random number).By connection, first register 104 and time register 105 can be complete
Into pile line operation, i.e., caused random number 1 is locked by connecting line in first rising edge clock randomizer 103
There are in first register 104, random number 1 is latched in by secondary post by connecting line in second rising edge clock head register 104
In storage 105, and the random number 2 from randomizer 103 latching, random number 1 is stored in from register 105 at this time,
Random number 2 is stored in first register 104.
Two input terminals of comparator 106 are connected secondary by the first register 104 of connecting line connection with by connecting line respectively
Register 105.Compare the random number that two input terminals obtain, if the same compare failure, comparator 106 exports one at this time
Compare failure signal, otherwise relatively success.Processor 109 can be directly connected to by connecting line by comparing failure signal, can also
An input terminal as combinational logic gate 108 as shown in Figure 1.Another input terminal of combinational logic gate 108 passes through connecting line
Connect the output of sequential logic gate 107.Combinational logic gate 108, which can produce, compares failure signal, and by connecting line input everywhere
Manage in device 109.This comparison failure signal has two ways：1. failure signal is compared in the output of comparator 106；2. sequential is patrolled
Collect door 107 and directly write 1 enabled combinational logic gate 108 and produce and compare failure signal, for example this side can be used for test purpose
Formula.Processor 109 connects sequential logic gate 107 and memory 110 by storing bus.The storage mapping of processor 109 includes
Sequential logic gate 107 and memory 110, so when meeting a storage address mapping, memory 109 can be total by storing
Line read-write sequence logic gate 107.
One input signal of first register 104 can be connected to processor 109 by connecting line, and this structure can make
One user defined value is write first register 104 by processor 109.This structure can test first register 104, secondary register
105th, whether the small circuit that comparator 106 is formed, which can normally produce, is compared failure signal, is specifically described as：Subsystem 101
By two clock edges, random number 1 and random number 2 are sequentially written in time register 105 and first register 104 respectively, and two
A random number is all read by processor 109 by connecting line and is stored in memory 110, and processor 109 leads to random number 1 at this time
Cross connecting line and write in head registers 104 random number 2 for substituting and being stored in first register 104, so first register 104 is posted with secondary
Random number 1 is all store in storage 105, so comparator 106, which should certainly will produce, compares failure signal, if more unsuccessfully believed
Explanation circuit existing defects number are not produced.One input signal of secondary register 105 can be connected to processor by connecting line
109, this structure can equally make processor 109 by a user defined value write-in time register 105.This structure equally may be used
Whether the small circuit formed with the first register 104 of test, secondary register 105, comparator 106, which can normally produce, is compared failure
Signal.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
With within principle, any modification, equivalent replacement, improvement and so on, should all be included in the protection scope of the present invention god.
Claims (4)
- A kind of 1. test circuit for testing randomizer, it is characterised in that：Including randomizer subsystem and processing Device subsystem；The randomizer subsystem includes randomizer, first register, secondary register and comparator, described secondary Register also includes gate, and the processor subsystem includes processor and memory,The processor connects randomizer, for asking randomizer to produce one group of random number, the random number Generator exports connection processing device, is used for transmission the random number of its generation, and the randomizer output is also connected with first deposit Device, the head registers connect time register by gate, and the gate is also connected with randomizer；The head registers connect two input terminals of comparator with the output terminal of time register, and the output terminal of the comparator is straight Connect processor in succession, or an input terminal of the output terminal connection combinational logic gate of comparator, the combinational logic gate it is another The output terminal of one input terminal connection sequential logic gate, the input terminal connection memory and processor of the sequential logic gate, institute State the output terminal connection processing device of combinational logic gate；The head registers, secondary register, memory are also connected with processor.
- A kind of 2. test circuit for testing randomizer according to claim 1, it is characterised in that：The random number Generator subsystem further includes combinational logic gate and sequential logic gate.
- A kind of 3. test circuit for testing randomizer according to claim 2, it is characterised in that：The combination is patrolled Collecting door includes OR gate.
- A kind of 4. test circuit for testing randomizer according to claim 2, it is characterised in that：The sequential is patrolled Collecting door includes d type flip flop.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711091415.4A CN107957543A (en) | 2017-11-08 | 2017-11-08 | A kind of test circuit for testing randomizer |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711091415.4A CN107957543A (en) | 2017-11-08 | 2017-11-08 | A kind of test circuit for testing randomizer |
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| CN107957543A true CN107957543A (en) | 2018-04-24 |
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| CN201711091415.4A Pending CN107957543A (en) | 2017-11-08 | 2017-11-08 | A kind of test circuit for testing randomizer |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109120430A (en) * | 2018-06-26 | 2019-01-01 | 天津鼎成高新技术产业有限公司 | A method of guaranteeing data communication reliability |
| CN113632063A (en) * | 2018-12-27 | 2021-11-09 | 智能Ic卡公司 | Device and method for testing sequences generated by a random number generator |
| CN114968689A (en) * | 2022-08-01 | 2022-08-30 | 北京数字光芯集成电路设计有限公司 | FPGA device, MIPI protocol layer testing device and method based on FPGA device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1397871A (en) * | 2001-07-17 | 2003-02-19 | 富士电气化学株式会社 | Random number generator and probability generator |
| US20070011533A1 (en) * | 2005-05-27 | 2007-01-11 | Yonsei University | Method and apparatus for reducing number of transitions generated by linear feedback shift register |
| US20100031105A1 (en) * | 2008-07-30 | 2010-02-04 | Anritsu Corporation | Random error signal generator |
| CN102231286A (en) * | 2009-10-08 | 2011-11-02 | 鸿富锦精密工业（深圳）有限公司 | Test method of DRAM (dynamic random access memory) |
-
2017
- 2017-11-08 CN CN201711091415.4A patent/CN107957543A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1397871A (en) * | 2001-07-17 | 2003-02-19 | 富士电气化学株式会社 | Random number generator and probability generator |
| US20070011533A1 (en) * | 2005-05-27 | 2007-01-11 | Yonsei University | Method and apparatus for reducing number of transitions generated by linear feedback shift register |
| US20100031105A1 (en) * | 2008-07-30 | 2010-02-04 | Anritsu Corporation | Random error signal generator |
| CN102231286A (en) * | 2009-10-08 | 2011-11-02 | 鸿富锦精密工业（深圳）有限公司 | Test method of DRAM (dynamic random access memory) |
Non-Patent Citations (1)
| Title |
|---|
| 赵海英: "随机数发生器随机性检测系统的设计与实现", 《中国优秀硕士学位论文全文数据库 信息科技辑》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109120430A (en) * | 2018-06-26 | 2019-01-01 | 天津鼎成高新技术产业有限公司 | A method of guaranteeing data communication reliability |
| CN113632063A (en) * | 2018-12-27 | 2021-11-09 | 智能Ic卡公司 | Device and method for testing sequences generated by a random number generator |
| CN114968689A (en) * | 2022-08-01 | 2022-08-30 | 北京数字光芯集成电路设计有限公司 | FPGA device, MIPI protocol layer testing device and method based on FPGA device |
| CN114968689B (en) * | 2022-08-01 | 2022-11-01 | 北京数字光芯集成电路设计有限公司 | FPGA device, MIPI protocol layer testing device and method based on FPGA device |
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Application publication date: 20180424 |