JP3487299B2 - Random number generator and probability generator - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a random number generator suitable for use in scientific and technological calculations, game machines, encryption processing, etc., and a probability generator constructed using this random number generator. is there.

[0002]

2. Description of the Related Art The use of random numbers is indispensable for advanced scientific and technological calculations, game machines, encryption processes, etc., and in recent years, uniformity (probability value and appearance rate of random numbers do not differ) Having and regularity of random number appearance, correlation before and after,
There is an increasing demand for high-performance natural random number (true random number) generators and probability generators that do not have periodicity.

As the above-mentioned natural random number / probability generator, for example, one using a random pulse obtained by utilizing weak radiation, thermal noise of a resistor or diode, or fluctuation of a crystal oscillator is known. is there.

[0004]

By the way, in the conventional random number / probability generating circuit using the random pulse based on the above-mentioned natural phenomenon, the random pulse generation source is
Since many analog elements such as signal amplifiers, waveform shaping, and uniformity optimization circuits are included, the circuit scale is large and complicated, and it is difficult to mount them as an integrated logic LSI. It is extremely disadvantageous for application to ultra-compact and thin high-tech devices such as IC cards, which are expected to increase in demand in the future.
Since it is difficult to convert to I, there is a problem that the productivity is poor and the cost is high.

The present invention solves the above problems of the prior art,
Realizes small size and thinness suitable for LSI mounting and excellent productivity, and also in terms of performance, uniformity, regularity, correlation,
It is an object of the present invention to provide a high-performance random number generator and probability generator that do not cause problems such as periodicity.

[0006]

A D-type flip-flop is known as a flip-flop whose output state (1 or 0) is determined according to the phase difference between signals input to two input sections. As shown in FIG. 34, this D-type flip-flop has a clock terminal C serving as an input section.
It has LK and data terminal D, and outputs Q depending on the state (0 or 1) of data terminal D at the rising edge of the CLK input signal.
This is a so-called edge-triggered flip-flop in which the state of / Q (/ Q: inverted output of Q) is fixed. Here, FIG.
When the difference (phase difference) Δt between the rising time of the CLK signal and the rising time of the D signal is brought closer to 0 from the state of 5 (a) or FIG. 35 (b), as shown in FIG. There is a range of phase difference in which the flip-flop outputs Qn and / Qn are uncertain. Then, the uncertain operation range of the flip-flop expands as the jitter of the input signal increases, which makes it easier to generate random numbers.

The present invention increases the jitter of the input signal and positively utilizes the uncertain operation of the flip-flop at that time to generate natural random numbers.

That is, the random number generator according to claim 1 automatically adjusts the phase difference between two input signals input to the flip-flop so that the appearance rate of 1 or 0 of the flip-flop output becomes constant. In the random number generator described above, a noise source, an amplifier circuit that amplifies the noise, and a mixer circuit that causes jitter in the input signal based on the clock signal due to the amplified noise signal are provided in the input line of the flip-flop. It is configured by adding a configured jitter generation circuit.

A random number generator according to a second aspect of the present invention is
It is configured by adding the jitter generation circuit to both input lines of the flip-flop.

A random number generator according to a third aspect of the present invention is
It is configured by adding the jitter generating circuit to one of the input lines of the flip-flop and adding an integrating circuit for delay time correction to the other input line.

Here, in the configurations according to the first to third aspects, the jitter occurs in the input signal input to the flip-flop, and the uncertain operation range of the flip-flop expands. As a result, it becomes possible to easily generate a more complete natural random number that has uniformity and does not have regularity, correlation, or periodicity.

Further, the random number generator according to claim 4 is
It is configured by adding latch means for latching the output of the jitter generating circuit at each repeating cycle of the input signal. With this configuration, one input signal can be obtained in one random number generation, and the random number generation operation is stable.

A random number generator according to a fifth aspect of the present invention is
In a random number generator in which a phase difference between two input signals is automatically adjusted so that an appearance rate of 1 or 0 in a flip-flop output becomes constant, the two input signals are connected to a data input line of the flip-flop. It is configured by adding a phase-voltage conversion circuit that converts the phase difference of 1 to voltage. In this configuration, a voltage substantially equal to the threshold voltage of the semiconductor element (for example, the buffer in FIG. 25) connected to the phase-voltage conversion circuit is generated at the output, and the voltage of 1 or 0 of the flip-flop output is generated. The phase difference between the two input signals (that is, the output of the phase-voltage conversion circuit) is automatically adjusted so that the appearance rate becomes constant.

A random number generator according to a sixth aspect of the present invention is
The phase-voltage conversion circuit is configured by adding enable means that operates only when the operation is permitted. In this configuration, by issuing the operation permission signal only when a random number is needed,
The active period of the circuit can be freely limited, so that the power consumption can be reduced.

A random number generator according to a seventh aspect is
To the output of the phase-voltage conversion circuit, a jitter generation circuit including a noise generation source, an amplification circuit that amplifies the noise, and a mixer circuit that causes a jitter in the input signal by the amplified noise signal is added. Composed. In this configuration, the uncertainties of the probability that 1 or 0 of the flip-flop output appears will be positively increased. As a result, it becomes possible to easily generate a more complete natural random number that has uniformity and does not have regularity, correlation, or periodicity.

The random number generator according to claim 8 is:
The jitter generation circuit is configured by adding enable means that operates only when the operation is permitted. In this configuration, the activation period of the circuit can be freely limited by issuing the operation permission signal only when the random number is needed, and thus the power consumption can be reduced.

A random number generator according to a ninth aspect is
The mixer circuit is composed of an integrating circuit and a series connection circuit of a serial P-channel transistor circuit and a serial N-channel transistor circuit, which receives the integrated output signal and the amplified noise signal, respectively.

According to a tenth aspect of the present invention, in the random number generating device, the mixer circuit is a serial transistor circuit of an N-channel transistor and a P-channel transistor that receives a combined signal of the amplified noise signal and the input signal. Composed.

In the random number generator according to the present invention, the phase difference between the two input signals input to the RS flip-flop is automatically adjusted so that the appearance rate of 1 or 0 in the flip-flop output is constant. In the random number generator configured as described above, a P-channel transistor is provided on the power supply side of the R-side gate circuit of the internal transistor circuit or the S-side gate circuit forming the RS flip-flop, and
N-channel transistors are connected in series on the ND side, and a noise source and an amplifier circuit for amplifying the noise are connected to the inputs of the P-channel transistor and the N-channel transistor, and one of the gate circuits is connected by the amplified noise signal. It is configured to change the threshold voltage of.

In the random number generator according to the present invention, the phase difference between the two input signals input to the RS flip-flop is automatically adjusted so that the appearance rate of 1 or 0 in the flip-flop output is constant. In the random number generator configured as described above, a P-channel transistor is provided on the power supply side of the R-side gate circuit and the S-side gate circuit of the internal transistor circuit forming the RS flip-flop, and the GN.
N-channel transistors are connected in series to the D side, respectively, and a noise source and an amplifier circuit for amplifying the noise are connected to the inputs of the P-channel transistor and the N-channel transistor, and both gates are connected by the amplified noise signal. It was configured to change the threshold voltage of the circuit.

In the RS flip-flop, when the phase difference between the rising edges of the R-side input signal and the S-side input signal approaches 0, a metastable phenomenon occurs. When this phenomenon occurs, it takes time for the output of the flip-flop to be fixed, and the output state after a certain time is either 0 or 1, the threshold voltage is held, or the oscillation state. Here, in the configurations according to claims 11 and 12, by changing the threshold voltage of the R-side and / or S-side gate circuit, a stable state of 1 or 0 is immediately obtained from the metastable state. be able to. Then, the phase difference between the two input signals is automatically adjusted so that the appearance rate of 1 or 0 in the output of the flip-flop becomes constant.

According to a thirteenth aspect of the present invention, in the random number generating device, the amplifier circuit has a series input circuit including a capacitor and a resistor, a series circuit of a P-channel transistor and an N-channel transistor, and the transistor circuit. It is constituted by interposing a resistor between the input and output.

According to a fourteenth aspect of the present invention, in the random number generating device, the amplifier circuit has a series input circuit including a capacitor and a resistor, a series circuit of a P-channel transistor and an N-channel transistor, and the transistor circuit. A resistor and a capacitor are interposed in parallel between the input and the output of.

In the random number generator according to the fifteenth aspect, the amplifier circuit has a multi-stage configuration. Here, in the configuration according to any one of claims 13 to 15, a Low Pass Filter or a High Pass Filter is provided depending on a noise source described later.
An amplifier having a suitable characteristic can be realized by appropriately setting the frequency characteristic of. Further, when the MOS transistor is used, the influence of temperature and power supply fluctuation can be reduced, and stable operation can be obtained.

According to the sixteenth aspect of the present invention, in the random number generator, the noise generating source is formed by connecting a P-channel transistor and an N-channel transistor in series and short-circuiting the input and the output.

According to the seventeenth aspect of the present invention, in the random number generator, the noise source is formed by connecting a P-channel transistor and an N-channel transistor in series, and interposing a resistor between the input and the output. It

According to the eighteenth aspect of the present invention, in the random number generating device, the noise generating source has a P-channel transistor and an N-channel transistor connected in series, a resistor is interposed between the input and the output, and the noise is generated between the input and the GND. It consists of a series circuit consisting of a resistor and a capacitor.

According to a nineteenth aspect of the present invention, in the random number generating device, the noise generating source has a P-channel transistor and an N-channel transistor connected in series, a resistor is provided between the input and the output, and the noise is generated between the input and the power supply. It consists of a series circuit consisting of a resistor and a capacitor.

Further, in the random number generating device according to the twentieth aspect, the noise generating source is constituted by short-circuiting the input and output of the N-channel transistor and interposing a resistor between the output and the power supply.

Further, in the random number generating device according to the twenty-first aspect, the noise generating source is constituted by interposing a resistor between the input and output of the N-channel transistor and between the output and the power supply, respectively.

Further, in the random number generating device according to the twenty-second aspect, the noise generating source is formed by short-circuiting the input and the output of the P-channel transistor and interposing the resistor between the output and the GND.

Further, in the random number generating device according to the twenty-third aspect, the noise generating source is constituted by interposing resistors between the input and the output and between the output and the GND of the P-channel transistor.

Here, in the configurations described in claims 16 to 23, a weak thermal noise generated from a circuit element (transistor, resistor, capacitor, or a combination thereof) in an active state as a noise source is generated. Since it is used, it can be realized at a very low cost with a simple circuit configuration.

A probability generating device according to a twenty-fourth aspect is configured by using the random number generating device according to any one of the first to twenty-third aspects. With this configuration, the random number generator has uniformity, and an ideal probability generator without regularity, correlation, and periodicity can be realized. If it is used for cryptographic communication, etc., communication with excellent security can be performed.

[0035]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a random number generator and a probability generator according to the present invention will be described below with reference to FIGS.

First, the first embodiment of the present invention will be described. As shown in FIG. 1, the random number generator 1 of the first embodiment is described.
0 is a flip-flop 1 that outputs a 1-bit serial random number RND, and the flip-flop input (CL
Two delay circuits 2 and 3 for giving a phase difference between K signals)
And a phase control circuit 5 for adjusting a delay time of the delay circuit 3 and a jitter generation circuit 4, 4 added corresponding to each delay circuit 2, 3.

The phase control circuit 5 measures a predetermined repetition period of the CLK signal and outputs 1 of the flip-flop output (random number data RND) within the predetermined period.
Or, the number of 0s is monitored and the appearance rate is a constant value (for example,
Feedback control for automatically adjusting the delay time of the delay circuit 3 so as to be maintained at 50%), and as a result,
As shown in FIG. 35 (c), it operates so that the phase difference Δt between the two input signals input to the flip-flop 1 approaches 0. The flip-flop 6 added to the final stage is a latch circuit for synchronizing the output timing of the random number data RND with the CLK signal.

Here, as the flip-flop 1, an edge-triggered flip-flop whose output state (1 or 0) is determined by the phase difference of the input signal can be used. In the present embodiment, CLK is used. A D-type flip-flop having a terminal and a D terminal is used, and a jitter generation circuit 4 described in detail below induces phase jitter in an input signal to positively cause an uncertain operation.

As shown in FIG. 3, the jitter generating circuit 4
Is composed of a noise generation source 7, an amplification circuit 8 for power-amplifying the generated weak noise, and a mixer circuit 9 for causing a jitter in an input signal by the amplified noise signal.

In the mixer circuit 9 mounted on the jitter generating circuit 4 of FIG. 3, circuits of P-channel MOS transistors Q4 and Q3 connected in series and circuits of N-channel MOS transistors Q2 and Q1 connected in series are connected in series. In each of the series transistor circuits, the output of the amplifier circuit 8 is connected to the gates of the transistors Q4 and Q1, and the gates of the transistors Q3 and Q2 are connected to the resistor R and The output of the integrating circuit 12 by the capacitor C is connected. Input IN
The output of the delay circuit 2 or the delay circuit 3 is connected to.

In the above circuit configuration, as shown in FIG. 5, by inputting the amplified noise signal to the gates of the transistors Q4 and Q1, the threshold voltage of the transistors Q3 and Q2 with respect to the integrated output waveform of the delayed CLK signal is increased. It fluctuates, and jitter Δj is generated at the output OUT. The magnitude of this jitter Δj greatly expands the uncertain operation range of the flip-flop 1 in the subsequent stage.

As the mixer circuit 9, in addition to the embodiment shown in FIG. 3, the configuration shown in FIG. 4 can be adopted. In the embodiment of FIG. 4, P-channel MOS transistors Q2 and N
It is composed of a series circuit of the channel MOS transistor Q1, and each gate has an output and an input IN of the amplifier circuit 8.
Delayed CLK signal from the capacitor C and resistor R respectively
Connected through. Therefore, in the above circuit configuration,
The amplified noise signal and the CLK signal whose phase is adjusted by the delay circuit are combined by the capacitor C and input to the gates of the transistors Q2 and Q1, and the output having the jitter Δj as in the case of FIG. OUT is obtained.

Next, the structure of the noise source 7 will be described. 6 to 13 show specific circuit examples of the noise source 7. FIG. 6 shows a configuration in which a P-channel MOS transistor Q2 and an N-channel MOS transistor Q1 are connected in series and the gate and the output are short-circuited.
Further, FIG. 7 shows a resistor R2 between the gate and the output in FIG.
Is intervening. Further, FIG. 8 shows the P channel M
An OS transistor Q2 and an N-channel MOS transistor Q1 are connected in series, a resistor R2 is interposed between a gate and an output, and an RC series circuit including a resistor R1 and a capacitor C1 is interposed between a gate and GND. . Further, FIG. 9 shows the configuration in which the RC series circuit in FIG. 8 is interposed between the gate and the power supply. Further, FIG. 10 shows a configuration in which the gate and the output of the N-channel MOS transistor Q1 are short-circuited and the resistor R1 is interposed between the output and the power supply. Further, FIG. 11 is configured by interposing a resistor R2 between the gate and the output in FIG. Further, FIG. 12 is configured by short-circuiting the gate and output of the P-channel transistor Q1 and interposing a resistor R1 between output and GND. In addition, FIG.
In the above, the resistor R2 is interposed between the gate and the output.

In the above embodiment, the feeble thermal noise generated in the circuit element (transistor, resistor, capacitor, or a combination thereof) in the active state is used to realize an inexpensive noise source. Further, it is less affected by external noise and power supply fluctuations, etc., and stable operation is obtained, and since it does not use a radiation source, it is excellent in environmental safety and does not cause a problem of disposal such as disposable disposal.

Next, the structure of the amplifier circuit 8 will be described with reference to FIGS. The amplifier circuit 8 shown in FIG.
Serial input circuit (Hight with capacitor C1 and resistor R1
Pass Filter) and P-channel MOS transistor Q2
And a series circuit of N-channel MOS transistor Q1. Further, the amplifier circuit 8 shown in FIG. 15 has a configuration in which a capacitor C2 is connected in parallel to the feedback resistor R2 in FIG. 14 to form a Low Pass Filter. . Although not shown, the output of the noise generation source 7 is connected to the input IN of these amplifier circuits 8 and the output OUT is connected to the mixer circuit 9 described above. In the amplifier circuit 8 having the above configuration,
Depending on the configuration of the noise source 7 described above, the High Pa
The characteristics of ss Filter and Low Pass Filter are set, and an amplifier with suitable characteristics is realized.

Next, a specific circuit configuration of the jitter generating circuit 4 will be described with reference to FIGS. These are configured by a combination of the noise generating source 7, the amplifier circuit 8 and the mixer circuit 9 described above, and the following is a physical example of them. Therefore,
Of course, the present invention is not limited to these circuit examples.

FIG. 16 shows a jitter generation circuit 4 having the configuration shown in FIG. 3, which is composed of a combination of the noise generation source 7 shown in FIG. 6 and the amplification circuit 8 shown in FIG. Also, FIG.
7 is an example of a circuit configured by connecting the amplifier circuits 8 in series in two stages in FIG. Further, FIG. 18 shows that P-channel MOS transistors Q14 and Q2 are provided on the power supply sides of the noise source 7, the amplifier circuit 8 and the mixer circuit 9 in FIG.
A switch circuit 14 composed of Q4, Q34, and Q46, and an N-channel MOS transistor Q1 on each ground side.
Switch circuit 15 composed of 1, Q21, Q31 and Q41
Are connected, and these switch circuits 14 and 15 are turned on / off by an operation enable signal ENABLE from the outside. Specifically, the jitter generation circuit 4 is operated by supplying power to each circuit only when a random number is required. It is configured to let.

As described above, by freely limiting the activation period of the circuit by the enable function, it is possible to eliminate wasteful power consumption and reduce the power consumption of the random number generator.

19 to 22 show the jitter generating circuit 4 based on the configuration of FIG. 4, and the combination form of the noise generating source 7 and the amplifying circuit 8 is the same as in the case of FIGS. 16 to 18 already described. Therefore, the description is omitted here.

Although the embodiment of the jitter generating circuit 4 has been described above, in the present invention, the jitter generating circuit 4 is provided on both input lines (CLK terminal and D terminal) of the flip-flop 1.
In addition to the configuration of the random number generator 10 of FIG. 1 added to the terminal), the jitter generation circuit 4 is added only to one of the input lines (the D terminal side in this embodiment) of the flip-flop 1. It is also possible to adopt a configuration of No. 2 and thereby the same effect as that of the configuration of FIG. 1 can be obtained. In this case, in order to match the input timings of both input terminals, the RC input circuit 13 (the integration of FIG. 3) for correcting the delay time by the jitter generation circuit 4 is applied to the other input line (CLK terminal in this embodiment). (Corresponding to the time constant of the circuit 12) is added.

By the way, in the jitter generation circuit 4, chattering occurs in the output of the mixer circuit 9 due to the input of the integrated waveform, and 1 is input to the input terminal of the flip-flop 1.
The inconvenience arises that an input signal is input a plurality of times within one random number generation period.

Therefore, in this embodiment, FIGS.
As shown in FIG. 5, an RS flip-flop 11 that operates (sets / resets) at both edges (rising / falling) of the CLK signal is provided at the subsequent stage of the jitter generation circuit 4, and the output OUT of the mixer circuit 9 is output as a CKL signal. I tried to latch with. As a result, a signal without chattering can be input to the flip-flop 1, and stable random number generation can be performed. In the configuration of FIG. 24, the integrating circuit 13
Also in this case, since chattering occurs in the buffer output in the subsequent stage, the RS flip-flop 11 is added.

In the embodiment described above, the D-type flip-flop 1 is used as the flip-flop 1 for generating random numbers, but the present invention is not limited to this, and a function equivalent to this is provided. Any flip-flop may be used, for example, an RS flip-flop can be used.

Next, a second embodiment of the present invention will be described. As shown in FIG. 25, the random number generator 10 according to the second embodiment.
Is a D-type flip-flop 18 that outputs a 1-bit serial random number RND, and two delay circuits 2 and 3
, A phase-voltage conversion circuit 17, and a phase control circuit 5 (not shown) (see FIGS. 1 and 2).

Here, the phase-voltage conversion circuit 17 is
A circuit for converting the phase difference between the delayed output signals of the delay circuits 2 and 3 into a voltage, and as shown in the internal circuit of FIG.
A gate circuit for detecting the phase difference between (CLK) and the input IN (D), a series circuit of a P-channel MOS transistor Q2 and an N-channel MOS transistor Q1 which is turned on / off by the output of each gate circuit, and is connected to the output side thereof. And an RC integrating circuit.

In the phase-voltage conversion circuit 17 having the above configuration, the phase of IN (D) is IN (CL) as shown in FIG.
K), the P-channel MOS transistor Q2 is turned on (during this period, the N-channel MOS transistor Q1 is turned off) by the phase difference, the capacitor C is charged through the resistor R, and the input voltage v ( t
It operates to raise h). Also, FIG. 27 (b)
When the phase of IN (D) is delayed from IN (CLK), the N-channel MOS transistor Q1 is turned on (during this period, the P-channel MOS transistor Q2 is turned off) by the phase difference and the resistance R is passed. And discharges the capacitor C and operates so as to drop the input voltage V (th) of the buffer.

Therefore, at the output of the phase-voltage conversion circuit 17, a voltage V (th) approximately equal to the threshold voltage of the buffer connected thereto is generated, and two inputs, IN (CLK) and IN ( D) The change in the output voltage caused by the phase difference is converted into a digital signal due to the relationship with the threshold voltage of the buffer, and the flip-flop 1
1 input to the D terminal of 8 and synchronized with the CLK signal at the output
Bit random number data RND is obtained. Then, the random number data RND is monitored by the phase control circuit 5, and the phase difference (ie, phase) between the two input signals is controlled so that the appearance rate of 1 or 0 in the flip-flop output becomes constant (eg, 50%). -The output of the voltage conversion circuit 7) is automatically adjusted.

Although not shown, in FIG. 25, R
By connecting the resistors in series after the C integrator circuit, the noise generated by the resistors makes the threshold operation of the next-stage element more effective due to the fluctuation of V (th).

In FIG. 25, the phase-voltage conversion circuit 17
Although the buffer is interposed between the flip-flop 18 and the flip-flop 18, it may be directly connected to the D terminal of the flip-flop 18 without the buffer. In this case, the output voltage V (th) of the phase-voltage conversion circuit 7 is automatically adjusted to the threshold voltage of the D terminal. Further, a comparator is used instead of the buffer, and the output voltage V
A digital signal may be obtained by comparing (th) with the reference voltage.

Further, as shown in FIG. 28, a P-channel MO is connected to the serial transistor circuit of the phase-voltage conversion circuit 7.
By adding the S-transistor Q4 and the N-channel transistor Q5 and stopping the circuit operation by the operation enable signal ENABLE from the outside except when necessary, the power consumption can be reduced.

FIG. 29 shows a configuration in which the jitter generation circuit 4 is connected to the output side of the phase-voltage conversion circuit 17. The jitter generation circuit 4 has the configuration shown in FIGS. 3 and 4 which is composed of the noise generation source 7, the amplification circuit 8 and the mixer circuit 9, and the description thereof is omitted here. By connecting the jitter generation circuit 4 and causing the jitter in the threshold voltage V (th), the uncertain factor of the probability that 1 or 0 of the flip-flop output appears is positively increased, and as a result, it becomes uniform. Thus, it becomes possible to easily generate a more complete natural random number that has the property of not having regularity, correlation, or periodicity. Next, a third embodiment of the present invention will be described. As shown in FIG. 30, the random number generator of the third embodiment outputs R that outputs a 1-bit serial random number RND.
-S flip-flop 16 and this RS flip-flop
It is composed of delay circuits 2 and 3 connected to the S terminal and the R terminal of the flop 16 and a phase control circuit 5 (not shown) (see FIGS. 1 and 2).

FIG. 31 shows the internal circuit of the RS flip-flop composed of N-channel MOS transistors and P-channel MOS transistors. The transistors Q1 to Q4 form the NAND gate circuit on the S side, N on the R side by transistors Q5 to Q8
An AND gate circuit is configured.

For example, in an edge-triggered flip-flop such as the RS flip-flop, a metastable phenomenon may occur when the phase difference between the rising edges of the S-side input signal and the R-side input signal approaches 0. It is known that when this phenomenon occurs, it takes time for the flip-flop output to be determined, and the output state after a certain time is 0.
1 or 1, the threshold voltage is held, or the oscillation state is established. The present embodiment positively utilizes this metastable phenomenon to generate natural random numbers.

That is, in this embodiment, as shown in FIG. 32, in the circuit configuration of FIG. 31, a P-channel MOS transistor Q10 is provided on the power supply Vcc side of the S-side NAND gate circuit, and an N-channel MOS transistor is provided on the GND side. Q9 is connected in series, and the noise generation source 7 and the amplifier circuit 8 are connected to the gates of these transistors Q9 and Q10.
It was configured to change the threshold voltage of the gate circuit. In addition, the output of the delay circuit 2 is connected to the terminal R at the terminal S.
Is connected to the output of the delay circuit 3. In addition, FIG.
The above circuits are added to both the S-side and R-side NAND gate circuits, and separate amplified noise signals are input to the respective circuits.

In the above structure, by changing the threshold voltage of the NAND gate circuit, the flip-flop output can be immediately brought to a stable state of 1 or 0 from the metastable state. The random number data RND is monitored by the phase control circuit 5, and the phase difference between the two input signals is automatically adjusted so that the appearance rate of 1 or 0 in the flip-flop output becomes constant (for example, 50%). .

In the third embodiment described above, the RS flip-flop 16 is used as the flip-flop for generating random numbers (flip-flop that causes the metastable phenomenon), but the present invention is limited to this. Other flip-flops (for example,
Of course, it is also possible to realize an equivalent function with a D-type flip-flop or the like).

Although not shown, the above-mentioned first to third
By arranging P serial-type random number generators 10 of the embodiment in parallel, it is possible to configure a parallel-type random number generator having a Pbit configuration in which there is no mutual relationship between the individual random number generators 10.

Further, if the probability generator is constructed by using the serial type random number generator or the parallel type random number generator described above, an ideal probability having no regularity, correlation or periodicity can be generated. You can

As described above, each circuit of the present invention is
Since it is digitally configured using transistors, it is an LSI
It is easy to deal with high productivity and has high productivity, and it is possible to supply a large amount of random number and probability data at high speed and at low cost for applications to high-tech industries such as scientific computing, game machines, and cryptographic processing. It is a thing.

[0070]

As described above, according to the present invention,
Since a jitter generation circuit is added to the input line of the flip-flop that generates random numbers, the jitter of the input signal causes
The uncertain operation range of the flip-flop is expanded to facilitate the generation of random numbers, resulting in a more complete natural random number generator with uniformity and no regularity, correlation, or periodicity. can do. Further, as another configuration, since the phase adjustment is converted into a voltage and the voltage fluctuation is digitized by using the threshold voltage of the circuit element, a random number is generated, so that there is uniformity, In addition, it is possible to realize a more complete natural random number generator having no regularity, correlation, or periodicity. further,
As another configuration, since the random number is generated by utilizing the metastable phenomenon of the flip-flop, it is a more complete natural random number that has uniformity and does not have regularity, correlation or periodicity. The generator of can be realized.

Further, by using the random number generating device having such a configuration, an ideal probability generating device having a uniform probability distribution over the entire area can be realized, and scientific and technological calculations, game machines,
Alternatively, it is extremely effective for entering a high-tech industry that has security such as encryption processing.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of a random number generator according to the present invention.

FIG. 2 is a diagram showing a configuration different from that of FIG. 1 of the random number generation device according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a jitter generation circuit according to the present invention.

FIG. 4 is a diagram showing a configuration different from that of FIG. 3 of a jitter generation circuit according to the present invention.

FIG. 5 is a diagram showing input / output waveforms in jitter generation.

FIG. 6 is a diagram showing a configuration of a noise generation source according to the present invention.

FIG. 7 is a diagram showing a configuration of the noise generation source according to the present invention, which is different from that of FIG. 6;

FIG. 8 is a diagram showing a configuration of the noise generation source according to the present invention, which is different from FIG. 7.

FIG. 9 is a diagram showing a configuration of the noise generation source according to the present invention, which is different from that of FIG. 8;

FIG. 10 is a diagram showing a configuration of the noise generation source according to the present invention, which is different from that of FIG. 9;

FIG. 11 is a diagram showing a configuration of the noise source according to the present invention, which is different from FIG.

FIG. 12 is a diagram showing a configuration of the noise source according to the present invention, which is different from that of FIG.

FIG. 13 is a diagram showing a configuration of the noise generation source according to the present invention, which is different from that shown in FIG. 12;

FIG. 14 is a diagram showing a configuration of an amplifier circuit according to the present invention.

FIG. 15 is a diagram showing a configuration different from that of FIG. 14 of the amplifier circuit according to the present invention.

FIG. 16 is a diagram showing a circuit configuration of a jitter generation circuit according to the present invention.

FIG. 17 is a diagram showing a circuit configuration different from that of FIG. 16 of the jitter generation circuit according to the present invention.

FIG. 18 is a diagram showing a circuit configuration of the jitter generation circuit according to the present invention, which is different from that shown in FIG. 17;

19 is a diagram showing a circuit configuration different from that of FIG. 18 of the jitter generation circuit according to the present invention.

FIG. 20 is a diagram showing a circuit configuration of the jitter generation circuit according to the present invention, which is different from that of FIG. 19;

FIG. 21 is a diagram showing a circuit configuration of the jitter generation circuit according to the present invention, which is different from FIG. 20.

FIG. 22 is a diagram showing a circuit configuration of the jitter generation circuit according to the present invention, which is different from that of FIG. 21.

FIG. 23 is a circuit diagram of essential parts of a random number generation device according to the present invention to which a latch circuit is added.

24 is a circuit diagram of a main part, which is different from FIG. 23, of the random number generation device according to the present invention to which a latch circuit is added.

FIG. 25 is a diagram showing a second embodiment of a random number generation device according to the present invention.

FIG. 26 is a diagram showing a phase-voltage conversion circuit according to the present invention.

27 is a diagram showing an operation of the phase-voltage conversion circuit of FIG. 26. FIG.

FIG. 28 is a diagram showing a configuration different from that of FIG. 26 of the phase-voltage conversion circuit according to the present invention.

FIG. 29 is a diagram showing a configuration different from that of FIG. 25 of the random number generation device according to the second embodiment of the present invention.

FIG. 30 is a diagram showing a third embodiment of a random number generation device according to the present invention.

FIG. 31 is a diagram showing an internal configuration of an RS flip-flop.

FIG. 32 is a diagram showing an internal configuration of an RS flip-flop according to the third embodiment of the present invention.

FIG. 33 is a diagram showing the internal structure of an RS flip-flop different from that of FIG. 32 according to the third embodiment of the present invention.

FIG. 34 is a diagram showing a D-type flip-flop.

35 is a diagram showing the operation of the flip-flop shown in FIG. 34. FIG.

[Explanation of symbols]

1 flip flop 4 Jitter generator 7 Noise source 8 amplifier circuit 9 Mixer circuit 10 Random number generator 11 Latch means (RS flip-flop) 12,13 Integration circuit 14, 15 Enable means (switch circuit) 16 R-S flip-flop 17 Phase-voltage conversion circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Misako Koibuchi 5-36-11 Shinbashi, Minato-ku, Tokyo Iwaki Electronics Co., Ltd. (56) References JP-A-2-145010 (JP, A) (58) Survey Fields (Int.Cl. ⁷ , DB name) G06F 7/58

Claims (24)

(57) [Claims] 1. A random number generator in which the phase difference between two input signals input to a flip-flop is automatically adjusted so that the appearance rate of 1 or 0 in the flip-flop output becomes constant. In the input line of, a jitter generation circuit including a noise generation source, an amplification circuit that amplifies the noise, and a mixer circuit that causes a jitter in the input signal based on the clock signal by the amplified noise signal is added. Characteristic random number generator. 2. The random number generator according to claim 1, wherein the jitter generation circuit is added to both input lines of the flip-flop. 3. The jitter generation circuit is added to one of the input lines of the flip-flop, and an integration circuit for delay time correction is added to the other input line of the flip-flop. Random number generator. 4. The random number generation device according to claim 1, further comprising a latch unit that latches an output of the jitter generation circuit for each repetition cycle of the input signal. 5. A random number generator in which a phase difference between two input signals is automatically adjusted so that an appearance rate of 1 or 0 in a flip-flop output becomes constant, wherein a data input line of the flip-flop has: A random number generator characterized in that a phase-voltage conversion circuit for converting the phase difference between the two input signals into a voltage is added. 6. The random number generation device according to claim 5, wherein the phase-voltage conversion circuit has enable means that operates only when operation is permitted. 7. A jitter generator that comprises, at the output of the phase-voltage conversion circuit, a noise generation source, an amplifier circuit that amplifies the noise, and a mixer circuit that causes a jitter in the input signal due to the amplified noise signal. 7. The random number generator according to claim 5, wherein a circuit is added. 8. The random number generation device according to claim 1, wherein the jitter generation circuit has enable means that operates only when operation is permitted. 9. The mixer circuit comprises an integrator circuit, and a series connection circuit of a serial P-channel transistor circuit and a serial N-channel transistor circuit, which receives the integrated output signal and the amplified noise signal, respectively. Claims 1 to 4 and 7 characterized
The random number generator according to any one of 1. 10. The mixer circuit is also configured by a serial transistor circuit of an N-channel transistor and a P-channel transistor, which receives a composite signal of the amplified noise signal and the input signal as an input. 8. The random number generator according to any one of claims 4 to 7. 11. A random number generator in which the phase difference between two input signals input to an RS flip-flop is automatically adjusted so that the appearance rate of 1 or 0 in the flip-flop output becomes constant. A P-channel transistor is connected in series to the R side gate circuit of the internal transistor circuit forming the S flip-flop or the power supply side of the S-side gate circuit, and an N channel transistor is connected to the GND side. And a noise generation source and an amplifier circuit for amplifying the noise are connected to the inputs of the N-channel transistor, and the threshold voltage of one of the gate circuits is changed by the amplified noise signal. 12. A random number generator in which the phase difference between two input signals input to an RS flip-flop is automatically adjusted so that the appearance rate of 1 or 0 in the flip-flop output becomes constant. -A P-channel transistor is provided on the R side gate circuit of the internal transistor circuit forming the S flip-flop and the power supply side of the S side gate circuit, and an N side is provided on the GND side
While connecting the channel transistors in series,
A random number characterized by connecting a noise source and an amplifier circuit for amplifying the noise to the inputs of the P-channel transistor and the N-channel transistor, and changing the threshold voltages of both the gate circuits by the amplified noise signal. Generator. 13. The amplifier circuit includes a series input circuit including a capacitor and a resistor, and a series circuit of a P-channel transistor and an N-channel transistor, and
A resistor is interposed between the input and the output of the transistor circuit, and the transistor circuit has a resistor.
And the random number generation device according to any one of claims 11 and 12. 14. The amplifier circuit further includes a series input circuit including a capacitor and a resistor, and a series circuit of a P-channel transistor and an N-channel transistor,
A random number according to any one of claims 1 to 4, claim 7, claim 11 and claim 12, wherein a resistor and a capacitor are interposed in parallel between the input and output of the transistor circuit. Generator. 15. The random number generator according to claim 13, wherein the amplifier circuits are connected in multiple stages in series. 16. The noise generating source is configured by connecting a P-channel transistor and an N-channel transistor in series and short-circuiting between an input and an output. The random number generation device according to any one of claim 7, claim 11, and claim 12. 17. The noise source further comprises a P-channel transistor and an N-channel transistor connected in series, and a resistor interposed between the input and the output. The random number generation device according to any one of claim 4, claim 7, claim 11, and claim 12. 18. The noise source further includes a P-channel transistor and an N-channel transistor connected in series, a resistor interposed between the input and the output, and the input-source.
The random number generator according to any one of claims 1 to 4, claim 7, claim 11 and claim 12, characterized in that a series circuit of a resistor and a capacitor is interposed between GNDs. 19. The noise source further includes a P-channel transistor and an N-channel transistor connected in series, a resistor interposed between the input and the output, and the input-source.
A random number generator according to any one of claims 1 to 4, claim 7, claim 11, and claim 12, characterized in that a series circuit of a resistor and a capacitor is interposed between the power supplies. 20. The noise source further comprises a short circuit between the input and the output of the N-channel transistor, and a resistor interposed between the output and the power supply. 4 and claim 7 and claim 1
The random number generation device according to claim 1 or 12. 21. The noise generating source is also configured by interposing a resistor between the input and output of the N-channel transistor and between the output and the power supply, respectively. The random number generation device according to any one of claim 7, claim 11, and claim 12. 22. The noise source further comprises a short circuit between the input and the output of the P-channel transistor and a resistor interposed between the output and the GND. 4. The random number generator according to claim 4, claim 7, claim 11 or claim 12. 23. The noise generating source is also configured by interposing a resistor between the input and output of the P-channel transistor and between the output and GND of the P-channel transistor, respectively. The random number generation device according to any one of claim 7, claim 11, and claim 12. 24. A probability generation device comprising the random number generation device according to any one of claims 1 to 23.