CN100414465C - Multi-serial bus passive real panel - Google Patents
Multi-serial bus passive real panel Download PDFInfo
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- CN100414465C CN100414465C CNB2005100467787A CN200510046778A CN100414465C CN 100414465 C CN100414465 C CN 100414465C CN B2005100467787 A CNB2005100467787 A CN B2005100467787A CN 200510046778 A CN200510046778 A CN 200510046778A CN 100414465 C CN100414465 C CN 100414465C
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Abstract
The invention relates to a multiple string trunk passive backboard for the decentralized controller, the distributed control system and the programmable logic controller which includes the power backboard, the controller backboard, the I/O backboard, the backboard elongation pad, the end matching module which is connected to the end I/O backboard. The low speed serial trunk is mixed with the middle speed serial trunk. The three serial trunks are connected to the different I/O modules respectively. The invention has the high reliability, many supporting modules, many kinds of modules and high communication speed, low cost.
Description
Technical field
The present invention relates to the back board module of decentralised control station in the automation field, DCS (dcs), PLC (programmable logic controller (PLC)) etc., a kind of specifically multi-serial bus passive real panel, be used for power module, the controller module of the said goods, the connection of various I/O modules, realize the power supply and the communication function of intermodule.
Background technology
At present, be used for the composition mode that automatic decentralised control station, DCS (dcs), the PLC (programmable logic controller (PLC)) that controls substantially adopts backboard and module both at home and abroad.Backboard is by having or not active device can be divided into active backboard and passive backplane; Can be divided into single module backboard and multimode backboard by plug-in module number; Can be divided into rack posture and guide tracked backboard by mounting means; Can be divided into parallel bus and universal serial bus by bus form.Below the relative merits of various forms backboard are done simple an introduction.
| Classification | Advantage | Shortcoming |
| Active backboard | Can simplify modular design | Poor reliability, difficult in maintenance, backboard cost height. |
| Passive backplane | Passive design, the reliability height, the backboard cost is low | Modular design is complicated, not absolute slightly. |
| The single module backboard | Can not waste I/O module slot position | When a plurality of backboards connect, be easy to generate mechanical fault, poor reliability, thus generally can only connect the minority module, to reduce failure rate. |
| The multimode backboard | Only need less backboard can support a lot of I/O modules | Module is installed quantity can waste I/O module slot position after a little while. |
| Parallel backboard | Can realize high traffic rate | Take more connector pinout, poor reliability, total length is limited, and support module quantity is few, poor anti-interference. |
| Low speed list universal serial bus backboard | Connector pinout is few, the reliability height, and total length can be very long, and is anti-interference strong.Simplicity of design, low cost. | Speed is low, can't support big data quantity and high-speed module. |
| The single universal serial bus backboard of high speed | Connector pinout is few, reliability height, speed height. | Design is complicated, the cost height, and PCB layout difficulty height, power consumption is big, and antijamming capability is poor slightly, and support module quantity is medium. |
Above-mentioned various forms backboard all has employing on a lot of Related products.What adopt on the FP3000 decentralised control station as America NI company is active, single module, guide tracked, parallel backboard, and the MOST system of U.S. MTL adopts is passive, multimode, guide tracked, low-speed serial backboard.
Yet present existing technical scheme all can't be weighed in all respects preferably, does not also have patent or document to take into account aspects such as reliability, support module quantity, support module kind, communication speed, cost at the same time and does relevant the introduction.
Summary of the invention
In order to solve the problem that can not take into account aspects such as reliability, support module quantity, support module kind, communication speed, cost in the existing design simultaneously, the object of the invention is to provide a kind of multi-serial bus passive real panel that has characteristics such as reliability height, support module quantity is many, the support module kind is complete, communication speed is high, cost is low simultaneously.
To achieve these goals, concrete technical scheme of the present invention comprises:
-power supply backplane is electrically connected with other backboards, is used to install power module;
-controller back plate links to each other with I/O backboard and power supply backplane, is used to install controller module;
-I/O backboard is used to install the I/O module, with controller back plate, and power supply backplane link to each other; Described I/O backboard has: power path, backboard address shift circuit, module relative address form circuit, universal serial bus path;
-backboard extender is used to realize the connection of I/O backboard;
Also comprise the terminal matching module, do not link to each other, be used for the terminal coupling of the inner difference string row bus of I/O backboard with holding the I/O backboard; The overall many universal serial bus technology that adopts of I/O backboard, low-frequency serial bus and middling speed universal serial bus Mixed Design, multiple universal serial bus is worked simultaneously; Be embodied in 3 kinds of universal serial bus paths of I/O backboard, 3 kinds of universal serial bus paths connect different I/O modules respectively, are specially:
1) the 1st universal serial bus adopts 1Mbps half-duplex asynchronous communication, has a pair of difference string row bus, and communication mode is 485 communication modes, and controller and I/O module communication are principal and subordinate's inquiry mode, and controller sends read-write requests, and the I/O module is returned corresponding response; The 1st universal serial bus is used for conventional low speed I/O module;
2) the 2nd universal serial bus adopts 6Mbps half-duplex synchronous communication; Have two pairs of difference string row bus, that is: a pair of transmitting synchronous clock that is used for, another is to being used to transmit data; The 2nd universal serial bus is realized the data transmission of controller and I/O module by programmable logic device (PLD); The 2nd universal serial bus is used for high speed DI, DO (digital quantity input, digital quantity output module);
3) the 3rd universal serial bus adopts the 6Mbps full duplex synchronously from arbitrating communication mode, is applicable to the variety of protocol conversions module; The 3rd universal serial bus utilizes the high-speed synchronous serial communication function of CPU (central processing unit), adds priority arbitration mechanism simultaneously;
Wherein said the 2nd universal serial bus has two kinds of operator schemes, and its communication format is as follows:
1) controller read operation: be made up of command frame and Frame, controller sends command frame, I/O module return data frame;
2) controller write operation: be made of command frame, Frame, I/O rreturn value, controller sends command frame, Frame, and the I/O module sends rreturn value;
Described the 3rd universal serial bus specifically is made up of clock signal, the transmission of I/O module data, the reception of I/O module data, the busy four pairs of differential signals of bus, wherein:
Clock signal provides the data communication synchronous clock, is produced by controller;
The I/O module data sends signal and is received by controller, receives line with controller data and links to each other;
I/O module data received signal is sent by controller, sends line with controller data and links to each other;
Bus busy signal detects before the I/O module sends, and the bus free time then sends data; When having a plurality of module requests to send simultaneously, determine which module to send earlier according to priority;
The priority arbitration mechanism realization flow of described the 3rd universal serial bus is as follows:
Elder generation's testbus busy signal when the I/O module sends data detecting bus when busy, is waited for and is also continued to detect; When detecting bus after the spare time, bus is made as busy, in the official hour sheet (timeslice by I/O module priority decision) I/O module repeatedly the I/O module data in the testbus send line whether signal arranged, finish up to timeslice; Do not have signal can take bus if the I/O module data sends line at once, send line by the I/O module data and send start signal; If I/O module data transmission line has signal then represents to have the I/O module of other high priority will take bus, this I/O module withdraws from competition; A period of time that bus is made as after hurrying is defined as the arbitration time, and the arbitration time span is (N-1) * Δ t, and wherein N is the I/O number of modules that participates in the competition on the 3rd universal serial bus, and Δ t is the cycle of a timeslice; According to priority order is given the timeslice of the different numbers of I/O module assignment, and the priority of each I/O module is by the address decision of module, and address low priority more is high more; The highest I/O module of priority directly sends start bit when idle detecting bus; Priority is detecting bus after the free time for time high I/O module, etc. a timeslice cycle Δ t to be detected, to send on the line be high to the I/O module data always in during Δ t, and promptly wait acknowledge does not use after the bus than the I/O module of its high priority and takies bus, the transmission start signal under the situation; When the number of I/O module is 3, the I/O module that priority is minimum, wait 2 timeslice cycles 2 Δ t to be detected, have only when the I/O of high priority module, priority do not take bus for time high I/O module, promptly send line at the I/O module data and remain under the situation of noble potential always, the I/O module that priority is minimum just can take bus and send start signal.
The present invention adopts many universal serial bus technology, low-frequency serial bus and middling speed universal serial bus Mixed Design, and the different bus of characteristics employing according to disparate modules satisfies the requirement of disparate modules.Multiple universal serial bus can be worked simultaneously, improves communication speed.Have more following advantage:
1. reliability height.The design of employing passive backplane only is made up of minority connector and passive device, greatly reduces the failure rate of backboard; Adopt the multimode back plate design, reduced backboard quantity, thereby reduced the connection fault between backboard; Employing serial design has significantly reduced number of signals, has improved the reliability of system.
2. Electro Magnetic Compatibility is good.Passive backplane itself can not produce any radiation; The serial design is because number of signals is few, so radiation is naturally little; Differential design has also guaranteed the low radiation of every pair of differential signal, has improved the antijamming capability of signal simultaneously.
3. dirigibility is strong.Can support various I/O modules, the present invention not only supports common data acquisition and output module, also supports the variety of protocol conversions module, and the function of being convenient to system expands.
4. cost is low.The cost of passive backplane design the simplification greatly backboard; The design of many universal serial bus guarantees that various modules adopt only universal serial bus, so also reduced the cost of corresponding module.
5. but support module quantity is many.The present invention is when guaranteeing module communication speed, and each backboard can be installed 8 I/O modules, and a decentralised control station can be installed 8 backboards at most, and a cover decentralised control station can be installed 64 I/O modules altogether.
6. support hot plug naturally.Need special circuit or structural support hot plug to compare with active backboard in the prior art, the present invention adopts passive design, with relevant module cooperation, can easily support hot plug, and the hot plug function can be carried out on-line maintenance to module easily.
7. thermal adaptability is good.The present invention adopts passive backplane can be operated in technical grade temperature range (40 ℃～85 ℃) even wideer temperature range easily.
Description of drawings
Fig. 1 is hardware architecture figure of the present invention.
Fig. 2 is an I/O backboard theory diagram.
Fig. 3 is an I/O backboard address shift circuit schematic diagram.
Fig. 4 is that I/O module relative address forms circuit theory diagrams.
Fig. 5 is a controller read operation command frame format.
Fig. 6 is a controller read operation I/O module return data frame format.
Fig. 7 is a controller write operation command frame format.
Fig. 8 is a controller write operation data frame format.
Fig. 9 is a controller write operation I/O module rreturn value form.
Figure 10 is the 3rd universal serial bus arbitration mechanism.
Embodiment
Below in conjunction with drawings and Examples the present invention is described in further detail.
As shown in Figure 1, the present invention is made up of power supply backplane, controller back plate, backboard extender, terminal matching module, I/O backboard, wherein:
-power supply backplane is electrically connected with other backboards, is used to install power module.
-controller back plate links to each other with I/O backboard and power supply backplane, is used to install controller module, functions such as controller back plate support controller redundancy, hot plug, the communication function of realization controller module and I/O module.
-I/O backboard is used to install the I/O module, is core of the present invention; With controller back plate, and power supply backplane link to each other, the hot plug of I/O backboard support I/O module, any one groove position of interconnective any one I/O backboard all can produce a unique address, is used for the location of I/O module.Module's address is to produce automatically, does not need extra wire jumper configuration.
-backboard extender is used to realize the connection of I/O backboard, uses when installing space is limited, as is installed in the rack.
-terminal matching module does not link to each other with holding the I/O backboard, is used for the terminal coupling of the inner difference string row bus of I/O backboard.
As shown in Figure 2, the I/O backboard is made up of three parts on hardware, left connector, I/O module slot, right connector.A left side/right connector be used between the I/O backboard and with being connected of controller back plate or power supply backplane.The I/O module slot can be 1～8, and present embodiment is 8, is used to install the I/O module, because space cause chart 2 does not all draw.
As shown in Figure 2, the I/O backboard is made of 4 parts on principle: power path, backboard address shift circuit, module relative address form circuit, universal serial bus path.Wherein:
Power path is responsible for power delivery to I/O module and next backboard.
As shown in Figure 3, backboard address shift circuit adopts PCB cabling ring shift method, realizes the automatic change of I/O backboard address, and each I/O backboard all has a unique backboard address.With 4 I/O backboards is example, be positioned at the leftmost side promptly the start address of the 1st I I/O backboard be 0001, this address is provided by controller back plate.0001 address directly offers the I/O module, and the address of giving next I/O backboard is through ring shift, and address, displacement back becomes 0010.The rest may be inferred, and the address of the 4th I/O backboard becomes 1000.Needing to support more I/O backboard only need increase I/O backboard address signal number gets final product.
As shown in Figure 4, the module relative address forms circuit and adopts direct ground connection of I/O module's address signal or unsettled mode, for unsettled address, utilizes pull-up resistor to draw on carrying out by the I/O module.With 8 module backboards is example, be provided with the 1st～the 8I/O module slot, the relative address of 1I/O module is 000, only corresponding 0 address signal need be connect logically and get final product, the full ground connection of this example, the relative address of 2I/O module is 001, and corresponding 1 address signal is unsettled, the I/O module's address increases progressively with scale-of-two, and the rest may be inferred.
The universal serial bus path is established 3 kinds altogether, connects different I/O modules respectively.
1, the 1st universal serial bus, adopt 1Mbps half-duplex asynchronous communication, be used for conventional low speed I/O module, as AI (analog input), AO (analog input), RTD (thermal resistance), TC (thermopair), interchange DI (digital quantity input), interchange DO (digital quantity output).The collection or the output speed of these modules self are lower, so use at utmost simplified design of this communication mode, reduce cost, and improve reliability.
Described the 1st universal serial bus only uses a pair of difference string row bus, adopts 485 general communication modes; Controller (being installed on the controller back plate) adopts principal and subordinate's inquiry mode with the I/O module communication, and controller sends read-write requests, and the I/O module is returned corresponding response.
2, the 2nd universal serial bus adopts 6Mbps half-duplex synchronous communication, is used for some DI, DO modules at a high speed, as SOE (sequence of events) module.This class I/O module requirement collection or output speed are very fast, but data are simple, only comprise the on off state of module.
Described the 2nd universal serial bus uses two pairs of difference string row bus.The a pair of transmitting synchronous clock that is used for, another is to being used to transmit data.Adopt CPLD (FPGA (Field Programmable Gate Array)) device to realize the data transmission of controller and I/O module.CPLD is arranged in controller and I/O module, communicates according to the communication format of the 2nd universal serial bus.
The 2nd universal serial bus has two kinds of operator schemes, and its communication format is as follows:
1) controller read operation: form by command frame and Frame.Controller sends command frame, I/O module return data frame.
A) read operation command frame format (as shown in Figure 5): the read operation command frame is formed by 10, and every implication is as follows:
Start bit: expression begins transmission.
R/W: read-write sign, 0: write; 1: read.
A4-A0: module's address, from 0 to 31.
AA1, AA0: module channels address; AA1, AA0 have following 4 kinds of combinations:
00: visit the 0th to the 7th passage;
01: visit the 8th to the 15th passage;
10: visit the 16th to the 23rd passage;
10: visit the 24th to the 31st passage.
B) I/O module return data frame format (as shown in Figure 6): be high-impedance state on first clock bus after the controller read command frame sends and finishes, second clock I/O module sends Frame, negative edge output.
2) controller write operation: be made of command frame, Frame, I/O rreturn value, controller sends command frame, Frame, and the I/O module sends rreturn value;
A) write operation command frame data layout (as shown in Figure 7): the write operation command frame is formed by 10, and every implication is as follows:
Start bit: expression begins transmission.
R/W: read-write sign, 0: write; 1: read.
RE WR:0: represent that this write operation is first operation, the I/O module only need latch this secondary data, does not export; 1: represent that this write operation is repetitive operation, the I/O module should compare this secondary data and latch data, as identical then output, returns correct information returning frame simultaneously, then returns error message as difference; This sign is mainly used in error correction.
A4-A0: module's address, from 0 to 31.
AA1, AA0: inside modules address.AA1, AA0 have following 4 kinds of combinations:
00: visit the 0th to the 7th passage;
01: visit the 8th to the 15th passage;
10: visit the 16th to the 23rd passage;
10: visit the 24th to the 31st passage.
Controller write operation data frame format (as shown in Figure 8): Frame finishes with position of rest immediately following in the back of command frame.After Frame sent and finishes, the I/O module changed accepting state into.
C) be high-impedance state on first clock bus after controller data frame I/O module rreturn value form (as shown in Figure 9): at b) sends and finishes, second clock I/O module should send rreturn value; Rreturn value should be exported at the clock negative edge.01 represents the write operation success, and other show wrong.
3, the 3rd universal serial bus adopts the 6Mbps full duplex synchronously from arbitrating communication mode, is applicable to the variety of protocol conversions module, as the protocol conversion module of various field bus protocols such as FF fieldbus, HART, PROFIBUS, Modbus.Can make the decentralised control station not only have general data acquisition and output function by protocol conversion module, also can support various standards or off-gauge bus protocol, strengthen the function at decentralised control station greatly.The decentralised control station of using this backboard has had the ability that substitutes middle-size and small-size DCS system from the system scale.
The 3rd universal serial bus has utilized the high-speed synchronous serial communication function of CPU, and added priority arbitration mechanism, realized the high speed full-duplex communication of I/O module and controller, and the data of module send and not need controller control, can judge bus idle state voluntarily before sending.The 3rd universal serial bus is made up of following 4 pairs of differential signals: CLK (clock signal), TXD (transmission of I/O module data), RXD (reception of I/O module data), BUSY (bus busy signal).Wherein:
CLK: synchronous clock is provided, produces by controller.
The TXD:I/O module data sends, and is received by controller, receives line with controller data and links to each other.
The RXD:I/O module data receives, and is sent by controller, sends line with controller data and links to each other.
BUSY: bus busy signal, before sending, the I/O module detects, and the bus free time then sends; When having a plurality of module requests to send simultaneously, determine which module to send earlier according to priority.
The standard compliant USART of the data communication format of the 3rd universal serial bus (USART) form.
The flow process that the priority arbitration of the 3rd universal serial bus is realized is as follows:
Elder generation's testbus busy signal when the I/O module sends data is detecting bus when busy, waits for and constantly detects; When detecting bus after the spare time, bus is made as busy, need several clock period during this.During this period of time, other I/O module still can detect BUSY=1 (bus spare time), thinks that also the idle also attempt of bus takies, and has at this moment just occurred competing and conflicting.According to priority order is given the timeslice of the different numbers of I/O module assignment, in the official hour sheet I/O module repeatedly the I/O module data in the testbus send line whether signal arranged, finish up to timeslice; Do not have signal can take bus if the I/O module data sends line at once, send line by the I/O module data and send start signal; If I/O module data transmission line has signal then represents to have the I/O module of other high priority to take, this I/O module withdraws from competition; The arbitration sequential chart as shown in figure 10.
The a period of time that BUSY is made as 0 after (bus is busy) is defined as the arbitration time, and the arbitration time span is (N-1) * Δ t, and wherein N is the I/O number of modules that participates in the competition on the bus, and Δ t is the length of a timeslice.According to priority order is given the timeslice of the different numbers of I/O module assignment, and the priority of each I/O module is by the address decision of I/O module, and address low priority more is high more.Suppose to have 3 I/O modules, the 1I/O module, the 2I/O module, the 3I/O module is installed in respectively on the slot of 0,1,2 three address of I/O backboard.1I/O module priority is the highest, and it needn't carry out timeslice test, directly sends start bit when idle detecting bus; 2I/O module priority is inferior high, detecting bus after the free time, timeslice cycle Δ t to be detected such as its needs, be high on the I/O module data transmission line in during Δ t always, be after wait acknowledge does not use bus than the 1I/O module of its high priority, the 2I/O module just can take bus, sends start signal; 3I/O module priority is minimum, it etc. 2 timeslice cycles 2 Δ t to be detected, have only when 1I/O module, 2I/O module do not take bus (the I/O module data sends line and remains height always), I/O module 2 just can take bus and send start signal.
Claims (7)
1. multi-serial bus passive real panel comprises:
-power supply backplane is electrically connected with other backboards, is used to install power module;
-controller back plate links to each other with I/O backboard and power supply backplane, is used to install controller module;
-I/O backboard is used to install the I/O module, with controller back plate, and power supply backplane link to each other; Described I/O backboard has: power path, backboard address shift circuit, module relative address form circuit, universal serial bus path;
-backboard extender is used to realize the connection of I/O backboard;
It is characterized in that: also comprise the terminal matching module, link to each other, be used for the terminal coupling of the inner difference string row bus of I/O backboard with terminal I/O backboard; The overall many universal serial bus technology that adopts of I/O backboard, low-frequency serial bus and middling speed universal serial bus Mixed Design, multiple universal serial bus is worked simultaneously; Be embodied in 3 kinds of universal serial bus paths of I/O backboard, 3 kinds of universal serial bus paths connect different I/O modules respectively, are specially:
1) the 1st universal serial bus adopts 1Mbps half-duplex asynchronous communication, has a pair of difference string row bus, and communication mode is 485 communication modes, and controller and I/O module communication are principal and subordinate's inquiry mode, and controller sends read-write requests, and the I/O module is returned corresponding response; The 1st universal serial bus is used for conventional low speed I/O module;
2) the 2nd universal serial bus adopts 6Mbps half-duplex synchronous communication; Have two pairs of difference string row bus, that is: a pair of transmitting synchronous clock that is used for, another is to being used to transmit data; The 2nd universal serial bus is realized the data transmission of controller and I/O module by programmable logic device (PLD); The 2nd universal serial bus is used for high-speed figure amount load module, digital quantity output module;
3) the 3rd universal serial bus adopts the 6Mbps full duplex synchronously from arbitrating communication mode, is applicable to the variety of protocol conversions module; The 3rd universal serial bus utilizes the high-speed synchronous serial communication function of central processing unit, adds priority arbitration mechanism simultaneously.
2. by the described multi-serial bus passive real panel of claim 1, it is characterized in that: wherein the described programmable logic device (PLD) of the 2nd universal serial bus is arranged in controller and I/O module, communicates according to the communication format of the 2nd universal serial bus.
3. by the described multi-serial bus passive real panel of claim 1, it is characterized in that: described the 2nd universal serial bus has two kinds of operator schemes, and its communication format is as follows:
1) controller read operation: be made up of command frame and Frame, controller sends command frame, I/O module return data frame;
2) controller write operation: be made of command frame, Frame, I/O rreturn value, controller sends command frame, Frame, and the I/O module sends rreturn value.
4. by the described multi-serial bus passive real panel of claim 1, it is characterized in that: described the 3rd universal serial bus specifically is made up of clock signal, the transmission of I/O module data, the reception of I/O module data, the busy four pairs of differential signals of bus, wherein:
Clock signal provides the data communication synchronous clock, is produced by controller;
The I/O module data sends signal and is received by controller, receives line with controller data and links to each other;
I/O module data received signal is sent by controller, sends line with controller data and links to each other;
Bus busy signal detects before the I/O module sends, and the bus free time then sends data; When having a plurality of module requests to send simultaneously, determine which module to send earlier according to priority.
5. by the described multi-serial bus passive real panel of claim 1, it is characterized in that: the priority arbitration mechanism realization flow of described the 3rd universal serial bus is as follows:
Elder generation's testbus busy signal when the I/O module sends data detecting bus when busy, is waited for and is also continued to detect; When detecting bus after the spare time, bus is made as busy, in the official hour sheet I/O module repeatedly the I/O module data in the testbus send line whether signal arranged, finish up to timeslice; Do not have signal to take bus if the I/O module data sends line at once, send line by the I/O module data and send start signal; If I/O module data transmission line has signal then represents to have the I/O module of other high priority will take bus, this I/O module withdraws from competition; A period of time that bus is made as after hurrying is defined as the arbitration time, and according to priority order is given the timeslice of the different numbers of I/O module assignment, and the priority of each I/O module is by the address decision of module; The highest I/O module of priority directly sends start bit when idle detecting bus; Priority is detecting bus after the free time for time high I/O module, etc. a timeslice cycle to be detected, to send on the line be high to the I/O module data always in during timeslice, and promptly wait acknowledge does not use after the bus than the I/O module of its high priority and takies bus, the transmission start signal under the situation; When the number of I/O module is 3, the I/O module that priority is minimum, wait 2 timeslice cycles to be detected, have only when the I/O of high priority module, priority do not take bus for time high I/O module, promptly send line at the I/O module data and remain under the situation of noble potential always, the I/O module that priority is minimum just can take bus and send start signal.
6. by the described multi-serial bus passive real panel of claim 5, it is characterized in that: described arbitration time span is (N-1) * Δ t, and wherein N is the I/O number of modules that participates in the competition on the 3rd universal serial bus, and Δ t is the cycle of a timeslice.
7. by the described multi-serial bus passive real panel of claim 5, it is characterized in that: the address of described I/O module low priority more is high more.
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| CN102934351B (en) * | 2011-04-20 | 2016-08-17 | 中山大洋电机制造有限公司 | A kind of daughter circuit board for conversion of interface signals of electronic commutation motor |
| CN102508456B (en) * | 2011-09-29 | 2013-12-18 | 东南大学 | Backplane bus type structure of vibration monitoring and protecting device and communication control method thereof |
| CN102546141B (en) * | 2012-02-20 | 2015-02-18 | 杭州海康威视系统技术有限公司 | 485 bus system and asynchronous half-duplex communication method thereof |
| CN103116564B (en) * | 2013-03-11 | 2015-06-24 | 武汉邮电科学研究院 | Time slot multiplexing single two-way backplane bus and redundancy protective method thereof |
| CN104301453A (en) * | 2014-10-21 | 2015-01-21 | 许继电气股份有限公司 | Intelligent device address coding method based on special setting communication |
| CN104731007A (en) * | 2015-03-13 | 2015-06-24 | 沈阳中科博微自动化技术有限公司 | Backboard communication assembly and communication method for function security PLC |
| CN110442097B (en) * | 2019-07-30 | 2024-03-29 | 南京国电南自维美德自动化有限公司 | Device and method for automatically identifying module address in distributed control system |
| CN113051204A (en) * | 2019-12-27 | 2021-06-29 | 中车大连电力牵引研发中心有限公司 | Serial backplane bus communication method and system |
| CN112383462B (en) * | 2020-11-13 | 2022-05-24 | 新华三技术有限公司合肥分公司 | Network device and bus configuration method |
| CN112882424A (en) * | 2021-01-27 | 2021-06-01 | 武汉中元华电科技股份有限公司 | Data acquisition system and method for power system |
| CN114047731B (en) * | 2021-11-08 | 2023-01-24 | 西安热工研究院有限公司 | Distributed control system IO module hardware address self-adaptive identification method and system |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010049801A1 (en) * | 2000-05-23 | 2001-12-06 | Berke Stuart Allen | Dual-ported operator control panel with automatic failover |
| US20020112106A1 (en) * | 2000-12-15 | 2002-08-15 | Henehan Burke S. | Backplane physical layer controller with an internal bus reset |
| US20040131054A1 (en) * | 1999-06-03 | 2004-07-08 | Fujitsu Network Communications, Inc., A California Corporation | Serialized bus communication and control architecture |
| US20050081100A1 (en) * | 2003-09-26 | 2005-04-14 | Xin Zeng | System and method for automatically initializing and diagnosing backplanes of electronic devices |
-
2005
- 2005-06-29 CN CNB2005100467787A patent/CN100414465C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040131054A1 (en) * | 1999-06-03 | 2004-07-08 | Fujitsu Network Communications, Inc., A California Corporation | Serialized bus communication and control architecture |
| US20010049801A1 (en) * | 2000-05-23 | 2001-12-06 | Berke Stuart Allen | Dual-ported operator control panel with automatic failover |
| US20020112106A1 (en) * | 2000-12-15 | 2002-08-15 | Henehan Burke S. | Backplane physical layer controller with an internal bus reset |
| US20050081100A1 (en) * | 2003-09-26 | 2005-04-14 | Xin Zeng | System and method for automatically initializing and diagnosing backplanes of electronic devices |
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