CN100409201C - First-in first-out type storage based on RAM and FPGA and its control method - Google Patents
First-in first-out type storage based on RAM and FPGA and its control method Download PDFInfo
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- CN100409201C CN100409201C CNB2005100099569A CN200510009956A CN100409201C CN 100409201 C CN100409201 C CN 100409201C CN B2005100099569 A CNB2005100099569 A CN B2005100099569A CN 200510009956 A CN200510009956 A CN 200510009956A CN 100409201 C CN100409201 C CN 100409201C
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Abstract
The present invention relates to a first-in first-out (FIFO) type memory based on an RAM and an FPGA and a control method thereof, and the present invention relates to the technical field of memories. The present invention solves the problem that the existing FIFO memory has a small memory capacity and has a high price. A data address bus end of a first RIM random access memory (1) is connected with a first bus end of an FPGA programmable logic matrix (3), and a data address bus end of a second RIM random access memory (2) is connected with a second bus end of the FPGA programmable logic matrix (3). A read-write control signal input end of the first RIM random access memory (1) is connected with a first read-write control signal output end of the FPGA programmable logic matrix (3), and a read-write control signal input end of the second RIM random access memory (2) is connected with a second read-write control signal output end of the FPGA programmable logic matrix (3). The left side of the FPGA programmable logic matrix (3) is a data output bus end, and the right side of the FPGA programmable logic matrix (3) is a data input bus end. The control method of the FPGA programmable logic matrix (3) has the steps that the data input from the data bus end of the right side of the FPGA programmable logic matrix (3) is respectively stored into the first RIM random access memory (1) or the second RIM random access memory (2); after the data in the first RIM random access memory (1) or the second RIM random access memory (2) is read, the data the second RIM random access memory (2) or the first RIM random access memory (1) is read, and the data is output from the data bus end of the left side of the FPGA programmable logic matrix (3). The present invention can replace the existing FIFO, and has the advantages of large capacity, high speed and low price.
Description
Technical field:
What the present invention relates to is the memory technology field, specifically is a kind of first-in first-out type storer and control method thereof based on RAM and FPGA.
Background technology:
The first-in first-out type storeies (FIFO) that adopt as buffer unit more in the available data communication (transmission).And the memory capacity of first-in first-out type storer (FIFO) is very little, its price is but very expensive, want to increase memory capacity and must use high capacity and expensive first-in first-out type storer (FIFO), make that its cost is huge to be increased, so just limited the fast development and the popularization of data communication technology.
Summary of the invention:
The purpose of this invention is to provide a kind of first-in first-out type storer and control method thereof based on RAM and FPGA.It is very little that the present invention can solve existing first-in first-out type storer (FIFO) memory capacity, the problem that its price is but very expensive.It is made up of a RAM random access memory 1, the 2nd RAM random access memory 2, FPGA FPGA (Field Programmable Gate Array) matrix 3; The data address output input bus end of the one RAM random access memory 1 connects the first data address input/output bus end of FPGA FPGA (Field Programmable Gate Array) matrix 3, the data address output input bus end of the 2nd RAM random access memory 2 connects the second data address input/output bus end of FPGA FPGA (Field Programmable Gate Array) matrix 3, the read-write control signal input end of the one RAM random access memory 1 connects the first read-write control signal output terminal of FPGA FPGA (Field Programmable Gate Array) matrix 3, the read-write control signal input end of the 2nd RAM random access memory 2 connects the second reading write control signal output terminal of FPGA FPGA (Field Programmable Gate Array) matrix 3, the left side of FPGA FPGA (Field Programmable Gate Array) matrix 3 is the data-out bus end, and the right side of FPGA FPGA (Field Programmable Gate Array) matrix 3 is the data input bus (DIB) end; After in a RAM random access memory 1, storing the data of a constant volume, FPGA FPGA (Field Programmable Gate Array) matrix 3 is controlled a RAM random access memory 1 by the first read-write control signal output terminal and is in the state of reading, and controls the 2nd RAM random access memory 2 by second reading write control signal output terminal and is in the state of writing; When the data read in the RAM random access memory 1 is intact, FPGA FPGA (Field Programmable Gate Array) matrix 3 is controlled a RAM random access memory (1) by the first read-write control signal output terminal and is in the state of writing, and controls the 2nd RAM random access memory (2) by second reading write control signal output terminal and is in the state of reading; When the data read in the 2nd RAM random access memory 2 is intact, FPGA FPGA (Field Programmable Gate Array) matrix 3 is controlled a RAM random access memory 1 by the first read-write control signal output terminal and is in the state of reading, and controls the 2nd RAM random access memory 2 by second reading write control signal output terminal and is in the state of writing.
The internal control method step of its FPGA FPGA (Field Programmable Gate Array) matrix 3 is: when FPGA FPGA (Field Programmable Gate Array) matrix 3 right side data input bus (DIB) ends have the data input, FPGA FPGA (Field Programmable Gate Array) matrix 3 is controlled a RAM random access memory 1 by the first read-write control signal output terminal and is in the state of writing, control the 2nd RAM random access memory 2 by second reading write control signal output terminal and be in the state of reading, and will write in the RAM random access memory 1 001 after the above-mentioned data processing; After in a RAM random access memory 1, storing the data of a constant volume, FPGA FPGA (Field Programmable Gate Array) matrix 3 is controlled a RAM random access memory 1 by the first read-write control signal output terminal and is in the state of reading, control the 2nd RAM random access memory 2 by second reading write control signal output terminal and be in the state of writing, FPGA FPGA (Field Programmable Gate Array) matrix 3 sense data and handle the left data output bus end output of back from a RAM random access memory 1 from FPGA FPGA (Field Programmable Gate Array) matrix 3, FPGA FPGA (Field Programmable Gate Array) matrix 3 writes in the 2nd RAM random access memory 2 002 with the data of its right side data input bus (DIB) end input simultaneously; When the data read in the RAM random access memory 1 is intact, FPGA FPGA (Field Programmable Gate Array) matrix 3 is controlled a RAM random access memory 1 by the first read-write control signal output terminal and is in the state of writing, and controls the 2nd RAM random access memory 2 by second reading write control signal output terminal and is in the state of reading 003; FPGA FPGA (Field Programmable Gate Array) matrix 3 sense data and handle the left data output bus end output of back from the 2nd RAM random access memory 2 from FPGA FPGA (Field Programmable Gate Array) matrix 3, FPGA FPGA (Field Programmable Gate Array) matrix 3 continues to write in the RAM random access memory 1 004 with the data of its right side data input bus (DIB) end input simultaneously; When the data read in the 2nd RAM random access memory 2 is intact, FPGA FPGA (Field Programmable Gate Array) matrix 3 is controlled a RAM random access memory 1 by the first read-write control signal output terminal and is in the state of reading, control the 2nd RAM random access memory 2 by second reading write control signal output terminal and be in the state of writing, FPGA FPGA (Field Programmable Gate Array) matrix 3 sense data from a RAM random access memory 1 is also handled the left data output bus end output of back from FPGA FPGA (Field Programmable Gate Array) matrix 3, and the data that while FPGA FPGA (Field Programmable Gate Array) matrix 3 is imported its right side data input bus (DIB) end write in the 2nd RAM random access memory 2 and return operation 003 step 005.The present invention can replace existing first-in first-out type storer (FIFO), and its capacity is big, price is low, speed is high, and the advantage that has simple in structure, stable performance, makes easily.
Description of drawings:
Fig. 1 is an one-piece construction synoptic diagram of the present invention, and Fig. 2 is the schematic flow sheet of FPGA FPGA (Field Programmable Gate Array) matrix 3 internal control method steps among the present invention.
Embodiment:
In conjunction with Fig. 1, Fig. 2 present embodiment is described, it is made up of a RAM random access memory 1, the 2nd RAM random access memory 2, FPGA FPGA (Field Programmable Gate Array) matrix 3; The data address output input bus end of the one RAM random access memory 1 connects the first data address input/output bus end of FPGA FPGA (Field Programmable Gate Array) matrix 3, the data address output input bus end of the 2nd RAM random access memory 2 connects the second data address input/output bus end of FPGA FPGA (Field Programmable Gate Array) matrix 3, the read-write control signal input end of the one RAM random access memory 1 connects the first read-write control signal output terminal of FPGA FPGA (Field Programmable Gate Array) matrix 3, the read-write control signal input end of the 2nd RAM random access memory 2 connects the second reading write control signal output terminal of FPGA FPGA (Field Programmable Gate Array) matrix 3, the left side of FPGA FPGA (Field Programmable Gate Array) matrix 3 is the data-out bus end, and the right side of FPGA FPGA (Field Programmable Gate Array) matrix 3 is the data input bus (DIB) end.The model that the one RAM random access memory 1, the 2nd RAM random access memory 2 are selected for use is CY7C1049CV33, and the model that FPGA FPGA (Field Programmable Gate Array) matrix is selected for use is the EP1C6Q240C8 of Cyclone company.The internal control method step of FPGA FPGA (Field Programmable Gate Array) matrix 3 is: when FPGA FPGA (Field Programmable Gate Array) matrix 3 right side data input bus (DIB) ends have the data input, FPGA FPGA (Field Programmable Gate Array) matrix 3 is controlled a RAM random access memory 1 by the first read-write control signal output terminal and is in the state of writing, control the 2nd RAM random access memory 2 by second reading write control signal output terminal and be in the state of reading, and will write in the RAM random access memory 1 001 after the above-mentioned data processing; After in a RAM random access memory 1, storing the data of a constant volume, FPGA FPGA (Field Programmable Gate Array) matrix 3 is controlled a RAM random access memory 1 by the first read-write control signal output terminal and is in the state of reading, control the 2nd RAM random access memory 2 by second reading write control signal output terminal and be in the state of writing, FPGA FPGA (Field Programmable Gate Array) matrix 3 sense data and handle the left data output bus end output of back from a RAM random access memory 1 from FPGA FPGA (Field Programmable Gate Array) matrix 3, FPGA FPGA (Field Programmable Gate Array) matrix 3 writes in the 2nd RAM random access memory 2 002 with the data of its right side data input bus (DIB) end input simultaneously; When the data read in the RAM random access memory 1 is intact, FPGA FPGA (Field Programmable Gate Array) matrix 3 is controlled a RAM random access memory 1 by the first read-write control signal output terminal and is in the state of writing, and controls the 2nd RAM random access memory 2 by second reading write control signal output terminal and is in the state of reading 003; FPGA FPGA (Field Programmable Gate Array) matrix 3 sense data and handle the left data output bus end output of back from the 2nd RAM random access memory 2 from FPGA FPGA (Field Programmable Gate Array) matrix 3, FPGA FPGA (Field Programmable Gate Array) matrix 3 continues to write in the RAM random access memory 1 004 with the data of its right side data input bus (DIB) end input simultaneously; When the data read in the 2nd RAM random access memory 2 is intact, FPGA FPGA (Field Programmable Gate Array) matrix 3 is controlled a RAM random access memory 1 by the first read-write control signal output terminal and is in the state of reading, control the 2nd RAM random access memory 2 by second reading write control signal output terminal and be in the state of writing, FPGA FPGA (Field Programmable Gate Array) matrix 3 sense data from a RAM random access memory 1 is also handled the left data output bus end output of back from FPGA FPGA (Field Programmable Gate Array) matrix 3, and the data that while FPGA FPGA (Field Programmable Gate Array) matrix 3 is imported its right side data input bus (DIB) end write in the 2nd RAM random access memory 2 and return operation 003 step 005.
Claims (2)
1. based on the first-in first-out type storer of RAM and FPGA, it is characterized in that it is made up of a RAM random access memory (1), the 2nd RAM random access memory (2), FPGA FPGA (Field Programmable Gate Array) matrix (3); The data address output input bus end of the one RAM random access memory (1) connects the first data address input/output bus end of FPGA FPGA (Field Programmable Gate Array) matrix (3), the data address output input bus end of the 2nd RAM random access memory (2) connects the second data address input/output bus end of FPGA FPGA (Field Programmable Gate Array) matrix (3), the read-write control signal input end of the one RAM random access memory (1) connects the first read-write control signal output terminal of FPGA FPGA (Field Programmable Gate Array) matrix (3), the read-write control signal input end of the 2nd RAM random access memory (2) connects the second reading write control signal output terminal of FPGA FPGA (Field Programmable Gate Array) matrix (3), the left side of FPGA FPGA (Field Programmable Gate Array) matrix (3) is the data-out bus end, and the right side of FPGA FPGA (Field Programmable Gate Array) matrix (3) is the data input bus (DIB) end; After in a RAM random access memory (1), storing the data of a constant volume, FPGA FPGA (Field Programmable Gate Array) matrix (3) is controlled a RAM random access memory (1) by the first read-write control signal output terminal and is in the state of reading, and controls the 2nd RAM random access memory (2) by second reading write control signal output terminal and is in the state of writing; When the data read in the RAM random access memory (1) is intact, FPGA FPGA (Field Programmable Gate Array) matrix (3) is controlled a RAM random access memory (1) by the first read-write control signal output terminal and is in the state of writing, and controls the 2nd RAM random access memory (2) by second reading write control signal output terminal and is in the state of reading; When the data read in the 2nd RAM random access memory (2) is intact, FPGA FPGA (Field Programmable Gate Array) matrix (3) is controlled a RAM random access memory (1) by the first read-write control signal output terminal and is in the state of reading, and controls the 2nd RAM random access memory (2) by second reading write control signal output terminal and is in the state of writing.
2. based on the control method of the first-in first-out type storer of RAM and FPGA, the internal control method step that it is characterized in that FPGA FPGA (Field Programmable Gate Array) matrix (3) is: when FPGA FPGA (Field Programmable Gate Array) matrix (3) right side data input bus (DIB) end has the data input, FPGA FPGA (Field Programmable Gate Array) matrix (3) is controlled a RAM random access memory (1) by the first read-write control signal output terminal and is in the state of writing, control the 2nd RAM random access memory (2) by second reading write control signal output terminal and be in the state of reading, and will write after the above-mentioned data processing in the RAM random access memory (1) (001); After in a RAM random access memory (1), storing the data of a constant volume, FPGA FPGA (Field Programmable Gate Array) matrix (3) is controlled a RAM random access memory (1) by the first read-write control signal output terminal and is in the state of reading, control the 2nd RAM random access memory (2) by second reading write control signal output terminal and be in the state of writing, FPGA FPGA (Field Programmable Gate Array) matrix (3) sense data from a RAM random access memory (1) is also handled the left data output bus end output of back from FPGA FPGA (Field Programmable Gate Array) matrix (3), and the data that while FPGA FPGA (Field Programmable Gate Array) matrix (3) is imported its right side data input bus (DIB) end write in the 2nd RAM random access memory (2) (002); When the data read in the RAM random access memory (1) is intact, FPGA FPGA (Field Programmable Gate Array) matrix (3) is controlled a RAM random access memory (1) by the first read-write control signal output terminal and is in the state of writing, and controls the 2nd RAM random access memory (2) by second reading write control signal output terminal and is in the state of reading (003); FPGA FPGA (Field Programmable Gate Array) matrix (3) sense data from the 2nd RAM random access memory (2) is also handled the left data output bus end output of back from FPGA FPGA (Field Programmable Gate Array) matrix (3), and the data that while FPGA FPGA (Field Programmable Gate Array) matrix (3) is imported its right side data input bus (DIB) end continue to write in the RAM random access memory (1) (004); When the data read in the 2nd RAM random access memory (2) is intact, FPGA FPGA (Field Programmable Gate Array) matrix (3) is controlled a RAM random access memory (1) by the first read-write control signal output terminal and is in the state of reading, control the 2nd RAM random access memory (2) by second reading write control signal output terminal and be in the state of writing, FPGA FPGA (Field Programmable Gate Array) matrix (3) sense data from a RAM random access memory (1) is also handled the left data output bus end output of back from FPGA FPGA (Field Programmable Gate Array) matrix (3), and the data that while FPGA FPGA (Field Programmable Gate Array) matrix (3) is imported its right side data input bus (DIB) end write in the 2nd RAM random access memory (2) and return operation (003) step (005).
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| CNB2005100099569A CN100409201C (en) | 2005-04-29 | 2005-04-29 | First-in first-out type storage based on RAM and FPGA and its control method |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1094525A (en) * | 1993-04-19 | 1994-11-02 | 电子科技大学 | A kind of high-capacity and high-speed data acquisition caching method and equipment |
| CN1147676A (en) * | 1994-08-05 | 1997-04-16 | 美国电报电话公司 | First-in first-out memory |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1094525A (en) * | 1993-04-19 | 1994-11-02 | 电子科技大学 | A kind of high-capacity and high-speed data acquisition caching method and equipment |
| CN1147676A (en) * | 1994-08-05 | 1997-04-16 | 美国电报电话公司 | First-in first-out memory |
Non-Patent Citations (2)
| Title |
|---|
| 基于FPGA和PCI总线的数据采集板设计. 何文波，孙德宝，吴新建.微机发展，第14卷第11期. 2004 |
| 基于FPGA和PCI总线的数据采集板设计. 何文波，孙德宝，吴新建.微机发展，第14卷第11期. 2004 * |
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