CN212084122U - NVMe controller - Google Patents

Abstract

The utility model discloses a NVMe controller, including order queue processing module, completion queue processing module, data cache module, access module, register module, random access memory, memory module, high-speed serial bus and central processing unit, order queue processing module accomplish queue processing module the data cache module the access module all is connected with high-speed serial bus electricity, the access module with the central processing unit electricity is connected, random access memory with order queue processing module electricity is connected, memory module with the data cache module electricity is connected. The utility model relates to a NVMe controller has realized the read-write operation to the register module based on current NVMe standard protocol, provides a set of simple external interface and supplies the use to higher read-write bandwidth has been reached.

Description

NVMe controller

Technical Field

The utility model relates to the field of electronic technology, especially, relate to a NVMe controller.

Background

The HDD and the early register module mostly use the SATA interface, and the AHCI (advanced Host Controller interface) protocol is used, in the HDD era or early register module, the AHCI protocol and the SATA interface can sufficiently meet the performance requirement of the system, but with the development of the underlying flash Memory technology, the performance of the register module disk is greatly improved, and the AHCI protocol and the SATA interface cannot meet the requirement of the current register module performance.

SUMMERY OF THE UTILITY MODEL

The utility model aims at providing a NVMe controller for solving above-mentioned problem.

The utility model discloses a following technical scheme realizes above-mentioned purpose:

an NVMe controller comprises a command queue processing module, a completion queue processing module, a data cache module, an access module, a register module, a random access memory, a memory module, a high-speed serial bus and a central processing unit, wherein the command queue processing module, the completion queue processing module, the data cache module and the access module are electrically connected with the high-speed serial bus, the access module is electrically connected with the central processing unit, the random access memory is electrically connected with the command queue processing module, and the memory module is electrically connected with the data cache module.

Specifically, the command queue processing module comprises an SQ management module, an SQ cache module and a prplist module, and the SQ management module, the SQ cache module and the prplist module are electrically connected;

the SQ management module receives the command instruction and packages the command instruction into a read-write command specified by an NVMe protocol to complete the read-write operation of the register module data;

the SQ cache module is used for caching read-write commands;

the prplist module is used for caching prplist data;

the random access memory is used for storing read-write commands and prplist data.

Specifically, the data cache module comprises a data processing module and a cache module, wherein the data processing module is electrically connected with the high-speed serial bus through the cache module, and the data processing module is electrically connected with the memory module;

the memory module is used for storing the data written or read by the register module;

the data processing module is used for converting the non-aligned read-write command sent by the register into an aligned read-write command supported by the memory module;

the cache module is used for prefetching data, a write channel of the cache module comprises 5 groups of cache FIFOs, and a read channel of the cache module comprises 6 groups of cache FIFOs.

Preferably, the access module is electrically connected to the central processor via a locabus bus.

The beneficial effects of the utility model reside in that:

the utility model relates to a NVMe controller has realized the read-write operation to the register module based on current NVMe standard protocol, provides a set of simple external interface and supplies the use to higher read-write bandwidth has been reached.

Drawings

Fig. 1 is a schematic structural diagram of an NVMe controller according to the present invention;

fig. 2 is a schematic diagram of a command queue processing module according to the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiment is only one embodiment of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

To make the purpose, technical solution and advantages of the present application more clear, the present invention will be further described with reference to fig. 1 and 2:

an NVMe controller comprises a command queue processing module SQ, a completion queue processing module CQ, a data cache module, an access module CPU _ accrss _ regs, a register module SSD, a random access memory RAM, a memory module DDR, a high-speed serial bus PCIE and a central processing unit CPU, wherein the command queue processing module SQ, the completion queue processing module CQ, the data cache module and the access module CPU _ accrss _ regs are all electrically connected with the high-speed serial bus PCIE, the access module CPU _ accrss _ regs is electrically connected with the central processing unit CPU, the random access memory RAM is electrically connected with the command queue processing module, and the memory module DDR is electrically connected with the data cache module.

The command queue processing module SQ comprises an SQ management module, an SQ cache module cache and a prplist module, and the SQ management module, the SQ cache module cache and the prplist module are electrically connected;

the SQ management module receives the command instruction, packages the command instruction into a read-write command specified by an NVMe protocol, and completes read-write operation on SSD data of the register module; the SQ cache module is used for caching read-write commands; the prplist module is used for caching prplist data; the random access memory RAM is used to store read and write commands and prplist data. The command queue processing module SQ stores both the command and the prplist in the RAM without writing them into the RAM, mainly to reduce the read latency

The command queue processing module SQ provides a group of self-defined command interfaces including a command ID, a memory address, a logic address of the register module SSD, a data size, a command type, an enable signal and a to-be-full signal, receives a command from an external module, packages the command into a read-write command specified by an NVMe protocol, and completes read-write operation of data of the register module SSD.

The completion queue processing module CQ has a simple structure, is mainly used for receiving and analyzing the command response returned by the register module SSD, judging whether the corresponding command has an error or not, and writing the extracted required command information into an FIFO (first in first out) for a Central Processing Unit (CPU) to read and analyze the error for the command with the error; and if the command is correct, the command ID is returned to the command queue processing module SQ for analysis and management.

The data cache module comprises a data processing module DQ and a cache module cache, wherein the data processing module DQ is electrically connected with the PCIE through the cache module cache, and the data processing module DQ is electrically connected with the DDR; the memory module DDR is used for storing data written or read by the register module SSD;

the data processing module DQ is used for converting the unaligned read-write command sent by the register into an aligned read-write command supported by the memory module DDR; the cache module cache is used for prefetching data, a write channel of the cache module cache comprises 5 groups of cache FIFOs, and a read channel of the cache module cache comprises 6 groups of cache FIFOs.

The data cache module is connected with the high-speed serial bus PCIE and receives a read-write command from the register module SSD, for the memory module DDR, the read-write command is operated according to 32-byte alignment, and the data cache module needs to convert a non-alignment command sent by the register module SSD into a corresponding alignment command so as to correctly access the memory module DDR. In order to guarantee the read-write bandwidth, the prefetch operation is carried out, a cache module is set, and because the data of 4KB of the SSD of the register module is sequential, the FIFO is adopted to replace a random access memory RAM, so that the logic operation is simplified.

Therefore, the delay of reading data from the FIFO at the data side of the data reading processing module DQ is far less than the delay of reading data from the memory module DDR; on the data side of the data writing processing module DQ, data is written in a burst mode when being written into the FIFO, and the utilization efficiency of DDR bandwidth of the memory module is improved. Meanwhile, the possibly out-of-order of a plurality of 4KB read-write commands initiated by the register module SSD is considered, so a plurality of FIFOs are designed to cache read-write data for order preservation. For SQ and prplist and other non-data processing block DQ data, there is another FIFO for storage.

Preferably, the access module CPU _ accrss _ regs is electrically connected to the central processing unit CPU via a locabus bus.

The communication protocol is customized for the operation of the central processing unit CPU initiating the read-write register module SSD, the read-write command initiated by the central processing unit CPU can be written into the FIFO, and the logic can send the command to the high-speed serial bus PCIE to complete the read-write operation of the register module SSD.

In the following description, references to "one embodiment," "an embodiment," "one example," "an example," etc., indicate that the embodiment or example so described may include a particular feature, structure, characteristic, property, element, or limitation, but every embodiment or example does not necessarily include the particular feature, structure, characteristic, property, element, or limitation. Moreover, repeated use of the phrase "in accordance with an embodiment of the present application" although it may possibly refer to the same embodiment, does not necessarily refer to the same embodiment.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (4)

1. An NVMe controller characterized by: the system comprises a command queue processing module, a completion queue processing module, a data cache module, an access module, a register module, a random access memory, a memory module, a high-speed serial bus and a central processing unit, wherein the command queue processing module, the completion queue processing module, the data cache module and the access module are all electrically connected with the high-speed serial bus, the access module is electrically connected with the central processing unit, the random access memory is electrically connected with the command queue processing module, and the memory module is electrically connected with the data cache module.

2. An NVMe controller according to claim 1, wherein: the command queue processing module comprises an SQ management module, an SQ cache module and a prplist module, and the SQ management module, the SQ cache module and the prplist module are electrically connected;

the SQ management module receives the command instruction and packages the command instruction into a read-write command specified by an NVMe protocol to complete the read-write operation of the register module data;

the SQ cache module is used for caching read-write commands;

the prplist module is used for caching prplist data;

the random access memory is used for storing read-write commands and prplist data.

3. An NVMe controller according to claim 1, wherein: the data cache module comprises a data processing module and a cache module, the data processing module is electrically connected with the high-speed serial bus through the cache module, and the data processing module is electrically connected with the memory module;

the memory module is used for storing the data written or read by the register module;

the data processing module is used for converting the non-aligned read-write command sent by the register into an aligned read-write command supported by the memory module;

the cache module is used for prefetching data, a write channel of the cache module comprises 5 groups of cache FIFOs, and a read channel of the cache module comprises 6 groups of cache FIFOs.

4. An NVMe controller according to claim 1, wherein: the access module is electrically connected with the central processing unit through a locabus.

Images