CN100399752C

CN100399752C - System and method for testing digital communication signal processing single board

Info

Publication number: CN100399752C
Application number: CNB2004100443063A
Authority: CN
Inventors: 文凯
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2004-05-21
Filing date: 2004-05-21
Publication date: 2008-07-02
Anticipated expiration: 2024-05-21
Also published as: CN1700662A

Abstract

The present invention relates to a testing technology of an electronic communication system, particularly to a testing system for a processing single board of a digital communication signal and a method thereof. Thus, hardware equipment for testing and corresponding software are reduced, tests are simpler, fault positioning is more accurate and convenient and relative tests of peripheral equipment which comprises an EPLD can be very conveniently carried out. The testing system for a processing single board of a digital communication signal comprises a processing single board of a digital communication signal. The single board comprises an embedded type integrated communication controller, a first memory, peripheral equipment and a testing terminal which is connected with the single board via a communication port and is used for displaying a test result output by the single board and for providing an interactive interface of test control to a tester, wherein test software is stored in the first memory; when the single board is started, the test software in the first memory is operated by the embedded type integrated communication controller so as to test the peripheral equipment and output the test result to the testing terminal.

Description

Testing system and method for digital communication signal processing single board

Technical Field

The invention relates to a test technology of an electronic communication system, in particular to a technology for testing a peripheral of a single board.

Background

PowerPC is a Central Processing Unit (CPU) chip developed by Motorola, Inc., and is mostly used in embedded systems.

In the field of Communications, embedded Integrated communication controllers (abbreviated as "powerquics") based on PowerPC architecture are widely used, such as MPC860 communication controllers. MPC860 incorporates a microprocessor and some of the usual peripheral components of the control domain within it, supporting any form of memory, particularly suitable for use in communication products. MPC860 has been widely used in a digital communication signal processing board, such as a microcellular Frame processing Unit (MFU) of a Base Transceiver Station (BTS). For convenience of explanation, the digital communication signal processing board based on the embedded integrated communication controller is described below by taking an MFU board based on the MPC860 as an example. It will be appreciated by those skilled in the art that this does not affect the understanding and spirit of the invention.

The MPC860 integrates two processing modules, one of which is an embedded PowerPC core and the other of which is a Communication Processor Module (CPM). The CPM supports four Serial Communication Controllers (SCC), and supports standard protocols such as Universal asynchronous receiver/Transmitter (UART). The UART protocol is used for data communication at the data link layer with the characteristics of simplicity, convenience, and low speed.

The peripheral of the MFU single board based on the MPC860 comprises: synchronous dynamic Memory (SDRAM), Flash Memory (Flash), Erasable Programmable Logic Device (EPLD), and Digital Signal Processor (DSP). The number of the DSPs may be multiple, for example, a Channel Codec DSP (Channel Codec DSP, abbreviated as "CHDSP") or a General Packet radio service DSP (General Packet radio service DSP, abbreviated as "GDSP").

In order to detect whether the MPC 860-based MFU is working properly, there are two methods, the first is to test the MFU board equipment used in production, and the second is to install the MFU board running the formal program on the BTS, such as a 3001C complete machine, and observe whether it is working properly. When the MFU single board with problems is tested or a specific peripheral of the single board needs to be tested, because the MFU single board peripheral needs to be tested independently, such as Flash, SDRAM, GDSP and CHDSP, the mode of installing the MFU single board on a 3001C for testing cannot meet the requirement, and the mode of installing the MFU single board for testing needs to be adopted.

The existing MFU single board equipment test for testing the MFU single board adopts a clamp manner, and a test schematic diagram is shown in fig. 1.

Hardware equipment required by MFU single-board equipment test comprises: the test system comprises a test terminal, an equipment control board, a microcellular operation and Maintenance Unit (MMU) tool board and an MFU single board to be tested; the software required for testing includes: MFU equipment test software running on a test terminal, MMU tool board software running on an MMU tool board, and MFU equipment test software running on an MFU single board. The test terminal may be a general Personal Computer (PC).

The test terminal controls the equipment control board through a serial port (COM), controls the MMU tool board through a microcellular Maintenance Interface (MMI for short), controls the MFU single board through the MMU tool board to send a transparent command, and respectively generates a signal required by the test or detects a signal output by the MFU single board to realize the test of the MFU single board.

In practical applications, the above scheme has the following problems: the existing test scheme for testing a digital communication signal processing single board based on an embedded integrated communication controller, such as an MFU single board, has more requirements on testing hardware and software, has higher test cost and complexity, cannot perform fault location, and cannot perform relevant tests on EPLD.

The main reason for this is that the existing testing scheme of the digital communication signal processing board based on the embedded integrated communication controller adopts a clamp method, needs more hardware devices and corresponding software running on different hardware devices, needs a testing tool board and a board to be tested to communicate normally during testing, all testing items cannot be performed when the testing tool board and the board to be tested cannot be linked, resulting in higher testing cost and complexity, and does not provide fault location information and relevant testing of EPLD when the external device has a fault by adopting the clamp testing.

Disclosure of Invention

In view of the above, the main objective of the present invention is to provide a testing system and method for a digital communication signal processing board, so that hardware devices and corresponding software for testing are reduced, testing is simpler, fault location is more accurate and convenient, and related testing of peripheral devices including EPLD can be conveniently performed.

In order to achieve the above object, the present invention provides a test system for a digital communication signal processing board, which comprises a digital communication signal processing board, wherein the board comprises an embedded integrated communication controller, a first memory and a peripheral device, and the test system further comprises

The test terminal is connected with the single board through a communication port and is used for displaying the test result output by the single board and providing an interactive interface for controlling the test for a tester;

wherein, the first memory stores testing software;

the peripheral comprises one or the combination of an erasable programmable logic device and a digital signal processor;

the embedded integrated communication controller operates the test software in the first memory to load files on the erasable programmable logic device when the single board is started, judges whether the loading is successful or not, and outputs a test result to the test terminal according to the loading result and the loading result; or,

and the embedded integrated communication controller runs the test software in the first memory to load the code of the digital signal processor through a host interface of the digital signal processor when the single board is started, and outputs a test result to the test terminal according to the loaded result.

The peripheral further comprises one or a combination of a synchronous dynamic memory and a flash memory.

And the test terminal also displays the fault detailed information and the fault positioning help information from the digital communication signal processing single board.

The single board may be a micro cell frame processing unit.

The invention also provides a testing method of the digital communication signal processing single board, which comprises the following steps:

a, running test software stored on the single board when the single board is started;

b, the testing software tests the peripheral equipment of the single board, the peripheral equipment is set as an erasable programmable logic device, and the testing of the erasable programmable logic device comprises the following steps:

b11 loading files to the erasable programmable logic device and judging whether loading is successful, if so, entering step B12, otherwise, outputting a test failure message;

b12 detecting whether the file in the erasable programmable logic device is correct, if yes, outputting a test success message, otherwise, outputting a test failure message;

and C, the single board sends the test result to the test terminal.

b, the testing software tests the peripheral equipment of the single board, the peripheral equipment is a digital signal processor, and the testing of the digital signal processor comprises the following steps:

b11 loading the code of the digital signal processor through the host interface of the digital signal processor;

b12 outputs test information including: the information whether the communication between the digital signal processor and other peripheral equipment is normal or not, the information whether the interrupt input signal of the digital signal processor is normal or not, the information whether the code loading of the digital signal processor is successful or not and the information whether the formal running code of the digital signal processor is started or not;

and C, the single board sends the test result to the test terminal.

The technical scheme of the invention is different from the prior art in that the scheme of the invention does not adopt a clamp mode, and tests of various peripheral devices of the single board are carried out by directly running the test program on the single board to be tested and outputting information to the test terminal.

Firstly, the technical scheme of the invention is utilized, so that the test equipment and corresponding software are reduced, and the test cost and complexity are greatly reduced; secondly, by using the scheme of the invention, the fault positioning is more accurate and rapid during the test, the test time is reduced, and the accuracy of the test result is improved; thirdly, the EPLD which cannot be tested in the existing test scheme can be tested by utilizing the scheme of the invention.

Drawings

Fig. 1 is a schematic diagram of a conventional MFU single board equipment testing system for testing an MFU single board by using a clamp;

FIG. 2 is a flow chart of a MFU single-board SDRAM test method according to a preferred embodiment of the present invention;

fig. 3 is a schematic flowchart of a method for testing Flash on an MFU board according to a preferred embodiment of the present invention;

fig. 4 is a flow chart of a MFU single board EPLD load test method according to a preferred embodiment of the present invention;

fig. 5 is a schematic flow chart of an MFU single-board EPLD verification test method according to another preferred embodiment of the present invention;

fig. 6 is a schematic diagram of an MFU board integration test flow according to a preferred embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings.

Those skilled in the art will appreciate that a digital communication signal processing board based on an embedded integrated communication controller, such as an MFU board, has a boot memory. The scheme of the invention completes the corresponding MFU single board test except the starting memory by operating the MFU single board test software which is stored in the starting memory and can independently operate on the MFU single board without depending on other peripheral equipment, and outputs the test result from the serial port by adopting a UART protocol through the SCC on the MFU single board. The test that the scheme of the invention can accomplish includes SDRAM test, Flash test, EPLD loading test, EPLD checking test, CHDSP communication test and GDSP communication test, and each test is accomplished by matching with a single item of test software. It should be noted that the test software may be software for performing a single test or integrated test software. The integrated test software integrates a plurality of single test software functions, and the test is more convenient.

According to experience, the MFU single board which cannot be normally started is tested, and the test result shows that the MFU single board mainly has the following reasons: the matching resistor between the MPC860 control signal and the SDRAM fails, but the SDRAM device is normal, so that the SDRAM cannot be read and written correctly; SDRAM device problems therefore do not read and write SDRAM correctly. An EPLD detection function fails; an EPLD load failure; the Flash can not be read and written; the CHDSP cannot work normally; the GDSP cannot normally operate. Based on these results, fault localization assistance information can be output in the test of the present invention.

The invention will now be described with reference to a specific embodiment thereof. The preferred embodiment is illustrated with an MFU board as an example.

The system for testing a digital communication signal processing board based on an embedded integrated communication controller according to a preferred embodiment of the present invention comprises: MFU single-board and test terminal. In a preferred embodiment of the present invention, the digital communication signal processor of the MFU board employs the MPC860, and the test terminal may be a PC. The test terminal communicates with the MFU single board through a serial port through terminal software supporting a UART protocol, such as a super terminal. In the implementation, the embedded system and the JTAG line connected with the PC can be used for connecting the MFU single board and the test terminal for communication.

The test terminal is used for displaying the test result output by the test and relevant fault positioning information and providing an interactive interface for a tester to control and select the test. For example, in a preferred embodiment of the invention, the test terminal adopts the super terminal to communicate with the MFU single board, and the detailed information of the test normality or the test failure is printed on the test terminal in the test process for the analysis of a tester. For another example, in a preferred embodiment of the present invention, the MFU board integrated test software is used for testing, and a tester selects which peripheral to test through the interactive interface of the test terminal.

The MFU single board is used for storing test software and testing external devices, and outputting test results or detailed information of faults by using a UART protocol when the test software is ended or has errors. In a preferred embodiment of the invention, the MFU single board is adopted to integrate the test software for testing, a tester selects to carry out Flash test through the test terminal, then the MFU single board runs a corresponding Flash test program, an error address and read storage data are output in the test process, and a test failure message and a fault positioning prompt message are output after the test is finished.

The following is described in connection with single-item test software of the MFU single board.

The flow of the MFU single-board SDRAM testing method according to a preferred embodiment of the present invention is shown in fig. 2.

Step 100 is entered first to initialize the SDRAM. Among other things, methods for initializing SDRAM are well known to those skilled in the art.

Step 110 is then entered to write data to all memory cells. The written data needs to be read later, and if the memory unit works normally, the written data cannot be in error.

Step 120 is then entered, where the data of all memory cells is traversed and compared with the written data. And if the storage unit works normally, the read data is the data stored in the storage unit.

Then, step 130 is entered to determine whether the read-back data and the write-in data are the same, if yes, step 140 is entered, otherwise, step 150 is entered. In a preferred embodiment of the present invention, if the read-back data and the write-in data are the same, it indicates that the memory cell is not defective, and if they are not the same, it indicates that there is a defect.

In step 140, a test success message is output after the traversal is finished. After the step is finished, the MFU single-board SDRAM test flow is finished. Wherein, the message of successful test is output to the test terminal by the MPC860 communication controller of the MFU board in the UART protocol through the SCC of its CPM.

In step 150, the error address and the read-back data are output, and a test failure message and a positioning prompt message are output after the traversal is finished. After the step is finished, the MFU single-board SDRAM test flow is finished. The output manner of the data and the message in step 150 is the same as that in step 140.

It should be noted that, in a preferred embodiment of the present invention, in order to ensure the reliability of the SDRAM test, multiple traversal tests are performed, and the data written during traversal includes 0x55 and 0xAA, i.e. binary 01010101B and 10101010B. Those skilled in the art will understand that this is equivalent to performing a read/write operation on each memory bit of each memory cell, and that the SDRAM may be considered to be operating normally when both read/write traversal 0x55 and 0xAA are normal.

A Flash test flow of the MFU board according to a preferred embodiment of the present invention is shown in fig. 3.

Step 200 is entered first, and a Flash vendor Identifier (ID) and a device Identifier (ID) are read and output. As will be appreciated by those skilled in the art, different vendors and different device flashes require different underlying drivers, and therefore the vendor ID and device ID need to be obtained before testing can begin.

And then, entering step 210, and installing a bottom layer Flash driver according to the Flash model. Wherein which driver is installed is determined by the vendor ID and the device ID obtained in step 200.

And then, entering step 220, and erasing the information of all the storage units of the Flash. It should be noted that before the test data is written, the information of all the storage units of Flash is erased to ensure the accuracy of the test.

Then, step 230 is entered, and data is written into all Flash memory cells. It should be noted that the data written herein may be changed as needed.

And then, entering step 240, traversing and reading the data of all Flash storage units and comparing the data with the written data. It should be noted that, if the Flash storage unit has no fault, the read data is the data stored in the storage unit.

Then step 250 is entered to determine whether the read-back data is the same as the write data, if so, step 260 is entered, otherwise, step 270 is entered. In a preferred embodiment of the present invention, if the read-back data and the write-in data are the same, the Flash memory unit is considered to be normal, otherwise, the Flash memory unit is considered to be faulty, and fault information needs to be output.

In step 260, a test success message is output after the traversal is completed. After the step is finished, the MFU single board Flash test flow is finished. In a preferred embodiment of the present invention, as in the SDRAM test method, the message of successful test is output to the test terminal by the MPC860 communication controller of the MFU board in UART protocol through the SCC of its CPM.

In step 270, the error address and the read-back data are output, and a test failure message and a positioning prompt message are output after the traversal is finished. After the step is finished, the MFU single board Flash test flow is finished.

It should be added that, because the write operation of Flash is time-consuming, the total test event is relatively long, and in order to show that the test is in progress, a light emitting diode on the MFU board may be flashed, and the specific implementation method is well known to those skilled in the art.

It should be noted that, in a preferred embodiment of the present invention, in order to ensure the reliability of the Flash test, multiple traversal tests are performed on all the memory cells, and the data written during traversal includes 0x55 and 0xAA, i.e., binary 01010101B and 10101010B. Those skilled in the art will understand that this is equivalent to performing read/write operations on each storage bit of each storage unit, and Flash can be considered to be working normally when both write traversal 0x55 and write traversal 0xAA are working normally.

Fig. 4 shows a loading test flow of the MFU single board EPLD according to a preferred embodiment of the present invention.

Step 300 is entered first, and data is written to the EPLD test port. In a preferred embodiment of the present invention, the testing port address of the EPLD is 0xFEF 0002F.

Then, step 310 is entered, the data is read back and judged whether it is correct, if so, step 320 is entered, otherwise, step 330 is entered. It will be understood by those skilled in the art that the read-back data and the written data of the EPLD are in an inverse relationship, for example, when the written data is 0xA5, i.e. binary number 10100101B, if the EPLD is operating normally, the read data should be 0x5A, i.e. binary number 01011010B.

In step 320, a test success message is output. After the step is completed, the loading test process of the MFU single board EPLD is finished. The output mode of the message is as described above, and is not described herein again.

In step 330, a test failure message and a location hint message are output. After the step is completed, the loading test process of the MFU single board EPLD is finished.

It should be noted that, in a preferred embodiment of the present invention, in order to ensure the reliability of the EPLD load test, multiple read/write operations are performed, and the read/write data includes 0xA5, 0xF0, and 0x9C, i.e. binary data 10100101B, 11110000B, and 10010110B. It will be understood by those skilled in the art that the EPLD load may be considered to operate properly when reads and writes 0xA5, 0xF0, and 0x9C all operate properly.

Fig. 5 shows a flow of the MFU single board EPLD verification test according to a preferred embodiment of the present invention.

Step 400 is entered first, and the EPLD is loaded. In a preferred embodiment of the present invention, the EPLD load file is stored in boot memory.

Step 410 is then entered to determine whether loading the EPLD was successful, if so, step 430 is entered, otherwise, step 420 is entered. In this step, if the loading of the EPLD is not successful, it indicates that there is a fault.

In step 420, a load failure message and a location hint message are output. After the step is completed, the checking and testing process of the EPLD of the MFU single board is finished.

In step 430, the EPLD is read and the load is checked for correctness, if so step 450 is entered, otherwise step 460 is entered. It should be noted that although the file has been loaded to the EPLD, it cannot be guaranteed whether the loaded data is correct, and therefore, it is necessary to detect whether the loading is correct. In a preferred embodiment of the invention, the loading is checked for correctness by reading the data of the EPLD and comparing it with the loaded file.

In step 440, the output logic detects the failure message and the location hint message. After the step is completed, the checking and testing process of the EPLD of the MFU single board is finished.

In step 450, a load success message is output. After the step is completed, the checking and testing process of the EPLD of the MFU single board is finished. Wherein, after the loading is successful and the loaded data is read out and checked to be correct, it can be considered that no fault occurs in the EPLD loading.

Since the flow of the MFU single board CHDSP communication test and the GDSP communication test is simple and clear, the following description is directed.

The flow of the communication test of the MFU single board CHDSP according to a preferred embodiment of the present invention is as follows:

firstly, the code of the CHDSP is loaded into a Dual Port Random Access Memory (DPRAM) of the CHDSP through a Host Port Interface (HPI), and then corresponding information is output. The output information includes: the information whether the communication between the MPC860 and the HPI port of the CHDSP is normal or not, the information whether the interrupt input signals PC12 and PC13 of the MPC860 are normal or not is inputted to the CHDSP, the information whether the code loading of the CHDSP is successful or not, and the information whether the code formal operation of the CHDSP is started or not. The CHDSP formal operation code is a non-bootstrap code which runs on the CHDSP, the bootstrap code is used for bootstrapping a program in the ROM to complete initialization of the serial port, and then a user is waited to write a user code from the serial port.

The MFU board GDSP communication test flow according to a preferred embodiment of the present invention is similar to the MFU board CHDSP communication test flow according to a preferred embodiment of the present invention described above:

the GDSP code is loaded into the GDSP DPRAM through the HPI port first, and then the corresponding information is output. The output information includes: the information whether the communication between MPC860 and the HPI port of the GDSP is normal, the information whether the interrupt input signal PC8 of MPC860 is normal or not is input to the GDSP, the information whether the code loading of the GDSP is successful or not, and the information whether the GDSP formally runs the code or not is started or not.

It will be appreciated by those skilled in the art that a plurality of individual test software items may be integrated together and a user interface provided on the test terminal to form the integrated test software.

Fig. 6 shows an MFU board integration test flow according to a preferred embodiment of the present invention.

Step 500 is entered first to output the functional and operational aids of the integrated test software. The output information is also output in the UART protocol.

Then, step 510 is entered for SDRAM testing. The SDRAM test method is as described in the MFU single-board SDRAM test method.

Then, step 520 is entered to determine whether the input information of the tester is valid, if yes, step 530 is entered, otherwise, step 540 is entered. Wherein the information entered by the tester is used to determine what peripheral tests are to be performed.

In step 530, a corresponding test is initiated based on the input information from the tester. After the step is completed, the MFU single-board integration test process is finished. Wherein, the tests which can be carried out in the step comprise: flash test, EPLD loading test, EPLD verification test, CHDSP communication test, and GDSP communication test, the methods of the item tests being as described above.

In step 540, a key deactivation message is output. After the step is completed, the MFU single-board integration test process is finished.

If the test can be performed continuously on different or the same peripheral, the process proceeds to step 500 after both step 530 and step 540 are completed, and the continuous test can be realized by this loop.

It will be appreciated by those skilled in the art that the substitution of a powerquic-based digital communications signal processing board for the MFU board fully enables the present invention to be implemented without affecting the spirit of the invention.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A test system of a digital communication signal processing single board comprises the digital communication signal processing single board, wherein the single board comprises an embedded integrated communication controller, a first memory and an external device, and is characterized in that the test system also comprises:

wherein, the first memory stores testing software;

the embedded integrated communication controller operates the test software in the first memory to load files on the erasable programmable logic device when the single board is started, judges whether the loading is successful or not, and outputs a test result to the test terminal according to the loading result; or,

2. The system for testing a board for processing digital communication signals according to claim 1, wherein the peripheral device further comprises one or a combination of a synchronous dynamic memory and a flash memory.

3. The system according to claim 1, wherein the test terminal further displays the fault detail information and the fault location help information from the digital communication signal processing board.

4. The system for testing a single board for processing digital communication signals according to claim 1, wherein said single board is a micro cellular frame processing unit.

5. A testing method for a digital communication signal processing single board is characterized by comprising the following steps:

and C, the single board sends the test result to the test terminal.

6. The method for testing a digital communication signal processing board according to claim 5, wherein the testing an erasable programmable logic device further comprises:

writing data into a test port of the erasable programmable logic device;

reading back the data of the testing port of the erasable programmable logic device and judging whether the data is correct, if so, outputting a testing success message, otherwise, outputting a testing failure message;

7. the method for testing a digital communication signal processing board according to claim 5, wherein the step B further includes testing a synchronous dynamic memory, including:

b21 initializing the synchronous dynamic memory and writing data to all memory cells of the synchronous dynamic memory;

b22 traversing all the memory cells of the synchronous dynamic memory and comparing with the written data, judging whether the data stored in all the memory cells of the synchronous dynamic memory are the same as the written data, if so, outputting a test success message, otherwise, outputting a memory cell address with a fault and a test failure message.

8. The method for testing a digital communication signal processing board according to claim 5, wherein in the step B, further comprising testing a flash memory, the method comprises:

b31, installing a bottom layer flash driver according to the flash model and writing data into all storage units of the flash;

b32 traversing all the memory cells of the flash memory and comparing with the written data, judging whether the data stored in all the memory cells of the flash memory are the same as the written data, if so, outputting a test success message, otherwise, outputting a memory cell address with a fault and a test failure message.

9. A testing method for a digital communication signal processing single board is characterized by comprising the following steps:

and C, the single board sends the test result to the test terminal.

10. The method for testing a digital communication signal processing board according to claim 9, wherein the step B further includes testing a synchronous dynamic memory, including:

11. The method for testing a digital communication signal processing board according to claim 9, wherein the step B further includes testing a flash memory, including: