CN102508748B - The detection method of veneer, internal memories of digital signal processors - Google Patents
The detection method of veneer, internal memories of digital signal processors Download PDFInfo
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- CN102508748B CN102508748B CN201110285641.2A CN201110285641A CN102508748B CN 102508748 B CN102508748 B CN 102508748B CN 201110285641 A CN201110285641 A CN 201110285641A CN 102508748 B CN102508748 B CN 102508748B
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Abstract
The invention discloses a kind of veneer, the internal-memory detection method of digital signal processor, method includes：The external memory of digital signal processor is mapped as addressable region by central processing unit；Data are write to the external memory of digital signal processor；The data of write-in are read, compare whether the data read are consistent with the data of write-in, if inconsistent, the external memory of judgement digital signal processor is abnormal.The external memory detection method of veneer provided by the present invention, digital signal processor, the external memory of digital signal processor is detected by central processing unit, it ensure that in detection external memory detection process, corresponding digital signal processor does not need the code of operational monitoring itself external memory in itself.
Description
Technical field
The present invention relates to technical field of communication equipment, more particularly, to the inspection of a kind of veneer, internal memories of digital signal processors
Survey method.
Background technology
With the high speed development of mechanics of communication, communications device single board widely uses DSP chip.Numeral
, it is necessary to use the external memory of Large Copacity during signal processor chip work.DSP chip uses external memory
Afterwards, its operating rate faster, also rises while abnormal probability occurs in its used external memory.In order to ensure data signal
The normal operation of processor, existing processing mode is：In veneer initial operating stage, it is necessary to the external memory of digital signal processor
Detected to ensure that digital signal processor being capable of normal work.
In the prior art, the external memory of digital signal processor is usually and detected by digital signal processor, this
Planting detection mode, there are the following problems：A, digital signal processor is needed to be detected in initial start stage, testing result is inconvenient
Report；B, startup post-digital signal processor use external memory, it is impossible to which whole external memory is detected；C, inspection
During survey, digital signal processor, which can not be run, is detected code in corresponding external memory；D, if it is multiple numeral believe
Number processor, each digital signal processor is required for detecting the external memory of itself, and detection process is difficult to control to, inspection
Result is surveyed to be difficult to report.
The content of the invention
It is a primary object of the present invention to provide the external memory detection method of a kind of veneer and digital signal processor, protect
Card is in the external memory detection process to digital signal processor, and digital signal processor can run detected external memory
In code.
The present invention proposes a kind of internal-memory detection method of digital signal processor, including step：
The external memory of digital signal processor is mapped as addressable region by central processing unit；
Data are write to the external memory of digital signal processor；
The data of write-in are read, whether with the data of write-in consistent, if inconsistent if comparing the data that read, resulting number
The external memory of word signal processor is abnormal.
Preferably, the internal-memory detection method of the digital signal processor, believes numeral performing the central processing unit
The internal memory of number processor is mapped as including before addressable region：
Central processing unit and digital signal processor configure the respective serial embedded interconnecting channels server of high speed；
The embedded interconnecting channels server of serial high speed of central processing unit and the serial high speed of digital signal processor are embedding
Enter formula interconnecting channels server and set up connection, form data exchange channel.
Preferably, it is described to be specifically included to the external memory write-in data of digital signal processor：
Central processing unit transmits data to digital signal processor by the data exchange channel；
Digital signal processor writes the data in its external memory.
Preferably, the central processing unit reads the data write in the external memory and specifically included：
Central processing unit is sent to digital signal processor by the data exchange channel and reads instruction；
Digital signal processor reads the data of write-in to the external memory according to instruction is read, and passes through the number
The data read are sent to central processing unit according to interchange channel.
Preferably, the internal-memory detection method of the digital signal processor also includes：
Central processing unit sends operation when the external memory of digital signal processor is abnormal, to digital signal processor and stopped
Only instruct, so that digital signal processor stops the operation of present procedure；
The data and the data of said write read are analyzed, and report analysis result.
The present invention separately proposes a kind of veneer, including central processing unit, digital signal processor and digital signal processor
External memory, the central processing unit is used for：
The external memory of digital signal processor is mapped as addressable region；
Data are write to the external memory of digital signal processor；
The data of write-in are read, whether with the data of write-in consistent, if inconsistent if comparing the data that read, resulting number
The external memory of word signal processor is different.
Preferably, the central processing unit is additionally operable to configure the embedded interconnecting channels server of serial high speed of itself；
The digital signal processor, is additionally operable to configure the embedded interconnecting channels server of serial high speed of itself；
The embedded interconnecting channels server of serial high speed of the central processing unit, for the string with digital signal processor
The embedded interconnecting channels server of row high speed sets up connection, to form data exchange channel.
Preferably, the central processing unit is further used for：
Digital signal processor is transmitted data to by the data exchange channel, makes digital signal processor described
Data are write in the external memory of its own.
Preferably, the central processing unit is further used for：
Sent by the data exchange channel to digital signal processor and read instruction；Make digital signal processor according to
Instruction is read, the data of write-in are read to the external memory, and central processing unit is sent to by the data exchange channel.
Preferably, the central processing unit is additionally operable to：
In the memory abnormal of digital signal processor, operation halt instruction is sent to digital signal processor, so that number
Word signal processor stops the operation of present procedure；
The data of data and said write to reading are analyzed, and report analysis result.
The external memory detection method of veneer provided by the present invention, digital signal processor, passes through central processing unit pair
The external memory of digital signal processor is detected, it is ensured that in detection external memory detection process, corresponding numeral letter
Number processor does not need the code of operational monitoring itself external memory in itself.
Brief description of the drawings
Fig. 1 is the flow chart of the embodiment of external memory detection method one of the digital signal processor of the present invention；
Fig. 2 is another flow chart of the external memory detection method embodiment of the digital signal processor of the present invention；
Fig. 3 is the structural representation of the embodiment of veneer one of the present invention.
The realization, functional characteristics and advantage of the object of the invention will be described further referring to the drawings in conjunction with the embodiments.
Embodiment
It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, it is not intended to limit the present invention.
Referring to Fig. 1, a kind of embodiment of internal-memory detection method one of digital signal processor of the present invention is proposed, it includes：
The external memory of digital signal processor is mapped as addressable region by step S101, central processing unit in advance；
Step S102, the external memory write-in data to digital signal processor；
Whether step S103, the data for reading write-in, the data for comparing reading are consistent with the data write, if inconsistent,
Then judge that the external memory of digital signal processor is abnormal.
In the present embodiment, digital signal processor is mainly used in operation Baseband algorithms code, it is necessary in the outside of Large Copacity
Deposit.The external memory of digital signal processor described in the present embodiment is one or more.It is when external memory is multiple, then right
External memory carries out data write-in, read operation one by one, and data to write-in and the data that read are contrasted.When all
The data of write-in corresponding to external memory are consistent with the data read, then it is assumed that the external memory of digital signal processor is just
Often.
In the present embodiment, the external memory of digital signal processor is detected by central processing unit, in detection process,
In the case of being not detected by external memory exception, digital signal processor can carry out the operation of Baseband algorithms code, while in
Central processor can be detected to the external memory of digital signal processor at any time, do not limited by the time, improve the spirit of detection
Activity.
Further, referring to Fig. 2, in the internal-memory detection method embodiment of above-mentioned digital signal processor in execution is described
The internal memory of digital signal processor is mapped as including before addressable region by central processor：
Step S201, central processing unit and the respective serial embedded interconnecting channels clothes of high speed of digital signal processor configuration
Business device；
Step S202, the central processing unit embedded interconnecting channels server of serial high speed and the string of digital signal processor
The embedded interconnecting channels server of row high speed sets up connection, forms data exchange channel.
In the present embodiment, the data that central processing unit and digital signal processor are exchanged each other are all needed by the number
It is transmitted according to interchange channel.
Further, it is described to Digital Signal Processing in the internal-memory detection method embodiment of above-mentioned digital signal processor
The external memory write-in data of device are specifically included：Central processing unit transmits data to digital letter by the data exchange channel
Number processor；Digital signal processor writes the data in its external memory.
Further, in the internal-memory detection method embodiment of above-mentioned digital signal processor, the central processing unit is read
The data write in the external memory specifically include following processing：Central processing unit is by the data exchange channel to numeral
Signal processor, which is sent, reads instruction；Digital signal processor reads the number of write-in to the external memory according to instruction is read
According to, and the data read are sent to by central processing unit by the data exchange channel.
In the present embodiment, each external memory includes multiple regions, is needed when being detected to each external memory to whole
All regions are detected in external memory, and need data wire and address wire in each external memory of correspondence to be examined
Survey, its Cleaning Principle is consistent with principles described above, will not be repeated here.
Further, in the internal-memory detection method embodiment of above-mentioned digital signal processor, in addition to following handling process：
Central processing unit sends operation halt instruction when the external memory of digital signal processor is abnormal to digital signal processor,
So that digital signal processor stops the operation of present procedure；And the data and the data of said write read are divided
Analysis, reports analysis result.Maintenance personal just can repair according to the analysis result reported to veneer.
The internal-memory detection method of the digital signal processor of the present invention is carried out specifically by taking a specific example as an example below
Description.
If including the outside that 512MB is hung with two digital signal processors, each digital signal processor on veneer
Internal memory.The external memory detection of digital signal processor is specific as follows：
After Board Power up, central processing unit and above-mentioned two digital signal processor are separately operable respective startup journey
Sequence, central processing unit reloads the version program of central processing unit after operation startup program.
The embedded interconnecting channels clothes of respective serial high speed are respectively configured in central processing unit and two digital signal processors
Business device.
The string of the embedded interconnecting channels server of serial high speed of central processing unit respectively with two digital signal processors
The embedded interconnecting channels server of row high speed sets up connection, forms two data exchange channels.
It is the region 0x80000000- that can be accessed by the area maps of first digit signal processor external memory
0x9fffffff；It is the region that can be accessed by the area maps of second digit signal processor external memory
0xa0000000-0xbfffffff；
Central processing unit detects according to default detection ordering to the external memory of two digital signal processors, such as
If default detection ordering is first detection first digit signal processor, then detect second digit signal processor.It is then first
First the external memory of first digit signal processor is detected, it is specific as follows：One is write to 0x80000000 addresses
32bit data, then read the data being written into again, and data to be written and the data of reading are compared, if unanimously,
Then think that the 0x80000000 addresses are normal.Then data wire and address wire to the external memory carries out the write-in and reading of data
Take, and compare the data of write-in and the data read, think that the data wire and address wire of external memory are normal if consistent.Then
Again other addresses in 0x80000000-0x9fffffff are carried out with data write-in and read operation, and compares what is write and read
Whether data are consistent, think that other addresses are normal if all consistent.If 0x80000000-0x9fffffff addresses, address wire
With part or all of exception in data wire, then it is determined as that the external memory is abnormal.Only as 0x80000000-0x9fffffff
Location, address wire and data wire are all normal, then judge that the external memory is normal.
Then the external memory of the second digital signal processor is detected, it is specific as follows：To 0xa80000000 addresses
32bit data are write, the data being written into then are read again, and data to be written and the data of reading are compared
Compared with if unanimously, then it is assumed that the 0xa80000000 addresses are normal.Then line number is entered to the data wire and address wire of the external memory
According to write-in and reading, and compare the data of write-in and the data read, the data wire and ground of external memory thought if consistent
Location line is normal.Then data write-in and read operation are carried out to other addresses in 0xa0000000-0xbfffffff again, and compared
Write whether consistent with the data read, think that other addresses are normal if all consistent.If 0xa0000000-0xbfffffff
It is partly or entirely abnormal in address, address wire and data wire, then it is determined as that the external memory is abnormal.Only work as 0xa0000000-
0xbfffffff addresses, address wire and data wire are all normal, then judge that the external memory is normal.
When the external memory of first, second digital signal processor is all normal, then it is assumed that digital signal processor in veneer
External memory it is normal.Now central processing unit then to first, second digital signal processor transmission program edition data and is opened
Dynamic flag information.First, second digital signal processor then continues to transport according to described program edition data and active flag information
The row down-stream of itself.
When partly or entirely abnormal in the external memory 121 of first, second digital signal processor 110, then it is assumed that veneer
The external memory 121 of digital processing processor 120 is abnormal in 100, then central processing unit is to first, second digital signal processor
Operation halt instruction is sent, first, second digital signal processor then stops the operation of present procedure；And the data to reading and
The data of said write are analyzed, and report analysis result.User can then be carried out according to the analysis result reported to veneer
Maintenance.
In the present embodiment, if there is the central processing unit on multiple digital signal processors, veneer can be to the list on veneer
Disposably detection is finished the external memory of all digital signal processors on plate.
Referring to Fig. 3, a kind of embodiment of veneer 100 of the present invention is proposed, it includes central processing unit 110, at data signal
Manage the external memory 121 of device 120 and digital signal processor.The central processing unit 110 is used for digital signal processor
120 external memory 121 is mapped as addressable region；Data are write to the external memory 121 of digital signal processor 120；
The data of write-in are read, whether with the data of write-in consistent, if inconsistent, at judgement data signal if comparing the data that read
The external memory 121 for managing device 120 is abnormal.
In the present embodiment, there can be one or more digital signal processors 120 in each veneer 100, to data signal
The detection process of external memory 121 of processor 120, can be selected in the outside to one or more digital signal processors 120
121 are deposited to be detected.Digital signal processor 120 is mainly used in operation Baseband algorithms code, it is necessary to the external memory of Large Copacity.
Wherein, the external memory 121 of digital signal processor 120 can be one or more.When external memory 121 is multiple, then
Carry out data write-in, read operation one by one to external memory 121, and data to write-in and the data that read are contrasted.When
The data of write-in corresponding to all external memories 121 and the data read are inconsistent, then judge digital signal processor 120
External memory 121 it is abnormal.
In the present embodiment, central processing unit 110 in the detection process of external memory 121 of digital signal processor 120,
In the case of being not detected by the exception of external memory 121, digital signal processor 120 can carry out the operation of Baseband algorithms code.
Central processing unit 110 can be detected to the external memory 121 of digital signal processor 120 at any time simultaneously, not limited by the time,
Improve the flexibility of detection.
Further, in the above-mentioned embodiment of veneer 100, the central processing unit 110 is additionally operable to configure the serial height of itself
The embedded interconnecting channels server of speed.The digital signal processor 120, the serial high speed for being additionally operable to configure itself is embedded mutually
Join Channel server.The embedded interconnecting channels server of serial high speed of the central processing unit 110, for at data signal
The embedded interconnecting channels server of serial high speed for managing device 120 sets up connection, to form data exchange channel.
In the present embodiment, the data that central processing unit 110 and digital signal processor 120 are exchanged each other all need to pass through
The data exchange channel is transmitted.
Further, in the above-mentioned embodiment of veneer 100, the central processing unit 110 is further used for by the data
Interchange channel transmits data to digital signal processor 120, makes digital signal processor 120 that the data are write into its own
External memory 121 in.
Further, in the above-mentioned embodiment of veneer 100, the central processing unit 110 is further additionally operable to by the number
Sent according to interchange channel to digital signal processor 120 and read instruction；Digital signal processor 120 is set to be instructed according to reading, to
The external memory 121 reads the data of write-in, and is sent to central processing unit 110 by the data exchange channel.
In the present embodiment, each external memory 121 includes multiple regions, is needed when being detected to each external memory 121
All regions in whole external memory 121 are detected, and need the data wire and ground in each external memory 121 of correspondence
Location line is detected that its Cleaning Principle is consistent with principles described above, will not be repeated here.
Further, in the above-mentioned embodiment of veneer 100, central processing unit 110 is additionally operable to：In digital signal processor 120
External memory 121 it is abnormal when, operation halt instruction is sent to digital signal processor 120, so that digital signal processor 120
Stop the operation of present procedure；And the data and the data of said write to reading are analyzed, and report analysis result.Think
Maintenance provides data reference.
Veneer 100 of the present invention is specifically described by taking a specific example as an example below.
If including two digital signal processors 120 on veneer 100, hung with each digital signal processor 120
512MB external memory 121.Specific as follows is detected to the external memory 121 of digital signal processor 120：
On veneer 100 after electricity, central processing unit 110 and above-mentioned two digital signal processor 120 are separately operable each
Startup program, central processing unit 110 reloads the version program of central processing unit 110 after operation startup program.
The embedded interconnection of respective serial high speed is respectively configured in central processing unit 110 and two digital signal processors 120
Channel server.
The embedded interconnecting channels server of serial high speed of central processing unit 110 respectively with two digital signal processors
The 120 embedded interconnecting channels server of serial high speed sets up connection, forms two data exchange channels.
It is addressable region 0x80000000- by the area maps of the external memory of first digit signal processor 120
0x9fffffff；It is addressable region by the area maps of the external memory of second digit signal processor 120
0xa0000000-0xbfffffff；
Central processing unit 110 enters according to default detection ordering to the external memory 121 of two digital signal processors 120
Row detection, if default detection ordering is first detection first digit signal processor 120, then detect second digit signal
Processor 120.Then the external memory 121 of first digit signal processor 120 is detected first, it is specific as follows：To
0x80000000 addresses write 32bit data, and the data being written into, and data to be written and reading are then read again
Data be compared, if unanimously, then it is assumed that the 0x80000000 addresses are normal.Then to the data wire of the external memory 121
The write-in and reading of data are carried out with address wire, and compares the data of write-in and the data read, is thought if consistent in outside
Data wire and the address wire for depositing 121 are normal.Then data write-in is carried out to other addresses in 0x80000000-0x9fffffff again
And read operation, whether and it is consistent with the data read to compare write-in, thinks that other addresses are normal if all consistent.If
It is partly or entirely abnormal in 0x80000000-0x9fffffff addresses, address wire and data wire, then it is determined as the external memory
121 is abnormal.Only when 0x80000000-0x9fffffff addresses, address wire and data wire are all normal, then judge in the outside
Deposit 121 normal.
Then the external memory 121 of the second digital signal processor 120 is detected, it is specific as follows：To
0xa80000000 addresses write 32bit data, and the data being written into, and data to be written and reading are then read again
The data taken are compared, if unanimously, then it is assumed that the 0xa80000000 addresses are normal.Then to the data wire of the external memory
The write-in and reading of data are carried out with address wire, and compares the data of write-in and the data read, is thought if consistent in outside
Data wire and the address wire for depositing 121 are normal.Then data write-in is carried out to other addresses in 0xa0000000-0xbfffffff again
And read operation, whether and it is consistent with the data read to compare write-in, thinks that other addresses are normal if all consistent.If
It is partly or entirely abnormal in 0xa0000000-0xbfffffff addresses, address wire and data wire, then it is determined as the external memory
121 is abnormal.Only when 0xa0000000-0xbfffffff addresses, address wire and data wire are all normal, then judge in the outside
Deposit 121 normal.
When the external memory 121 of first, second digital signal processor 110 is all normal, then it is assumed that numeral letter in veneer 100
The external memory 121 of number processor 120 is normal.Now central processing unit 110 is then to first, second digital signal processor 120
Transmission program edition data and active flag information.First, second digital signal processor 120 is then according to described program version number
According to continuing to run with the down-stream of itself with active flag information.
When partly or entirely abnormal in the external memory 121 of first, second digital signal processor 110, then it is assumed that veneer
The external memory 121 of digital processing processor 120 is abnormal in 100, then central processing unit 110 is at first, second data signal
Manage device 120 and send operation halt instruction, first, second digital signal processor 120 then stops the operation of present procedure；And to reading
The data and the data of said write taken are analyzed, and report analysis result.User can be with according to the analysis result reported, then
Veneer 100 is repaired.
In the present embodiment, if there is the central processing unit on multiple digital signal processors, veneer can be to the list on veneer
Disposably detection is finished the external memory of all digital signal processors on plate.
In above example, the embedded interconnecting channels controller of the serial high speed by digital signal processor, by number
The external memory of word signal processor regards that the internal memory of central processing unit is directly accessed as.
It should be appreciated that these are only the preferred embodiments of the present invention, it is impossible to therefore the scope of the claims of the limitation present invention,
Equivalent structure or equivalent flow conversion that every utilization description of the invention and accompanying drawing content are made, or be directly or indirectly used in
Other related technical fields, are included within the scope of the present invention.
Claims (10)
1. a kind of internal-memory detection method of digital signal processor, it is characterised in that including step：
The external memory of digital signal processor is mapped as addressable region by central processing unit；
Data are write to the external memory of digital signal processor；
The data of reading write-in, compare whether the data read are consistent with the data of write-in, if inconsistent, judgement numeral is believed
The external memory of number processor is abnormal；
Wherein, the external memory of the central processing unit, digital signal processor and digital signal processor is integrated in same
In veneer.
2. the internal-memory detection method of digital signal processor according to claim 1, it is characterised in that in execution is described
The internal memory of digital signal processor is mapped as including before addressable region by central processor：
Central processing unit and digital signal processor configure the respective serial embedded interconnecting channels server of high speed；
The embedded interconnecting channels server of serial high speed of central processing unit and the serial high speed of digital signal processor are embedded
Interconnecting channels server sets up connection, forms data exchange channel.
3. the internal-memory detection method of digital signal processor according to claim 2, it is characterised in that described to numeral letter
The external memory write-in data of number processor are specifically included：
Central processing unit transmits data to digital signal processor by the data exchange channel；
Digital signal processor writes the data in its external memory.
4. the internal-memory detection method of the digital signal processor according to Claims 2 or 3, it is characterised in that the center
Processor reads the data write in the external memory and specifically included：
Central processing unit is sent to digital signal processor by the data exchange channel and reads instruction；
Digital signal processor reads the data of write-in to the external memory according to instruction is read, and is handed over by the data
Change passage and the data read are sent to central processing unit.
5. the internal-memory detection method of digital signal processor according to claim 1, it is characterised in that also include：
Central processing unit sends operation stopping when the external memory of digital signal processor is abnormal, to digital signal processor and referred to
Order, so that digital signal processor stops the operation of present procedure；
The data and the data of said write read are analyzed, and report analysis result.
6. a kind of veneer, includes the external memory of central processing unit, digital signal processor and digital signal processor；It is special
Levy and be, the central processing unit is used for：
The external memory of digital signal processor is mapped as addressable region；
Data are write to the external memory of digital signal processor；
The data of reading write-in, compare whether the data read are consistent with the data of write-in, if inconsistent, judgement numeral is believed
The external memory of number processor is abnormal.
7. veneer according to claim 6, it is characterised in that
The central processing unit is additionally operable to configure the embedded interconnecting channels server of serial high speed of itself；
The digital signal processor, is additionally operable to configure the embedded interconnecting channels server of serial high speed of itself；
The embedded interconnecting channels server of serial high speed of the central processing unit, for the serial height with digital signal processor
The embedded interconnecting channels server of speed sets up connection, to form data exchange channel.
8. veneer according to claim 7, it is characterised in that the central processing unit is further used for：
Digital signal processor is transmitted data to by the data exchange channel, makes digital signal processor by the data
In the external memory for writing its own.
9. the veneer according to claim 7 or 8, it is characterised in that the central processing unit is further used for：
Sent by the data exchange channel to digital signal processor and read instruction；Make digital signal processor according to reading
Instruction, the data of write-in are read to the external memory, and are sent to central processing unit by the data exchange channel.
10. veneer according to claim 6, it is characterised in that the central processing unit is additionally operable to：
When the external memory of digital signal processor is abnormal, operation halt instruction is sent to digital signal processor, so that number
Word signal processor stops the operation of present procedure；
The data of data and said write to reading are analyzed, and report analysis result.
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| CN1409502A (en) * | 2001-09-24 | 2003-04-09 | 深圳市中兴通讯股份有限公司上海第二研究所 | Method for detecting production line of communication product single board with CPU |
| CN1700662A (en) * | 2004-05-21 | 2005-11-23 | 华为技术有限公司 | System and method for testing digital communication signal processing single board |
| CN101727989A (en) * | 2008-10-16 | 2010-06-09 | 付建云 | NAND FLASH memory chip test system |
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| CN1409502A (en) * | 2001-09-24 | 2003-04-09 | 深圳市中兴通讯股份有限公司上海第二研究所 | Method for detecting production line of communication product single board with CPU |
| CN1700662A (en) * | 2004-05-21 | 2005-11-23 | 华为技术有限公司 | System and method for testing digital communication signal processing single board |
| CN101727989A (en) * | 2008-10-16 | 2010-06-09 | 付建云 | NAND FLASH memory chip test system |
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