CN100380439C - Method for adjusting synchronization of digital display device - Google Patents
Method for adjusting synchronization of digital display device Download PDFInfo
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- CN100380439C CN100380439C CNB2005100670165A CN200510067016A CN100380439C CN 100380439 C CN100380439 C CN 100380439C CN B2005100670165 A CNB2005100670165 A CN B2005100670165A CN 200510067016 A CN200510067016 A CN 200510067016A CN 100380439 C CN100380439 C CN 100380439C
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Abstract
The present invention provides two methods for adjusting the output horizontal synchronization of the sequential conversion of a digital displayer, which enables a convergent-divergent controller to decrease the sequential offset of a line type buffer and conform to the sequential requirements of the vertical synchronization/horizontal synchronization of the digital displayer. Horizontal synchronization oscillation and the digestion of a last horizontal synchronization line are the two methods of the present invention.
Description
Technical field
The present invention relates to improve method synchronous in the digital indicator, refer in particular to the horizontal synchronization vibration of digital indicator and the digestion of the last item horizontal synchronization line.
Background technology
Universal day by day along with flat-panel screens, the image-zooming controller is also cheap day by day, and multiple functionally can handle input picture sequential (timing) different in the digital indicator.
Most scaler chip uses line style impact damper structure, rather than use the picture frame impact damper to construct, because the line style impact damper can be saved storer and chip pin interface, so how to dwindle the line style impact damper and guarantee that the convergent-divergent quality just becomes most important problem.But, when the relative timing between input picture and the output image was not accurately handled, less line style impact damper can produce too fast (under-run) or the too risk of slow (over-run) when first in first out (FIFO).
Usually for a set input picture, vertically import and should equal vertical output effective time (V_op_Active time) effective time (V_ip_Active time), the writing speed of line style impact damper is cooperated with reading speed.The horizontal output of but calculating so always count (HS_op_Total_dots) scarcely be integer, always count and make it to become integer in order to adjust horizontal output, but make input be not equal to output effective time effective time.In the prior art, the bigger line style impact damper of the use that has too soon or too slow tolerance, or first in first out can't be handled when some input pattern when increasing first in first out.
Fig. 1 illustrates the line style impact damper too fast (under-run) or the timing waveform of slow (over-run) too, wherein VSi represents " vertical synchronization input ; HDEi represents that " horizontal data starts input , and VSo represents that " vertical synchronization output , HDEo represent that " horizontal data starts output .When too fast, be that HDEo is too fast, when too slow, then be that HDEo is too slow, so cause the image distortion distortion.
And fixing all after dates of output clock period and horizontal synchronization (Hsync), the vertical total output line (V_op_Total_lines) that is calculated is not an integer.The last item score line will form some display noises on the top of next picture.
Summary of the invention
Fundamental purpose of the present invention is to propose two kinds of methods to improve the stationary problem of digital indicator.In a digital indicator, vertical sequential is divided into four sections:
During the vertical sync pulse (VSync PulseTime),
After during the vertical sync pulse (VSync_BackPorch),
The vertical demonstration reaches the valid period (V_Display_Active)
Before during the vertical sync pulse (VSync FrontPorch),
In the vertical demonstration valid period, use a default output clock (preset outputclock, irrelevant with input clock) calculate desirable horizontal synchronization and always count (HSync outputtotal dots, major part is a non-integer), its mark is counted is assigned on some other line then.The cycle of HSync (horizontal synchronization) is changed to some extent, have duration a bit, lack a bit sometimes, but equal the desirable HSync cycle its average period.This method fits like a glove the sequential of first in first out, is called " horizontal synchronization vibration ".
Second method is called " digestion of horizontal synchronization line (remapping) ".When the vertical total output line (Vertical output total line) that is calculated when being not integer, before being assigned to the point (dots of last VSync fraction line) of the last item vertical synchronization score line during the vertical sync pulse on the line of (VSync FrontPorch), or be assigned on the line of other non-perpendicular demonstration valid period (V_Display_Active), so solved the problem of short-term/long line easily.
Description of drawings
Timing waveform synoptic diagram when Fig. 1 reaches too slowly for the line style impact damper too soon.
Fig. 2 illustrates a normal magnified image.
Fig. 3 illustrates the too fast image of line style impact damper.
Fig. 4 illustrates the too slow image of line style impact damper.
Fig. 5 exports the synoptic diagram of horizontal synchronization vibration for the present invention.
Fig. 6 is the digestion synoptic diagram of the last item line of the present invention.
Embodiment
Why change synchronous sequence?
The scaler of numeric display unit must be supported the image of different resolution and the image of many separate sources, for example ADC and DVI input.Image may be XGA, SXGA, UXGA or other form, the vertical synchronization/horizontal sync frequencies of having nothing in common with each other.Image input (as ITU-R656, ITU-R601 ... etc.) have different sequential image inputs, for example NTSC, PAL, HDTV ... etc., must dwindle separately or amplify to meet the resolution of display panel.
Numeric display unit such as LCD panel have been stipulated fixing effective viewing area (resolution) based on its physical material, tolerable vertical synchronization widely (VSync) and horizontal synchronization (HSync) cycle, and can accept a little timing variations.But if the HSync sequence change is too big, for example greater than 10% of the previous cycle, then display device may produce unnecessary image, for example the image lines or the flicker of white point rubbish, shortening/delay ... etc., therefore keep horizontal synchronizing cycle as far as possible and stablize extremely important.
For the convergent-divergent of image,, then can save design cost, this promptly so-called " picture frame locking " if make output refresh rate (VSync frequency) equal to import refresh rate.Propose to implement three examples of scaler below with impact damper:
1. implement scaler with the picture frame impact damper
Some scaler is with the picture frame buffer design, wherein embed the external DRAM of DRAM or attached extension avoiding sequence problem, but the cost of this system or chip is too high.
2. implement scaler with a plurality of line style impact dampers
Some scaler is with a plurality of line style buffer design, it has extra impact damper to keep bigger FIFO outpost area (write index and read distance between the index), so can under several picture frame scopes, follow the trail of the picture frame locking, just needn't in each picture frame, carry out the picture frame locking, the last item score line of each desirable picture frame accumulated place some other picture frame, therefore each output picture frame all has the HSync line (not having short-term/long line) of integer, but some picture frame may be how a line or lacked a line.The design of this non-picture frame locking will make in each picture frame first write index to change with first distance (time cycle) of reading between the index, therefore the more line style impact damper outpost area of needs.This solution is used more SRAM block on chip, make chip size bigger usually.
3. implement scaler with a small amount of line style impact damper
Some scaler design is based on the consideration of chip cost, and possible impact damper outpost area is very limited, has so have impact damper problem or both slow too soon/too or short-term/long line usually.
Slow too soon/too problem of line style impact damper
When the line style impact damper very in short-term, if it can't keep the speed that impact damper writes and reads, just be easy to produce too soon or too slow problem.
Figure one illustrates the line style impact damper and reaches too slow timing waveform too soon, and wherein VSi represents " vertical synchronization input ", and HDEi represents " horizontal data starts input ", and VSo represents " vertical synchronization output ", and HDEo represents " horizontal data starts output ".When too fast, be that HDEo is too fast, when too slow, then HDEo is too slow, so cause the image distortion distortion.
For the input image, if the line style impact damper is kept correct speed, then image output can seem identical with the input image, as shown in Figure 2.
When too fast, the image of convergent-divergent will copy some lines, and the last item incoming line can't be shown, and image output has the appearance shown in the image pattern 3.
When too slow, the image of convergent-divergent will be lost some lines, and duplicate last several incoming lines, and image output has the appearance shown in the image pattern 4.
But export HSync the cycle, when active line (active line), can adjust, impact damper speed is cooperated, thereby save chip cost if allow the HSync cycle except careful calculating.
In ideal conditions, if select in addition convergent-divergent of effective image capturing range, for example import effective image, then Xia Mian formula must be set up:
V_ip_Active?time＝V_op_Active?time；
Perhaps be expressed as follows in the accurate mode of another kind:
V_ip_Active (line#) * HS_ip_Period (time) (HS represents Hsync)
=V_op_Active (line#) * HS_op_Period (time); And
HS_op_Period(time)
＝CLK_op_period(time/dot)×HS_op_Total(dots)；
So HS_op_Total (dots)=(V_ip_Active (line#) * HS_ip_Period (time)/V_op_Active (line#)/CLK_op_period (time/dot);
But the HS_op_Total that is calculated (dots) 99% is not an integer, therefore will accumulate in whole output V_op_Activeperiod the fractional part of each bar output line HS_op_Total (dots) becomes one and counts greatly, may surpass a line style impact damper, cause too soon or too slow problem.
Therefore allow the fractional part of HS_op_Total (dots) be assigned on some other the line and form horizontal synchronization vibration (HSync Vibration).
Horizontal synchronization vibration (HSync Vibration)
The present invention is called " the horizontal synchronization vibration of vertical effective coverage " and (HSyncVibration), implements with follow procedure:
Allow HS_op_Total (dots) _ Base=Integer (HS_op_Total (dots));
And HS_op_Total (dots) _ Fraction
＝HS_op_Total(dots)_HS_op_Total(dots)_Base；
When showing next bar output line each time, calculate:
HS_op_Total(dots)_Vary＝Fraction(HS_op_Total
(dots)_Vary)+HS_op_Total(dots)_Fractiorr，
If (HS_op_Total (dots) _ Vary＜1) is then in next bar output line
HS_op_Total(dots)＝?HS_op_Total(dots)_Base；
If (HS_op_Total (dots) _ Vary＞=1) is then in next bar output line
HS_op_Total(dots)＝HS_op_Total(dots)_Base+ 1.
So can the oneself adjust variation, this is shown among Fig. 5, and wherein " HS_op_Total (dots) _ Base line will increase " 1 " later to HS_op_Total (dots) at three.
For the high speed panel of some binary channel output, above-mentioned formula can be revised as follows a little:
Allow HS_op_Total (dots) _ Base=Integer (HS_op_Total (dots)/2) * 2;
And HS_op_Total (dots) _ Fraction
＝(HS_op_Total(dots)-HS_op_Total(dots)_Base)/2；
When showing next bar output line each time, calculate:
HS_op_Total(dots)_Vary＝Fraction(HS_op_Total
(dots)_Vary)+HS_op_Total(dots)_Fractiorr，
If (HS_op_Total (dots) _ Vary＜1) is then in next bar output line
HS_op_Total(dots)＝HS_op_Total(dots)_Base；
If (HS_op_Total (dots) _ Vary＞=1) is then in next bar output line
HS_op_Total(dots)＝HS_op_Total(dots)_Base+2.
The digestion of the last item horizontal synchronization line
For the panntographic system of picture frame locking,
input?frame?time＝output?frame?time
input?frame?time＝V_ip_Total(line#)×H_ip_Total(dots)×Clock_ip_Period(time/dot)；
output?frame?time＝V_op_Total(line#)×H_op_Total(dots)×Clock_op_Period(time/dot)；
For a set Clock_op_Period (time/dot) and a H_op_Total (dots) (or adjusted), calculate V_op_Total (line#)=(V_ip_Total (line#) * H_ip_Total (dots) * Clock_ip__Period (time/dot))/(H_op_Total (dots) * Clock_op_Period (time/dot)).
But unfortunately among the V_op_Total that is calculated (line#) 99% for non-integer.
The length that some panel can not be accepted the last item score line is lower than 90% of last line length, so present solution is to eliminate the HSync pulse wave of the last item output line and remove the last item score line; Or try to adjust and export clock or output HSync cycle.
The present invention digests the last item score line on other non-effective output line, thus some output HSync line may count more, but still within the tolerance of panel HSync (normally 10% variation range).
Fig. 6 is about short-term/long line problem and postdigestive result.The last item score line is a short-term, and when next VSo comes then, HSo will postpone a bit of time, thereby throw into question.If omit the HSo of the last item score line, then obtain a long line, this may make digitizing tablet can't follow the trail of the output HS cycle, and may produce unwanted image, for example image lines or the flicker of white point rubbish, shortening/delay ... etc.
Therefore the present invention proposes a kind of method, and counting of the last item score line is assigned in the former lines, and these former lines are (VSync FrontPorch) sections before during the vertical sync pulse, as shown in Figure 6.
The integer of additionally count=get [(counting of the last item score line)/(number of digestion line)] of each bar digestion line.The meaning of round numbers is that fractional part is omitted, and integral part is added " 1 ".
For counting of proper placement the last item score line, preferably digest line and want many.If do not have the line style impact damper too fast/too slow problem, can be whole output line, or use non-active line, or the line before only using during the vertical sync pulse.
Spirit of the present invention and scope are decided by following claims, not limited by the foregoing description.
Claims (5)
1. adjust method synchronous in the digital indicator for one kind, in this digital indicator, vertical sequential is divided into four sections:
During the vertical sync pulse,
After during the vertical sync pulse,
The vertical demonstration reaches the valid period
Before during the vertical sync pulse;
Show in the valid period vertical, using a default output clock calculation to go out a horizontal synchronization always counts, this integral part of always counting is always counted as the horizontal synchronization output of general output line style impact damper, this fractional part of always counting is accumulated, up to 1 o'clock, the horizontal synchronization output that allows next bar export the line style impact damper was always counted and is added 1.
2. synchronous method in the adjustment digital indicator as claimed in claim 1, wherein design binary channel output, this integral part of always counting is always counted as the horizontal synchronization output of general output line style impact damper, this fractional part of always counting is accumulated, up to 2 o'clock, the horizontal synchronization output that allows next bar export the line style impact damper was always counted and is added 2.
3. adjust method synchronous in the digital indicator for one kind, in this digital indicator, vertical sequential is divided into four sections:
During the vertical sync pulse,
After during the vertical sync pulse,
The vertical demonstration reaches the valid period
Before during the vertical sync pulse;
Wherein use an output clock of presetting and horizontal synchronization output always to count and calculate a vertical output number of buses, the integral part of this number of buses is treated as general vertical output number of buses, the fractional part of this number of buses always counted with horizontal synchronization output calculates counting of the last item score line, allows counting of this last item score line digest in the output line style impact damper of front then.
4. synchronous method in the adjustment digital indicator as claimed in claim 3, wherein this last item score line count digest during the vertical sync pulse before or section of other non-perpendicular demonstration valid period.
5. synchronous method in the adjustment digital indicator as claimed in claim 3, wherein each digestion line style impact damper additionally counts to getting the integer of [(counting of the last item score line)/(number of digestion line)], the meaning of round numbers is that fractional part is omitted, and integral part is added 1.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2005100670165A CN100380439C (en) | 2005-04-20 | 2005-04-20 | Method for adjusting synchronization of digital display device |
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| CNB2005100670165A CN100380439C (en) | 2005-04-20 | 2005-04-20 | Method for adjusting synchronization of digital display device |
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| CN100380439C true CN100380439C (en) | 2008-04-09 |
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| CN101986218B (en) * | 2010-11-03 | 2011-12-28 | 烟台持久钟表集团有限公司 | Clock delay compensation device and clock delay compensation synchronization method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0968968A (en) * | 1995-08-31 | 1997-03-11 | Hitachi Ltd | Image display device |
| CN1179580A (en) * | 1996-07-02 | 1998-04-22 | 索尼公司 | Picture processing apparatus and processing method |
| CN1180273A (en) * | 1995-07-31 | 1998-04-29 | 华邦电子股份有限公司 | Device capable of uniformly adjusting digital image size |
| CN1186394A (en) * | 1996-12-06 | 1998-07-01 | 松下电器产业株式会社 | Method of contracting image and apparatus using the same method |
| EP0966150A2 (en) * | 1998-06-19 | 1999-12-22 | Nec Corporation | Image processing apparatus and image processing method, and storage media thereof |
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2005
- 2005-04-20 CN CNB2005100670165A patent/CN100380439C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1180273A (en) * | 1995-07-31 | 1998-04-29 | 华邦电子股份有限公司 | Device capable of uniformly adjusting digital image size |
| JPH0968968A (en) * | 1995-08-31 | 1997-03-11 | Hitachi Ltd | Image display device |
| CN1179580A (en) * | 1996-07-02 | 1998-04-22 | 索尼公司 | Picture processing apparatus and processing method |
| CN1186394A (en) * | 1996-12-06 | 1998-07-01 | 松下电器产业株式会社 | Method of contracting image and apparatus using the same method |
| EP0966150A2 (en) * | 1998-06-19 | 1999-12-22 | Nec Corporation | Image processing apparatus and image processing method, and storage media thereof |
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