CN100377377C - Manufacturing method for semiconductor light emitting device - Google Patents
Manufacturing method for semiconductor light emitting device Download PDFInfo
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- CN100377377C CN100377377C CNB2005101187393A CN200510118739A CN100377377C CN 100377377 C CN100377377 C CN 100377377C CN B2005101187393 A CNB2005101187393 A CN B2005101187393A CN 200510118739 A CN200510118739 A CN 200510118739A CN 100377377 C CN100377377 C CN 100377377C
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Abstract
A manufacturing method for a semiconductor light emitting device is provided. The method includes preparing a first wafer in which at least one semiconductor layer including the emitter layer is formed; disposing a second wafer transparent to an emission wavelength of the emitter layer on the surface of the first wafer; providing a bonding failure prevention structure to at least either the first wafer or the second wafer for preventing bonding failures of the first wafer and the second wafer; and applying compressive force to a contact face between the first wafer and the second wafer while at the same time, heating the contact face. The first and second wafers can be bonded across their entire surfaces without causing bonding failure.
Description
Technical field
The present invention relates to for example to be used for to throw light on, the manufacture method of the semiconductor light-emitting elements of light source such as information display device and information carrying means.
Background technology
At present, in light-emitting diode (calling LED:Light Emitting Diode in the following text), the light that raising will produce in inside is fetched into outside efficient, and promptly outside ejaculation efficient is very important.
For improving the outside efficient that penetrates, use usually the transparent substrate of emission wavelength as the LED substrate.When using, because this substrate is with luminous light absorption, so in fact only can be to penetrating light with substrate about the opposite side (above below this face being called) of the layer of giving out light to the opaque substrate of emission wavelength.Relative therewith, when using to the transparent substrate of emission wavelength, not only above, can also penetrate light from other face.In addition, even in the situation of the face (below this face being called below) that engages the LED substrate side, also can be by above-mentioned following the reflection from the light of luminescent layer towards substrate side, can be from ejaculations such as top and sides.LED with this transparent substrates is applicable at present, uses the infrared LED that InGaAsP based semiconductor material is arranged or uses infrared red LED that AlGaAs based semiconductor material is arranged, uses the yellow led that GaAsP based semiconductor material is arranged or use green LED that GaP based semiconductor material is arranged etc.
In addition, in recent years, have in the exploitation of reddish yellow green LED etc. of AlGaInP based semiconductor material in use, the chip join technology that a plurality of substrates are directly engaged mutually begins rapid practicability.By utilizing this chip join technology to engage with the LED substrate, seek the outside raising of penetrating efficient of LED to the transparent substrate of emission wavelength.
As this first prior art, motion has, and directly engages the technology (with reference to No. 3230638 communique of patent) of GaP (gallium phosphorus) transparent substrates on the surface that is formed at AlGaInP (AlGaInP) the based semiconductor floor on GaAs (gallium arsenic) substrate by pressurization and high-temperature process.
In addition, as second prior art, motion has, and LED luminescent layer and hyaline layer is carried out the technology (with reference to No. 3532935 communique of patent) of chips welding via the knitting layer that contains In (indium).
As the 3rd prior art, motion has following technology, via mask second epitaxial loayer of growing up, forms the groove that reaches aforementioned mask on this second epitaxial loayer on first epitaxial loayer of growing up on first substrate.Then, chip join second substrate on above-mentioned second epitaxial loayer is via above-mentioned ditch trench etch aforementioned mask.Thus, above-mentioned second epitaxial loayer and second substrate are separated (opening the 2001-53056 communique with reference to the spy) from above-mentioned first substrate and first epitaxial loayer.
As the 4th prior art, motion has following technology, is formed on the extension chip that forms on the GaAs substrate as the laminate of luminescent layer, and the spacing with 300 μ m on the extension chip is carried out blade cuts in length and breadth, and the groove of width 100 μ m, the degree of depth 20 μ m is set.Behind bonding GaP substrate on the face that is provided with groove of this extension chip, remove the GaAs substrate of above-mentioned extension chip, form electrode, carry out element and separate, form led chip (opening the 2001-57441 communique) with reference to the spy.
But above-mentioned each prior art has following problem.
That is, there are the following problems in above-mentioned first prior art, when making LED in the chip of normally used 2 inches diameter or 3 inches, is difficult to rate of finished products highland, whole of bonding transparent substrates equably.
In the test that the China invites the person carries out, anchor clamps 50 shown in the front elevation of use Fig. 7 and the plane graph of Fig. 8, adhesion is as second chip 123 of GaP transparent substrates on the surface of first chip 122 that forms AlGaInP based semiconductor layer formation on the GaAs substrate, and pressurize, in heating furnace, carry out high-temperature process.Above-mentioned first and second chip 122,123 is the chip of 2 inches diameter.Consequently, after high-temperature process, behind heating furnace taking-up chip, on chip, crack, can not transfer to subsequent processing.In addition, even chip is being divided into 1/4, situation about engaging, because the flatness on the composition surface of semiconductor layer and transparent substrates, and the more appearance of area of formation bad connection.Fig. 9 is the figure of first chip 122 before expression engages, and Figure 10 is the figure of first and second chip 122,123 after expression engages.As shown in figure 10, crack 112 on first and second chip 122,123, in addition, bonding part 110 produces with island at the central authorities and the radial outside of chip, and part does not in addition engage, and it is bad to produce joint.Like this, there is the problem of the volume production that is difficult to be applicable to LED in above-mentioned first prior art.
In addition, in second prior art, as described in first embodiment, after forming the LED layer on the growth substrate, before the chip join transparent substrates, remove above-mentioned growth substrate.The LED layer of removing the state behind this growth substrate is because thin, damaged easily, so there is the problem that causes the rate of finished products reduction.In addition, as described in second embodiment, when carrying out chip join, for suppressing the damaged and be full of cracks of chip, when chip reaches the temperature of softness, the device that need utilize air slide that said chip is pressurizeed.Therefore, there is the complicated problem of causing the complicated of manufacturing installation and control thereof.
In the 3rd prior art, do not put down in writing the particular content of chip join operation.
The led chip of making by the 4th prior art is owing to forms the groove of 100 μ m width with the spacing of 300 μ m, so the problem that the composition surface of this extension chip of existence and GaP substrate diminishes on the extension chip.
Summary of the invention
Therefore, problem of the present invention is, the manufacture method of semiconductor light-emitting elements is provided, and is can be whole of chip even, simple and easy and carry out chip join with high rate of finished products.
For solving described problem, first aspect present invention provides the manufacture method of semiconductor light-emitting elements, and it has: configuration is to the operation of the second transparent chip of the emission wavelength of described luminescent layer on the surface of first chip that is formed with at least one semiconductor layer that contains luminescent layer; The operation of the bad bad structure of anti-joint of the joint prevent this first chip and second chip is set at least one in described first chip and second chip; On the contact-making surface that described first chip and second chip join, act on compression stress, simultaneously, heat the operation of described contact-making surface.
According to described structure, at described second chip of the surface configuration of described first chip.The bad structure of described anti-joint is set at least one in described first chip and second chip.In the presence of the bad structure of this anti-joint,, simultaneously, heat this contact-making surface to described contact-making surface effect compression stress.Therefore, even under the different mutually situation of for example thermal coefficient of expansion of the part of joining on the described contact-making surface of described first chip and second chip, can prevent that also the joint of first and second chip of described contact-making surface is bad.
In addition, second aspect present invention provides the manufacture method of semiconductor light-emitting elements, it has: configuration forms second chip to the transparent hyaline layer of the emission wavelength of described luminescent layer on the surface of first chip that is formed with at least one semiconductor layer that contains luminescent layer, makes the transparent layer surface of this second chip contact the operation of described first chip surface; The operation of the bad bad structure of anti-joint of the joint prevent this first chip and second chip is set at least one in described first chip and second chip; On the contact-making surface that described first chip and second chip join, act on compression stress, simultaneously, heat the operation of described contact-making surface.
According to described structure,, make the configuration of joining of the surface of the transparent layer surface of this second chip and described first chip at described second chip of the surface configuration of described first chip.The bad structure of described anti-joint is set at least one in described first chip and second chip.This engage bad structure in the presence of, to described contact-making surface effect compression stress, simultaneously, heat this contact-making surface.Therefore, even the mutual different situation of for example thermal coefficient of expansion of the part of joining on the described contact-making surface of described first chip and second chip, described first chip and second chip can prevent that also the joint of described contact-making surface is bad.
In the manufacture method of the semiconductor light-emitting elements of an embodiment, the bad structure of described anti-joint is the stress buffer film that is configured at least one a face side opposite with described contact-making surface, described first chip and second chip.
According to described embodiment, under the state that described stress buffer film is configured at least one a face side opposite, described first chip and second chip,, simultaneously, heat this contact-making surface to described contact-making surface effect compression stress with described contact-making surface.Thus, the deviation of the stress distribution in the described contact-making surface (り partially) reduces.Therefore, can prevent the loose contact of first and second chip in the described contact-making surface.
In the manufacture method of the semiconductor light-emitting elements of an embodiment, described stress buffer film is pressed 5～500kg/cm at clamping area
2Scope internal stress mitigation rate be 1.5～3.0%.
According to described embodiment, by pressing 5～20kg/cm at clamping area
2Scope internal stress mitigation rate be 1.5～3.0% described stress buffer film, can reduce the deviation of the stress of described first and second chip join face effectively.More preferably described stress buffer film is pressed 5～500kg/cm at clamping area
2Scope stress mitigation rate be 1.8～2.5%.
In the manufacture method of the semiconductor light-emitting elements of an embodiment, described stress buffer film has the following thickness of the above 2.0mm of 0.2mm.
According to described embodiment,, can reduce the deviation of the stress of described first and second chip join face effectively by having the described stress buffer film of the thickness below the above 2.0mm of 0.2mm.
In the manufacture method of the semiconductor light-emitting elements of an embodiment, the bad structure of described anti-joint is to face described contact-making surface and the groove that is provided with predetermined distance.
According to described embodiment, with in the presence of the groove of predetermined distance setting,, simultaneously, heat this contact-making surface to described contact-making surface effect compression stress facing described contact-making surface.Thus, the deviation of the stress distribution in the described contact-making surface reduces.Therefore, can prevent that the joint of first and second chip of described contact-making surface is bad.In addition, described groove also can be arranged on in first chip and second chip any.
In the manufacture method of the semiconductor light-emitting elements of an embodiment, described groove is provided with the interval of the chip size of corresponding semiconductor light-emitting elements.
According to described embodiment, because described groove is provided with the interval of the chip size of corresponding semiconductor light-emitting elements, thus can be by cutting apart first and second chip along this groove, and easily obtain the chip of semiconductor light-emitting elements.
In the manufacture method of the semiconductor light-emitting elements of an embodiment, described groove forms by cutting.
According to described embodiment,,, simultaneously, first and second chip can be divided into chip so the anti-bad structure that engages can easily be set because described groove forms by etching.
In the manufacture method of the semiconductor light-emitting elements of an embodiment, described groove forms by etching.
According to described embodiment,,, simultaneously, first and second chip can be divided into substrate so the anti-bad structure that engages can easily be set because described groove forms by etching.
In the manufacture method of the semiconductor light-emitting elements of an embodiment, described groove has the following degree of depth of the above 80 μ m of 5 μ m.
According to described embodiment, because described groove has the following degree of depth of the above 80 μ m of 5 μ m, so can reduce the deviation of the stress distribution of described contact-making surface effectively.In addition, described groove is the 100 μ m or the degree of depth more than the 100 μ m at the thickness that is provided with on first or second chip of this groove to the face from trench bottom to an opposite side with contact-making surface preferably.
In the manufacture method of the semiconductor light-emitting elements of an embodiment, the bad structure of described anti-joint is that thickness is following described first chip of the above 300 μ m of 100 μ m and at least one in second chip.
According to described embodiment, by at least one the thickness in described first chip and second chip being made as more than the 100 μ m below the 300 μ m, in the contact-making surface effect compression stress to this first chip and second chip, when simultaneously it being heated, the deviation of the stress distribution of this contact-making surface reduces.Therefore, can prevent that the joint of first and second chip of described contact-making surface is bad.
In the manufacture method of the semiconductor light-emitting elements of an embodiment, the bad structure of described anti-joint by grinding, etching, and the chemical machinery polishing at least one formation.
According to described embodiment, by grinding, etching, and the chemical machinery polishing at least one, can easily obtain the anti-bad structure that engages.
In the manufacture method of the semiconductor light-emitting elements of an embodiment, at least one of described first chip and second chip has the layer that forms by MOCVD (MOCVD) method or MBE (molecular line extension) method.
According to described embodiment, at least one of described first chip and second chip has the layer that forms by mocvd method or MBE method, the time that the growth needs of this layer is long.Therefore, when in a single day described layer is separated from having such substrate now, need grow into the bigger thickness that only will obtain the degree of prescribed strength, therefore by above-mentioned layer, the time of the growth cost of this layer becomes longer, and the time of the manufacturing cost of semiconductor light-emitting elements becomes longer.Relative therewith, according to described embodiment, owing in a single day described layer is not separated from substrate, and can under the state of chip, engage first and second chip, so will not grow to the degree that obtains prescribed strength by described layer, therefore, can shorten the time of the manufacturing cost of semiconductor light-emitting elements.In addition, as long as described layer uses so can prevent the waste of the material of this layer owing to grow into the thickness of luminous needed irreducible minimum.
In the manufacture method of the semiconductor light-emitting elements of an embodiment, described groove has the degree of depth with respect to thickness 1/20～1/3 ratio of the chip that is formed with this groove.
According to described embodiment, can reduce the deviation of the stress distribution of described contact-making surface effectively, can prevent effectively that the joint of described first chip and second chip is bad.In the degree of depth of described groove with respect to the ratio of described chip thickness greater than 1/3 situation, be easy to generate crackle being provided with on the chip of this groove.On the other hand, in the degree of depth of described groove with respect to the ratio of described chip thickness less than 1/20 situation, the reduction effect deficiency of the stress distribution deviation of described contact-making surface, the reducing of bonding area that causes described first chip and second chip.
In the manufacture method of the semiconductor light-emitting elements of an embodiment, described groove has the width with respect to interval 1/20～1/5 ratio that is provided with this groove.
According to described embodiment, can in the contact area of guaranteeing described first chip and second chip, prevent the deviation of the stress distribution of this contact-making surface, engage bad prevention.At the width of described groove with respect to the ratio at described interval greater than 1/5 situation, the contact area of first chip and second chip reduces.On the other hand, at the width of described groove with respect to the ratio at described interval less than 1/20 situation, the reduction effect deficiency of the stress distribution deviation of described contact-making surface, the reducing of bonding area that causes described first chip and second chip.
Description of drawings
Explanation that the present invention describes in detail from below and accompanying drawing can be understood more fully.Accompanying drawing only is used for explanation, to the present invention without limits.Among the figure,
Fig. 1 is the figure of expression as the joint operation of the manufacture method of the semiconductor light-emitting elements of the embodiment of the invention;
Fig. 2 A is illustrated in the figure that forms the sample attitude of a plurality of semiconductor layers that contain luminescent layer on the substrate;
Fig. 2 B is the figure of expression first chip;
Fig. 2 C is the figure of sample attitude that is illustrated in surface configuration second chip of first chip;
Fig. 2 D is that expression has first chip of second chip to remove the figure of the sample attitude of substrate and resilient coating to joint;
Fig. 2 E is the figure of sample attitude that the etching cut-off layer of first chip side is removed in the expression etching;
Fig. 2 F is the figure of the finished product of expression light-emitting diode;
The figure of the sample attitude of first and second chip that Fig. 3 is the joint seen from second chip side of expression;
Fig. 4 is the figure of first chip surface in the manufacture method of semiconductor light-emitting elements of expression second embodiment;
The figure of the sample attitude of first and second chip that Fig. 5 is the joint seen from second chip side of expression;
Fig. 6 is the surface of first chip in the manufacture method of semiconductor light-emitting elements of expression the 3rd embodiment and the figure of side;
Fig. 7 is the front elevation of sample attitude of joint operation of the manufacture method of expression conventional semiconductor light-emitting component;
Fig. 8 is the plane graph of sample attitude of joint operation of the manufacture method of expression conventional semiconductor light-emitting component;
Fig. 9 is the figure of first chip before expression engages in the manufacture method of conventional semiconductor light-emitting component;
Figure 10 is that expression engages first chip afterwards and the figure of second chip in the manufacture method of conventional semiconductor light-emitting component.
Embodiment
Below, describe the present invention in detail with reference to illustrated embodiment.
In an embodiment, be manufactured on the light-emitting diode that the AsGaInP (AlGaInP) that has the quaternary quantum well in the luminescent layer is as semiconductor light-emitting elements.
First embodiment
Fig. 1 is the figure of the joint operation in the above-mentioned manufacturing method for LED of expression.This joint operation is the operation with first chip 22 and second chip, 23 joints, via as the contact-making surface effect compression stress between 29 pairs of above-mentioned first and second chips 22,23 of buffer film of the anti-stress buffer film that engages bad structure, simultaneously, heat above-mentioned contact-making surface.
Above-mentioned first chip 22 is the chips that are formed with a plurality of semiconductor layers that comprise luminescent layer on n type GaAs (gallium arsenic) substrate, and above-mentioned second chip 23 is to the p type GaP substrate 23 from the optical transparency of above-mentioned luminescent layer.
Below, with reference to Fig. 2 A～Fig. 2 F above-mentioned manufacturing method for LED is described.In addition, be illustrated in the part that will be separated into the substrate shape in above-mentioned first chip 22 and second chip 23 among Fig. 2 A～Fig. 2 E.
At first, shown in Fig. 2 A, on GaAs substrate 1, form resilient coating 2, etch stopper 3, current-diffusion layer 4, resilient coating 5, coating layer 6, luminescent layer 7, laying 16, coating layer 17, intermediate layer 18, adhere to contact layer 20 and cap rock 21.Above-mentioned each layer grown up by mocvd method, has following note table 1 and table 2 such composition and bed thickness.
Table 1
| Reference number | Layer name | | Bed thickness | |
| 1 | Substrate | GaAs | 350μm | |
| 2 | Resilient coating | GaAs | 0.5μm | |
| 3 | Etching cut-off layer | Al 0.7Ga 0.3As | 0.2 |
|
| 4 | Current-diffusion layer | Al 0.6Ga 0.4As | |
|
| 5 | Resilient coating | (Al 0.7Ga 0.3) 0.5In 0.5P | 0.05μm | |
| 6 | Coating layer | Al
0.5In
0.5 | 1μm | |
| 7 | The MQW active layer | (Al 0.5Ga 0.5) 0.5In 0.5P | 0.1μm |
Table 2
| 16 | Laying | Al 0.5In 0.5P | 0.15μm |
| 17 | Coating layer | Al 0.5In 0.5P | 0.85 |
| 18 | The intermediate layer | Al 0.18Ga 0.62In 0.20P | 0.12μm |
| 20 | Adhere to contact layer | GaP | 5μm |
| 21 | Cap rock | GaAs | 0.01μm |
The composition of above-mentioned table 1 expression layer of 7 etc. from substrate 1 to luminescent layer.The composition of the layer of above-mentioned table 2 expression etc. from the laying 16 on the above-mentioned luminescent layer 7 to cap rock 21.As shown in table 1, above-mentioned luminescent layer 7 is not shown, but it is made of four quantum well layers of lamination chip layer and barrier layer alternately.
In addition, above-mentioned GaAs substrate 1 constitutes from (100) towards＜011 the planar orientation on the surface that the growth of above-mentioned each layer carries out〉direction closes 15 ° angle.In addition, the planar orientation on above-mentioned GaAs substrate 1 surface also can be other planar orientation.
In addition, each layer on the above-mentioned GaAs substrate 1 also can use the MBE method to form.
Then, shown in Fig. 2 B, remove cap rock 21, simultaneously, removing the part that is equivalent to 2 μ m degree thickness in the contact layer 20 by removing adhering to that this cap rock 21 exposes.And, utilize CMP (cmp) method to grind to form minute surface on the surface of adhering to contact layer 20 of removing above-mentioned part.Thus, obtain first chip 22.
Then, shown in Fig. 2 C, as above-mentioned first chip 22 surfaces adhere to the GaP substrate 23 of contact layer 20 surface configuration as second chip, cooperate with the crystal axis of the first chip GaAs substrate 1.Then, carry out the joint operation of above-mentioned first chip 22 and second chip 23.
Engage in the operation at this, use anchor clamps shown in Figure 1 50 to engage above-mentioned first chip 22 and second chip 23.Above-mentioned anchor clamps 50 are made of quartz, have the leave from office 51 of above-mentioned first chip 22 of supporting, in Fig. 1 of above-mentioned second chip 23, cover the face of upside pressing plate 52, bear the power of prescribed level, the press section 53 of pushing above-mentioned pressing plate 52.Lead along the vertical direction by see the framework 54 with approximate コ word shape from the front in this press section 53.Said frame 54 engages with above-mentioned leave from office 51, suitably transmits power to the above-mentioned pressing plate 52 between this leave from office 51 and above-mentioned press section 53.
(the thermal decomposition boron nitride: the pyrolysis boron nitride) film 24, configuration first chip 22 and second chip 23 on a PBN film 24 for configuration the one PBN in the leave from office 51 of above-mentioned anchor clamps.At this, above-mentioned second chip 23 is also carried out mirror ultrafinish with the surface, dispose the surface of this mirror ultrafinish, make itself and mirror ultrafinish the surface of above-mentioned first chip 22 join.What in addition, make the one-tenth major axis on above-mentioned first chip 22 surfaces and above-mentioned second chip 23 surfaces becomes the major axis unanimity.Constitute the upper side of second chip 23, configuration is as the anti-buffer film 29 that engages bad structure on a side opposite with the contact-making surface of above-mentioned first and second chip 22,23.
Above-mentioned buffer film 29 is by pressing 5～500kg/cm at clamping area
2Scope in to have stress mitigation rate be that 1.5～3.0% material constitutes, have the thickness of 1mm.Above-mentioned buffer film 29 is formed by carbon.In addition, this buffer film 29 also can use for example ceramic fibre and the such SiO of glass pulvinus
2Or Al
2O
3The thing that contains form.
Upper side at above-mentioned buffer film 29 disposes the 2nd PBN film 25, makes the upper side of pressing plate 52 contacts the 2nd PBN film 25 of anchor clamps.Then, the press section 53 of above-mentioned anchor clamps is applied the power of 0.6Nm, on the contact-making surface of second chip 23 and first chip 22, act on compression stress via above-mentioned pressing plate 52 and buffer film 29.Under this state, above-mentioned first and second chip 22,23 is put into heating furnace with anchor clamps 50, with 750 ℃ temperature heating one hour.At this, the state effect compression stress that the contact-making surface of above-mentioned first and second chip 22,23 reduces with stress-deviation by above-mentioned buffer film 29.Thus, on roughly whole of above-mentioned contact-making surface, form good joint interface 40.
Finish in heating, carried out cooling after, first and second chip of engaging 22,23 is taken out from heating furnace.Like this, the conjugant of first and second chip 22,23 that has carried out chip join (directly engaging) does not crack and engages bad etc. shown in the plane graph of Fig. 3.
Then, shown in Fig. 2 D, pass through NH
4OH-H
2O
2The substrate 1 and the resilient coating 2 of first chip side removed in the mixed solution etching.
Then, shown in Fig. 2 E, the etching cut-off layer 3 of first chip side is removed in etching.Then, forming N (negative electrode) electrode 45 by the surface of removing the current-diffusion layer 4 that above-mentioned etching cut-off layer 3 exposes.On the other hand, the back side grinding by surface portion makes the GaP substrate 23 of second chip side form specific thickness, and the surface after this grinding forms P (anode) electrode 46.Then, for coupling part alloying, under about 450 ℃ temperature, carry out 15 minutes heat treatment with chip and electrode 45,46.Then, first and second chip 22,23 that will be formed with electrode 45,46 by cutting is divided into substrate, finishes the light-emitting diode shown in Fig. 2 F.
In the light-emitting diode of Zhi Zaoing, GaP substrate 23 and the connecting state that adheres between the contact layer 20 are good like this.In addition, in manufacture process, even through the substrate 1 after engaging, resilient coating 2, and after the etching of etching cut-off layer 3 removes, or after the cutting that applies bigger power, also can not produce in the bonding part peel off etc. bad.
Like this, the manufacture method according to the semiconductor light-emitting elements of present embodiment can engage first and second chip 22,23 equably by simpler method on whole.Therefore, can be to make the higher light-emitting diode of luminous intensity well than present rate of finished products.
In the above-described embodiments, above-mentioned buffer film 29 is pressed 5～500kg/cm at clamping area
2Scope in, stress mitigation rate is 1.5～3.0%, but presses 5～500kg/cm at clamping area
2Scope in, stress mitigation rate also can be 1.5～5.0%.More preferably press 5～20kg/cm at clamping area
2Scope in, stress mitigation rate is 1.8～2.5%.
In addition, the thickness of above-mentioned buffer film 29 is not limited to 1mm, also can suit to set between below the above 2.0mm of 0.2mm.
In addition, above-mentioned buffer film 29 also can not be configured in the upper side of second chip 23, and is configured in the downside of first chip 22.
Second embodiment
In the manufacture method of the semiconductor light-emitting elements of present embodiment, to engage bad structure be to be formed at the groove on first chip, 22 surfaces except that anti-, and all the other are identical with first embodiment.In the present embodiment, the component part identical with first embodiment used identical reference marks, omits detailed explanation.
In the present embodiment, after forming first chip 22 shown in Fig. 2 B, form the groove 61 that arrives prescribed depth from the surface of adhering to contact layer 20 along direction in length and breadth shown in Figure 4 on the surface of this first chip 22.This groove 61 works as the bad structure of anti-joint, forms by cutting.This groove 61 preferably has the degree of depth with respect to thickness 1/20～1/3 ratio of first chip 22.The degree of depth of more preferably above-mentioned groove 61 is 5～80 μ m.In addition, the longitudinal direction of above-mentioned groove 61 is made as at interval with the longitudinal size of the chip of light-emitting diode roughly the same, simultaneously, is made as with the lateral dimension of light-emitting diode chip for backlight unit the longitudinal separation of above-mentioned groove 61 roughly the same.
Then, be upside with the formation face of above-mentioned groove 61, identical with Fig. 1, first chip 22 that will be formed with above-mentioned groove 61 via a PBN film 24 is configured in the leave from office 51 of anchor clamps.Configuration is as the GaP substrate 23 of second chip on this first chip 22, make this GaP substrate 23 mirror ultrafinish the surface groove that contacts above-mentioned first chip 22 form face.At this, the one-tenth major axis on above-mentioned first chip 22 surfaces and above-mentioned second chip 23 become that major axis is consistent to be disposed.
Then, dispose the 2nd PBN film 25 at the upside of above-mentioned second chip 23, configuration pressing plate 52 is via the contact-making surface effect compression stress of press section 53 to first and second chip 22,23.Under this state, heated one hour by the temperature of heating furnace with 750 ℃, with its cooling, thus, obtain shown in Figure 5 not having crackle and engage bad chip join body.
According to present embodiment, owing to form the groove 61 of direction in length and breadth on the composition surface of above-mentioned first chip 22, so corresponding by the configuration space that makes this groove 61 with chip size, the conjugant of first and second chip 22,23 more easily can be separated into substrate along above-mentioned groove 61.
In addition, the formation method of above-mentioned groove 61 is not limited to cutting, also can form by etching.
The groove that faces the composition surface also can not be arranged on the surface of first chip 22, and is arranged on the surface of second chip 23.
Above-mentioned groove 61 preferably has the width with respect to spacing 1/20～1/5 ratio that is provided with this groove 61.Specifically, above-mentioned groove 61 is preferably formed the width of 10 μ m～50 μ m.
In addition, in the present embodiment, also can and with the bad structure of anti-joint of first embodiment.Promptly, on the contact-making surface of first chip 22 or second chip 23, groove 61 is set, and, at the identical buffer film that disposes first embodiment with the face of the opposite side of contact-making surface of this first chip 22 and second chip 23 with buffer film 29, also can be via the contact-making surface effect compression stress of this buffer film to first chip 22 and second chip 23.By the effect that multiplies each other of this groove 61 and buffer film 29, can reduce the deviation of the stress distribution of contact-making surface effectively, can prevent the crackle of first and second chip 22,23 effectively and engage bad.
The 3rd embodiment
In the manufacture method of the semiconductor light-emitting elements of present embodiment, to engage bad structure be to form first chip 22 of specific thickness except that anti-, and all the other are identical with first embodiment.In the present embodiment, the component part identical with first embodiment used identical reference marks, omits detailed explanation.
In the present embodiment, after forming first chip 22 shown in Fig. 2 B, as shown in Figure 6, the surface portion of GaAs substrate 1 side by this first chip 22 of grinding back surface grinding.By this grinding, the thickness of the GaAs substrate 1 of above-mentioned first chip 22 is ground to 250 μ m degree from 350 μ m.Thus, the integral thickness of first chip 22 becomes 256 μ m degree.First chip 22 that forms this thickness works as the bad structure of anti-joint.
Then, be upside with the surface of adhering to contact layer 20, identical with Fig. 1, first chip 22 that will cut down GaAs substrate 1 thickness via a PBN film 24 is configured in the leave from office 51 of anchor clamps.Configuration is as the GaP substrate 23 of second chip on this first chip 22, make this GaP substrate 23 mirror ultrafinish surface and above-mentioned first chip 22 surface of adhering to contact layer 20 join.At this, the one-tenth major axis on above-mentioned first chip 22 surfaces and above-mentioned second chip 23 become that major axis is consistent to be disposed.
Then, dispose the 2nd PBN film 25 at the upside of above-mentioned second chip 23, configuration pressing plate 52 is via the contact-making surface effect compression stress of press section 53 to first and second chip 22,23.Under this state, heated one hour by the temperature of heating furnace with 750 ℃, with its cooling, thus, obtain there is not crackle or engage bad chip join body.
According to present embodiment, owing to the scope below the 300 μ m more than the 100 μ m that the thickness of above-mentioned first chip 22 is cut down, so can prevent in the deviation that when engaging, produces stress on the contact-making surface between above-mentioned first and second chip 22,23.Therefore, can obtain there is not crackle or engage bad chip join body.
In addition, the thickness of above-mentioned first chip 22 also can be cut down by the grinding of adopting grinding back surface other method in addition, in addition, also can cut down by etching and chemical machinery polishing.
Not with above-mentioned first chip 22, and the thickness of second chip 23 is formed the thickness of stipulating, second chip 23 that also can form this thickness is as the bad structure of anti-joint.
In the above-described embodiments, the luminescent layer that has AlGaInP quaternary class as the light-emitting diode of semiconductor light-emitting elements, but the structure of luminescent layer is not limited to quantum well structure, in addition, also can be widely used in the light-emitting diode of other composition.That is, the invention is not restricted to redness (AlGaAs etc.), blue (GaN, InGaN, SiC etc.), yellow (AlGaInP etc.), green (AlGaInP etc.) etc. and form and illuminant colour, all applicable to light-emitting diode.
In addition, use to from the GaP substrate of the optical transparency of the luminescent layer 7 of first chip as second chip, but also can use the substrate that constitutes by other material.In addition, second chip also can be to forming the chip to the hyaline layer of above-mentioned optical transparency on from the opaque substrate of the light of luminescent layer 7, at this moment, as long as at the above-mentioned hyaline layer of the surface engagement of first chip.
The present invention also goes for the semiconductor laser except that light-emitting diode etc.
In addition, also the bad structure of the anti-joint of first～the 3rd embodiment can be repeated to use more than two, thus, can be more effectively not have crackle and to engage bad state engaging first chip 22 and second chip 23.
The present invention more than has been described, but these also can carry out various changes.These changes should not regarded as from the spirit and scope of the present invention and break away from, and whole changes that the practitioner understands certainly are contained in the scope of claim.
Claims (14)
1. the manufacture method of a semiconductor light-emitting elements is characterized in that, has: preparation is formed with the operation of first chip of at least one semiconductor layer that contains luminescent layer; In the operation of described first chip surface configuration to the second transparent chip of the emission wavelength of described luminescent layer; The operation of the bad bad structure of anti-joint of the joint prevent this first chip and second chip is set at least one in described first chip and second chip; On the contact-making surface that described first chip and second chip join, act on compression stress, simultaneously, heat the operation of described contact-making surface,
The bad structure of described anti-joint is the stress buffer film that is configured at least one a face side opposite with described contact-making surface, described first chip and second chip.
2. the manufacture method of semiconductor light-emitting elements as claimed in claim 1 is characterized in that, at least one of described first chip and second chip has the layer that forms by mocvd method or MBE method.
3. the manufacture method of a semiconductor light-emitting elements is characterized in that, has: preparation is formed with the operation of first chip of at least one semiconductor layer that contains luminescent layer; Be formed with second chip in the surface configuration of described first chip, make the transparent layer surface of this second chip and the operation that described first chip surface joins the transparent hyaline layer of the emission wavelength of described luminescent layer; The operation of the bad bad structure of anti-joint of the joint prevent this first chip and second chip is set at least one in described first chip and second chip; On the contact-making surface that described first chip and second chip join, act on compression stress, simultaneously, heat the operation of described contact-making surface,
The bad structure of described anti-joint is the stress buffer film that is configured at least one a face side opposite with described contact-making surface, described first chip and second chip.
4. as the manufacture method of claim 1 or 3 described semiconductor light-emitting elements, it is characterized in that described stress buffer film is pressed 5～500kg/cm at clamping area
2Scope internal stress mitigation rate be 1.5～3.0%.
5. as the manufacture method of claim 1 or 3 described semiconductor light-emitting elements, it is characterized in that described stress buffer film has the following thickness of the above 2.0mm of 0.2mm.
6. as the manufacture method of claim 1 or 3 described semiconductor light-emitting elements, it is characterized in that at least one in described first chip and second chip has the groove that faces described contact-making surface and be provided with predetermined distance.
7. the manufacture method of semiconductor light-emitting elements as claimed in claim 6 is characterized in that, described groove is provided with the interval of the chip size of corresponding semiconductor light-emitting elements.
8. the manufacture method of semiconductor light-emitting elements as claimed in claim 6 is characterized in that, described groove forms by cutting.
9. the manufacture method of semiconductor light-emitting elements as claimed in claim 6 is characterized in that, described groove forms by etching.
10. the manufacture method of semiconductor light-emitting elements as claimed in claim 6 is characterized in that, described groove has the following degree of depth of the above 80 μ m of 5 μ m.
11. the manufacture method as claim 1 or 3 described semiconductor light-emitting elements is characterized in that, at least one thickness in described first chip and second chip is 100 μ m～300 μ m.
12. the manufacture method of semiconductor light-emitting elements as claimed in claim 11 is characterized in that, at least one in described first chip and second chip by grinding, etching, and the chemical machinery polishing at least one form described thickness.
13. the manufacture method of semiconductor light-emitting elements as claimed in claim 6 is characterized in that, described groove has the degree of depth with respect to thickness 1/20～1/3 ratio of the chip that is formed with this groove.
14. the manufacture method of semiconductor light-emitting elements as claimed in claim 6 is characterized in that, described groove has the width with respect to interval 1/20～1/5 ratio that is provided with this groove.
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| JP317054/04 | 2004-10-29 | ||
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| CN101267013B (en) * | 2008-04-30 | 2011-09-28 | 晶能光电（江西）有限公司 | Press welding structure for semiconductor extension slice |
| TWI457984B (en) * | 2008-08-06 | 2014-10-21 | Soitec Silicon On Insulator | Relaxation of strained layers |
| CN104051669B (en) * | 2014-05-28 | 2016-02-03 | 京东方科技集团股份有限公司 | Base plate for packaging, method for packing, display floater |
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|---|---|---|---|---|
| US5376580A (en) * | 1993-03-19 | 1994-12-27 | Hewlett-Packard Company | Wafer bonding of light emitting diode layers |
| US5403916A (en) * | 1993-02-10 | 1995-04-04 | Sharp Kabushiki Kaisha | Method for producing a light emitting diode having transparent substrate |
| JPH10135500A (en) * | 1996-03-18 | 1998-05-22 | Sony Corp | Manufacture of thin film semiconductor, solar cell and light emission element |
| JP2003294947A (en) * | 2002-04-08 | 2003-10-15 | Ricoh Co Ltd | Polarized light separating element and method for manufacturing the same |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5403916A (en) * | 1993-02-10 | 1995-04-04 | Sharp Kabushiki Kaisha | Method for producing a light emitting diode having transparent substrate |
| US5376580A (en) * | 1993-03-19 | 1994-12-27 | Hewlett-Packard Company | Wafer bonding of light emitting diode layers |
| JPH10135500A (en) * | 1996-03-18 | 1998-05-22 | Sony Corp | Manufacture of thin film semiconductor, solar cell and light emission element |
| JP2003294947A (en) * | 2002-04-08 | 2003-10-15 | Ricoh Co Ltd | Polarized light separating element and method for manufacturing the same |
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