CN100369236C - Method for manufacturing high accuracy analog circuit chip - Google Patents
Method for manufacturing high accuracy analog circuit chip Download PDFInfo
- Publication number
- CN100369236C CN100369236C CNB2003101226454A CN200310122645A CN100369236C CN 100369236 C CN100369236 C CN 100369236C CN B2003101226454 A CNB2003101226454 A CN B2003101226454A CN 200310122645 A CN200310122645 A CN 200310122645A CN 100369236 C CN100369236 C CN 100369236C
- Authority
- CN
- China
- Prior art keywords
- metal
- chip
- photoetching
- analog circuit
- test
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 31
- 239000002184 metal Substances 0.000 claims abstract description 31
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 22
- 238000012360 testing method Methods 0.000 claims abstract description 21
- 238000001259 photo etching Methods 0.000 claims abstract description 17
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 14
- 239000010703 silicon Substances 0.000 claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 11
- 229920005591 polysilicon Polymers 0.000 claims abstract description 11
- 238000012545 processing Methods 0.000 claims abstract description 5
- 238000002347 injection Methods 0.000 claims description 9
- 239000007924 injection Substances 0.000 claims description 9
- 230000009514 concussion Effects 0.000 claims description 8
- 238000004364 calculation method Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 238000002161 passivation Methods 0.000 claims description 4
- 238000012937 correction Methods 0.000 claims description 3
- 229910045601 alloy Inorganic materials 0.000 claims 2
- 239000000956 alloy Substances 0.000 claims 2
- 238000000206 photolithography Methods 0.000 abstract 2
- GNFTZDOKVXKIBK-UHFFFAOYSA-N 3-(2-methoxyethoxy)benzohydrazide Chemical compound COCCOC1=CC=CC(C(=O)NN)=C1 GNFTZDOKVXKIBK-UHFFFAOYSA-N 0.000 abstract 1
- FGUUSXIOTUKUDN-IBGZPJMESA-N C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 Chemical compound C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 FGUUSXIOTUKUDN-IBGZPJMESA-N 0.000 abstract 1
- 230000005611 electricity Effects 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 3
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 3
- 238000002715 modification method Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910000967 As alloy Inorganic materials 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000007664 blowing Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Images
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Micromachines (AREA)
Abstract
The present invention discloses a method for manufacturing a high accuracy analog circuit chip. The present invention is characterized in that the method comprises the following steps: step a, all the procedures including the procedure that polysilicon is photoetched are finished; step b, metal is deposited; step c, a piece of silicon chip is taken out, the metal is photoetched by a metal photoetching plate which is not corrected, residual working procedures are finished, a test chip is made, and the processing for the residual silicon chips is stopped temporarily; step d, electricity parameters of the test chip are tested; step e, an error between a real test result and an original proposal is calculated, and a proposal which is corrected is obtained; step f, according to the corrected proposal, a metal photolithography mask plate is made; step g, the metal of other silicon chips in the same batch is photoetched by the metal photolithography mask plate, and the residual working procedures are finished. The present invention has the advantages that the yield of high accuracy analog circuit chips is greatly increased, and the production cost is reduced.
Description
Technical field
The invention belongs to the chip manufacturing field, relate in particular to the manufacture method of semiconducter simulation circuit chip.
Background technology
As everyone knows, the high-quality electronic product needs high-precision analog circuit chip, for example voltage detecting circuit, electric power management circuit etc., yet in the semiconductor chip manufacture process, exist process deviation, cause the actual electrical mathematic(al) parameter difference of the chip of different batches, the index that departs from product makes the rate of finished products of high-precision analog circuit chip very low.For example promptly use highly stable semiconductor process line production, chip analog reference voltage error also can only reach 2%～3% less than 1% rate of finished products.For improving the rate of finished products of high-precision analog circuit chip, more common method has two kinds, and first kind is the laser cutting revised law, and flow chart as shown in Figure 1.This method is after the semi-conductor silicon chip manufacturing procedure is all finished, each sheet chip on the test silicon wafer chip yield is had material electrical parameter, real-time then test data according to each sheet chip, calculate amendment scheme by the program of finishing in advance, remove unwanted metal or polysilicon line with high-octane laser beam cutting then; Second method is a high programming voltage fuse revised law, and flow chart as shown in Figure 2.This method and laser revised law are similar, also be after silicon wafer process machines, test the electrical parameter of each sheet chip, program by prior editorial afterword calculates amendment scheme then, just in the end, add high voltage for revising on the pin of preparing, make unwanted metal lead wire be blown by big electric current special in advance, and this method can only be blown metal lead wire, can not blow the polysilicon lead-in wire.Although these two kinds of methods can effectively improve rate of finished products, all be subjected to the restriction of a lot of conditions.First method needs expensive laser corrective; these are for medium-sized and small enterprises; cost is too high; second method needs extra a plurality of test pins that increase; and what and precision that need to revise of pin become 2 exponential relationship, and this makes chip be restricted when application undoubtedly, simultaneously; the technology of blowing metal lead wire with high voltage is difficult to control, usually can influence the working life of chip.
Summary of the invention
The technical issues that need to address of the present invention are to provide a kind of high-precision analog circuit chip manufacture method, and are too high or limit defectives such as too much to overcome the prior art cost.
Technical scheme of the present invention comprises the steps:
Finish operations such as buried regions, grown epitaxial layer, an injection, photoetching well region, well region injection, photoetching active area, growth gate oxide, active area injection, deposit polysilicon, photoetching polysilicon;
Depositing metal;
Take out a slice from same batch silicon chip, with the metal lithographic version photoetching metal of not doing correction that designs in advance, and finish residue manufacturing procedures such as alloy, passivation, make test chip, all the other silicon chips suspend processing;
Test is by the electrical parameter that is removed the test chip that silicon chip makes of finishing all process steps;
Calculate the error of actual test result and original scheme, the metal connected mode of the related circuit that must revise according to Error Calculation promptly obtains amendment scheme;
Make the metal lithographic mask according to amendment scheme;
With the described metal lithographic mask of previous step other silicon chips of same batch are carried out the photoetching metal, and finish residue manufacturing procedures such as alloy, passivation, make chip, i.e. final products.
The invention has the beneficial effects as follows: compare with original scheme, because in advance the silicon chip that a slice has been finished all process steps is tested, and formulate amendment scheme on this basis, with strong points, can significantly improve the rate of finished products of high-precision analog circuit chip effectively, thereby reduced production cost, abolished many restrictions of original technology.
Description of drawings
Fig. 1 is for adopting the flow chart of laser correction.
Fig. 2 is for adopting the flow chart that burns the aluminium modification method.
Fig. 3 is a flow chart of the present invention.
Fig. 4 is the modification method example of output high-accuracy voltage chip
Fig. 5 is the modification method example of high accuracy oscillator chip
Embodiment
Below in conjunction with accompanying drawing and two specific embodiments the present invention is elaborated.
Making flow chart of the present invention such as Fig. 3.
Embodiment one:
The product of output high-precision analog reference voltage, output voltage values is 1.00V, requires error range less than ± 2%, promptly between the 1.02V, this voltage temperature drift simultaneously is less than ± 100ppm/ ℃ at 0.98V for output voltage.1.00V voltage is obtained through behind the electric resistance partial pressure by the reference voltage that an energy gap circuit produces, the energy gap source reference voltage that Theoretical Calculation goes out is 1.15V, and the resistance ratio of energy gap source circuit is 1: 7.5, and the electric resistance partial pressure ratio is 1: 6.5, as shown in Figure 4.By the inventive method, at first will all process and (comprise and finish buried regions with a collection of silicon chip, grown epitaxial layer, the field is injected, the photoetching well region, well region injects, the photoetching active area, the growth gate oxide, active area injects, the deposit polysilicon, operations such as photoetching polysilicon) after finishing depositing metal, suspend processing, get wherein a silicon chip and finish all processes operations of residue, after being made into test chip, should test the electrical parameter that it plays a decisive role to rate of finished products, as the chip that requires accurate output reference voltage needs test reference magnitude of voltage and reference voltage temperature drift coefficient, the concussion frequency of high precision oscillator chip etc.Actual test result is: the reference voltage of energy gap source circuit is 1.206V, and actual output voltage average value is 1.055V, and the temperature drift of reference voltage reached-200ppm/ ℃, has all surpassed to require index; Afterwards according to above test result, through calculating, changed the resistance ratio of energy gap source circuit into 1: 8.5 by 1: 7.5, electric resistance partial pressure is than changing 1.8: 6.5 into by 1: 6.5, as shown in Figure 4; Make the metal lithographic version according to this modification then; Finish the residue manufacturing procedure of all the other silicon chips again with corrected metal lithographic version.
Adopt chip output voltage error behind the present invention less than ± 2%, temperature drift has reached 55% less than ± 100ppm/ ℃ rate of finished products, and the average rate of finished products of the product that obtains according to original method is less than 5%, and therefore the cost of every chip has reduced by 10 times.
Embodiment two:
High accuracy oscillator product, concussion frequency values are that 500KHz, duty ratio are 0.5, require the concussion frequency error range less than ± 5%, promptly shake the frequency values requirement at 475KHz between the 525KHz.The connected mode that Theoretical Calculation goes out as shown in Figure 5, K wherein
1Disconnect.To the current source I=2uA of electric capacity charging, discharge, capacitor C=C
1=2pF.The bound difference Δ V=1V of charging.Period T=(Δ V/IC)
Charging+ (Δ V/IC)
Discharge=2us, concussion frequency f=1/T=500KHz.By the inventive method, at first will all process (comprising operations such as finishing buried regions, grown epitaxial layer, an injection, photoetching well region, well region injection, photoetching active area, growth gate oxide, active area injection, deposit polysilicon, photoetching polysilicon) with a collection of silicon chip and after finishing depositing metal, suspend processing, get wherein a silicon chip and finish all processes operations of residue, actual test result is: the concussion frequency is 625KHz, has surpassed index.Through calculating, be I=2.5uA because process deviation causes the current source values of the silicon chip reality of this batch.Connect as long as revise metal, with K
1In the connection, make capacitance C=C
1+ C
2=2.5pF, as shown in Figure 5.The concussion frequency just can be revised and get back to 500KHz.Make the metal lithographic version according to this modification then; Finish the residue manufacturing procedure of all the other silicon chips again with corrected metal lithographic version.
The concussion frequency error that adopts the chip behind the present invention has reached more than 90% less than ± 5% rate of finished products, and the average rate of finished products of the product that obtains according to original method is less than 20%, and therefore the cost of every chip has reduced by 4 times.
Claims (2)
1. high-precision analog circuit chip manufacture method is characterized in that may further comprise the steps:
A. finish buried regions, grown epitaxial layer, an injection, photoetching well region, well region injection, photoetching active area, growth gate oxide, active area injection, deposit polysilicon, photoetching polysilicon operation;
B. depositing metal;
C. take out a slice from same batch silicon chip, with the metal lithographic version photoetching metal of not doing correction that designs in advance, and finish remaining alloy, passivation manufacturing procedure, make test chip, all the other silicon chips suspend processing;
D. test by the electrical parameter that is removed the test chip that silicon chip makes of finishing all process steps;
E. calculate the error of actual test result and original scheme, the metal connected mode of the related circuit that must revise according to Error Calculation promptly obtains amendment scheme;
F. make the metal lithographic mask according to amendment scheme;
G. with the described metal lithographic mask of previous step other silicon chips of same batch are carried out photoetching metal and remaining alloy, passivation manufacturing procedure, make chip, i.e. final products.
2. high-precision analog circuit chip manufacture method as claimed in claim 1, it is characterized in that the electrical parameter described in the d item step for rate of finished products there being the electrical parameter of decision influence, comprise temperature drift coefficient, the concussion frequency of reference voltage level, reference voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101226454A CN100369236C (en) | 2003-12-22 | 2003-12-22 | Method for manufacturing high accuracy analog circuit chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101226454A CN100369236C (en) | 2003-12-22 | 2003-12-22 | Method for manufacturing high accuracy analog circuit chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1632943A CN1632943A (en) | 2005-06-29 |
| CN100369236C true CN100369236C (en) | 2008-02-13 |
Family
ID=34844556
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2003101226454A Expired - Lifetime CN100369236C (en) | 2003-12-22 | 2003-12-22 | Method for manufacturing high accuracy analog circuit chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100369236C (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102540749B (en) * | 2010-12-29 | 2013-11-06 | 中芯国际集成电路制造(上海)有限公司 | Photoetching method |
| CN105513989A (en) * | 2015-11-30 | 2016-04-20 | 无锡中感微电子股份有限公司 | Chip manufacturing method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1991018417A1 (en) * | 1990-05-23 | 1991-11-28 | North Carolina State University | Integrated circuit power device with automatic removal of defective devices |
| DE19738717C1 (en) * | 1997-09-04 | 1999-04-22 | Siemens Ag | CAD integrated circuit manufacturing method |
| CN1046822C (en) * | 1996-09-25 | 1999-11-24 | 中国科学院微电子中心 | Method for manufacturing MOS transistor IC with 10,000 gates |
| US6346427B1 (en) * | 1999-08-18 | 2002-02-12 | Utmc Microelectronic Systems Inc. | Parameter adjustment in a MOS integrated circuit |
| US6407602B1 (en) * | 2000-07-21 | 2002-06-18 | Hewlett-Packard Company | Post-silicon methods for adjusting the rise/fall times of clock edges |
-
2003
- 2003-12-22 CN CNB2003101226454A patent/CN100369236C/en not_active Expired - Lifetime
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1991018417A1 (en) * | 1990-05-23 | 1991-11-28 | North Carolina State University | Integrated circuit power device with automatic removal of defective devices |
| CN1046822C (en) * | 1996-09-25 | 1999-11-24 | 中国科学院微电子中心 | Method for manufacturing MOS transistor IC with 10,000 gates |
| DE19738717C1 (en) * | 1997-09-04 | 1999-04-22 | Siemens Ag | CAD integrated circuit manufacturing method |
| US6346427B1 (en) * | 1999-08-18 | 2002-02-12 | Utmc Microelectronic Systems Inc. | Parameter adjustment in a MOS integrated circuit |
| US6407602B1 (en) * | 2000-07-21 | 2002-06-18 | Hewlett-Packard Company | Post-silicon methods for adjusting the rise/fall times of clock edges |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1632943A (en) | 2005-06-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108628107A (en) | Overlay error measurement method and overlay mark | |
| CN104569832A (en) | Correcting method of residual capacity of BMS battery | |
| CN100369236C (en) | Method for manufacturing high accuracy analog circuit chip | |
| TW200521410A (en) | Fault detection and control methodologies for ion implantation processes, and system for performing same | |
| CN102194655B (en) | Method for optimally adjusting console parameters in semiconductor technology | |
| JP5683149B2 (en) | Optical element manufacturing method and optical element molding die manufacturing method | |
| CN101937835B (en) | Method for modifying parameters for fuse-class wafer | |
| CN103887154A (en) | Method for reinforcing ionization radiation resistance of bipolar device based on passivation layer ion injection mode | |
| CN116959979B (en) | Production process of high temperature resistant GPP chip | |
| CN101713920B (en) | Semiconductor device | |
| US8244500B2 (en) | Method of adjusting wafer processing sequence | |
| CN209233811U (en) | One kind trimming circuit | |
| CN107457544A (en) | A kind of processing technology encapsulated with mould molding chamber | |
| CN105321799B (en) | Asymmetry compensation method for photoetching overlay manufacture craft | |
| CN113361222B (en) | Virtual simulation method and device for integrated circuit manufacturing process | |
| CN110434376A (en) | Center processing method | |
| CN100431096C (en) | Method for processing semiconductor chip | |
| CN101739408A (en) | Semiconductor test data-based data processing method | |
| CN102930067B (en) | A kind of method for designing of high-accuracy adjustable chip resistor | |
| CN104462728B (en) | The analogy method and analogue means of semiconductor devices | |
| CN114236974A (en) | Method for compensating deviation of wafer marking structure | |
| CN110409000A (en) | A kind of damage profile of He ion beam processing monocrystalline silicon determines method | |
| CN110867374B (en) | Integrated etching method for metal hard mask and control system thereof | |
| JP3512577B2 (en) | Electric discharge machining apparatus and electric discharge machining method | |
| CN112819206A (en) | Blade mixing sorting process treatment method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI LEADCHIP MICROELECTRONICS CORP., LTD. Effective date: 20110830 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20110830 Address after: 200233 room 1, building 810, No. 401, Shanghai, Yishan Road Patentee after: SHANGHAI LEADCHIP MICROELECTRONICS Corp.,Ltd. Address before: 200233 No. 810, Shanghai, Yishan Road Patentee before: SHANGHAI BELLING Corp.,Ltd. |
|
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20080213 |