CN100431096C - Method for processing semiconductor chip - Google Patents
Method for processing semiconductor chip Download PDFInfo
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- CN100431096C CN100431096C CNB2005100821324A CN200510082132A CN100431096C CN 100431096 C CN100431096 C CN 100431096C CN B2005100821324 A CNB2005100821324 A CN B2005100821324A CN 200510082132 A CN200510082132 A CN 200510082132A CN 100431096 C CN100431096 C CN 100431096C
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Abstract
The invention relates to a processing method of the semiconductor wafer. First carry out the first process to the semiconductor wafer. Then record the measure data on the semiconductor wafer reflecting the windage status in the semiconductor wafer. According to the measure data, carry out the second process to the same semiconductor wafer to offset the windage in the first process. So it can correct the process windage in the same semiconductor wafer immediately and effectively.
Description
Technical field
The present invention relates to a kind of processing method of semiconductor wafer, particularly relate to a kind of processing method of in semiconductor wafer, carrying out the process deviation correction.
Background technology
In today semi-conductive manufacturing technology, encapsulate the semiconductor element of output to the end from the semiconductor wafer material, relate to most processing steps, and that each step influences all the size of semiconductor element and specification is very huge, so the quality of output can be effectively controlled in the adjustment of technological parameter in each technology.
(advanced process control APC) in the manufacture method of integrated circuit, is a kind of methodology of keeping and controlling critical process in advanced technologies control.In semiconductor technology, use metering outfit single or that integrate to be beneficial to reach wafer to wafer (wafer-to-wafer) or batch advanced technologies control to batch (run-to-run).Wherein, wafer to wafer is after handling a wafer, carries out an algorithm by resulting data on this wafer, and the result of estimation is fed back among the technology of next wafer.Batch to batch being that online in real time is integrated machinery equipment, technological operation, state variable and chip and measured qualitative variables, see through the prediction estimation of technology pattern, carry out online feedback with the adjusting process parameter.
Though be wafer to wafer or batch to batch the advanced technologies control technology, all be that the mode of adopting feedback is carried out the adjustment of technological parameter to next wafer.Yet after a wafer was carried out a technology, its wafer inside distribution of sizes everywhere also may produce uneven situation, for example was that the center wafer part can produce deviation with the peripheral distribution of sizes partly of wafer.When this wafer was continued to carry out next technology, center wafer part may be even more serious with the peripheral deviation partly of wafer, and cause the semiconductor element characteristic of making inconsistent.Because existing advanced technologies control technology only at wafer to wafer or batch to batch controlling, is not repaired same wafer inside in real time, and can't solve the problem of single wafer inside dimension deviation.
Summary of the invention
Purpose of the present invention is exactly that a kind of processing method of semiconductor wafer is being provided, with effective correction with the process deviation in the semiconductor wafer.
The present invention proposes a kind of processing method of semiconductor wafer, at first semiconductor wafer is carried out one first technology.Then, obtain and carry out the continuous data on the semiconductor wafer after first technology, this continuous data reflects single semiconductor wafer inside deviation state everywhere.Then, according to continuous data to carry out one second technology with semiconductor wafer, to compensate the deviation that is produced in first technology.
According to a preferred embodiment of the present invention, the processing method of above-mentioned semiconductor wafer wherein before carrying out second technology, also comprises and utilizes an advanced technologies controller that continuous data is carried out the operating parameter that an algorithm obtains second technology.Then, operating parameter is feedovered to second technology.
According to a preferred embodiment of the present invention, the processing method of above-mentioned semiconductor wafer, wherein first technology be selected from group that depositing operation, photoetching process, etch process and flatening process form one of them.
According to a preferred embodiment of the present invention, the processing method of above-mentioned semiconductor wafer, wherein second technology be selected from group that depositing operation, photoetching process, etch process and flatening process form one of them.
According to a preferred embodiment of the present invention, the processing method of above-mentioned semiconductor wafer, wherein first technology is depositing operation, and second technology is etch process.
According to a preferred embodiment of the present invention, the processing method of above-mentioned semiconductor wafer, wherein first technology is depositing operation, and this second technology is chemical mechanical milling tech.
According to a preferred embodiment of the present invention, the processing method of above-mentioned semiconductor wafer, wherein first technology is etch process, and second technology is depositing operation.
According to a preferred embodiment of the present invention, the processing method of above-mentioned semiconductor wafer, wherein first technology is chemical mechanical milling tech, and second technology is depositing operation.
According to a preferred embodiment of the present invention, the processing method of above-mentioned semiconductor wafer, wherein first technology is photoetching process, and second technology is depositing operation.
According to a preferred embodiment of the present invention, the processing method of above-mentioned semiconductor wafer, wherein first technology is etch process, and second technology is chemical machinery technology.
According to a preferred embodiment of the present invention, the processing method of above-mentioned semiconductor wafer, wherein first technology is etch process, and second technology is etch process.
According to a preferred embodiment of the present invention, the processing method of above-mentioned semiconductor wafer, wherein continuous data comprise group that semiconductor thickness, gash depth and live width form one of them.
The present invention also proposes a kind of processing method of semiconductor wafer, at first semiconductor wafer is carried out one first technology.Then, obtain and carry out one first continuous data on the semiconductor wafer after first technology, this first continuous data reflects single semiconductor wafer inside deviation state everywhere.Then, according to second continuous data to carry out one second technology with semiconductor wafer, to compensate the deviation that is produced in first technology.Afterwards, obtain and carry out one second continuous data on this semiconductor wafer after second technology, this second continuous data reflects same this semiconductor wafer inside deviation state everywhere.Next, according to second continuous data to carry out one the 3rd technology with semiconductor wafer, to compensate the deviation that is produced in first technology and second technology.
According to another preferred embodiment of the present invention, the processing method of above-mentioned semiconductor wafer wherein before carrying out second technology, also comprises and utilizes an advanced technologies controller that first continuous data is carried out one first operating parameter that an algorithm obtains second technology.Then, first operating parameter is feedovered to second technology.
According to another preferred embodiment of the present invention, the processing method of above-mentioned semiconductor wafer wherein before carrying out the 3rd technology, also comprises and utilizes an advanced technologies controller that second continuous data is carried out one second operating parameter that an algorithm obtains the 3rd technology.Then, second operating parameter is feedovered to the 3rd technology.
According to another preferred embodiment of the present invention, the processing method of above-mentioned semiconductor wafer, wherein first technology be selected from group that depositing operation, photoetching process, etch process and flatening process form one of them.
According to another preferred embodiment of the present invention, the processing method of above-mentioned semiconductor wafer, wherein second technology be selected from group that depositing operation, photoetching process, etch process and flatening process form one of them.
According to another preferred embodiment of the present invention, the processing method of above-mentioned semiconductor wafer, wherein the 3rd technology be selected from group that depositing operation, photoetching process, etch process and flatening process form one of them.
According to another preferred embodiment of the present invention, the processing method of above-mentioned semiconductor wafer, wherein first continuous data comprise group that semiconductor thickness, gash depth and live width form one of them.
According to another preferred embodiment of the present invention, the processing method of above-mentioned semiconductor wafer, wherein second continuous data comprise group that semiconductor thickness, gash depth and live width form one of them.
The processing method of semiconductor wafer proposed by the invention is carried out one second technology again to compensate the deviation that is produced in first technology after carrying out one first technology, can revise the process deviation that is produced in the same wafer.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Figure 1A～Fig. 1 C is the schematic diagram that illustrates basic conception of the present invention.
Fig. 2 is the flow chart that illustrates semiconductor wafer processing in one embodiment of the present invention.
Fig. 3 A-3D is the manufacturing process profile of another preferred embodiment of the present invention.
The simple symbol explanation
202: semiconductor wafer is carried out one first technology
204: obtain and carry out the continuous data on the semiconductor wafer after first technology
206: utilize an advanced technologies controller that continuous data is carried out the operating parameter that an algorithm obtains second technology
208: operating parameter is feedovered to second technology
210: to carrying out second technology with semiconductor wafer
300: the semiconductor-based end
302: dielectric layer
304: groove
306: conductor layer
308: lead
D1, D2: the degree of depth
Embodiment
Fig. 1 is the schematic diagram that illustrates basic conception of the present invention.
Please refer to Figure 1A, after carrying out one first technology, the situation that critical size distributes in its wafer be peripheral size partly less than mean value (with "-" expression), and the size of inner circle part greater than mean value (with "+" represent).After finding this process deviation, shown in Figure 1B, adjust in second technology, make the contribution of second technology on same wafer for peripheral size partly greater than mean value (with "+" expression), and the size of inner circle part less than mean value (with "-" expression), to compensate the deviation of first technology, make on the wafer everywhere size be equal to mean value (with " 0 " expression), and obtain the equally distributed best output of critical size (shown in Fig. 1 C).
The processing method of semiconductor wafer of the present invention then, is described.Fig. 2 is the flow chart that illustrates semiconductor wafer processing in one embodiment of the present invention.
Please refer to Fig. 2, step 202 pair semiconductor wafer carries out one first technology, and this first technology for example is depositing operation, photoetching process, etch process, flatening process or other technology.
Step 208 be with operating parameter feedforward to second technology, meaning promptly with this operating parameter as the input parameter that carries out second technology.
In another preferred embodiment, carrying out not reaching technological standards yet after second technology of the foregoing description, also can after second technology is carried out, carry out one the 3rd technology, to compensate the deviation that second technology is produced.
For instance, first technology for example is a depositing operation, when the uneven situation of deposition takes place in depositing operation, can compensate in second technology, this second technology for example is an etch process or chemical mechanical milling tech, the mode of compensation for example is to everywhere rate of etch on the wafer in the etch process, and in the chemical mechanical milling tech on the wafer everywhere grinding rate adjust to revise the deviation in first technology, opposite, also can utilize the adjustment of technology thickness in the depositing operation to compensate to carry out the deviation of thickness behind etch process or the chemical mechanical milling tech.
On the other hand, first technology for example is a photoetching process, the problem of finding the photoresist dimensional discrepancy that developing process produced is checked in the back developing, can compensate in second technology, this second technology for example is an etch process, and the mode of compensation for example is that everywhere rate of etch on the wafer in the etch process is adjusted to revise the deviation in first technology.
In addition, first technology for example is an etch process, after carrying out etch process, find to have the situation of thickness distribution inequality to take place, can compensate in second technology, this second technology for example is a chemical mechanical milling tech, and the mode of compensation for example is that everywhere grinding rate on the wafer in the chemical mechanical milling tech is adjusted to revise the deviation in first technology.
In addition, first technology for example is an etch process, after carrying out etch process, find to have the situation of thickness distribution inequality to take place, can compensate in second technology, this second technology for example is an etch process, and the mode of compensation for example is that everywhere rate of etch on the wafer in the etch process is adjusted to revise the deviation in first technology.
From the above, the processing method of semiconductor wafer proposed by the invention is carried out the process deviation situation that subsequent technique is produced with semiconductor wafer with compensation again in previous technology after carrying out a technology.
Fig. 3 A-3D is the manufacturing process profile of another preferred embodiment of the present invention.
At first, please refer to Fig. 3 A, form a dielectric layer 302 at semiconductor at long-pending the end 300, the material of this dielectric layer 302 for example is a silica, and the method for formation for example is a chemical vapor deposition method.
Then, please refer to Fig. 3 B, form a groove 304 in dielectric layer 302, by obtaining the gash depth data as can be known, the depth distribution of this groove 304 is also inhomogeneous, have a depth D 1 and a depth D 2, and depth D 1 is greater than depth D 2.Wherein, the method that forms this groove 302 is for example prior to forming a patterning photoresist layer on the dielectric layer 302, carries out an etch process again and gets.In addition, cause the uneven reason of depth distribution to be caused by etch process.
Then, please refer to Fig. 3 C, on dielectric layer 302, form a conductor layer 304, and fill up this groove 304.Wherein, the material that forms conductor layer 302 for example is a copper, and the method for formation for example is a chemical vapor deposition method.In another preferred embodiment, before forming conductor layer 304, also can on dielectric layer 302, deposit a barrier layer.
Then, please refer to Fig. 3 D, conductor layer 308 is carried out a flatening process with formation lead 308, and make the degree of depth of groove 304 become depth D 3 and reach consistency.Wherein, this flatening process for example is to carry out a chemical mechanical milling method, and it for example is R1 in depth D 1 grinding rate partly, for example be R2 in depth D 2 grinding rate partly, and R1 is greater than R2.Wherein, the grinding rate R1 and the R2 of this chemical mechanical milling method depth D 1 depth D 2 on semiconductor wafer carry out an algorithm to the continuous data (depth D 1, depth D 2) of dark canal 304 degree of depth and get via an advanced technologies controller.
By the foregoing description as can be known, in the resulting degree of depth behind etch process and inhomogeneous (depth D 1 is greater than depth D 2), and after flatening process is adjusted operating parameter (R1, R2), can the deviation that be caused in the previous technology be compensated, make the degree of depth that obtains can reach consistency.
Further, the foregoing description utilizes the twice processing step to explain, in another preferred embodiment of the present invention, carrying out in semiconductor technology, comprising most steps, utilize invention principle proposed by the invention can after carrying out one processing step, obtain continuous data on the single wafer, utilize the continuous data that is obtained in subsequent technique, to proceed to revise and adjust, to obtain the uniform wafer of size.
In sum, processing method according to semiconductor wafer proposed by the invention, carry out the process deviation that produces behind the processing step at semiconductor wafer, can utilize continuous data to carry out an algorithm to deviation, can obtain operating parameter in the subsequent technique to carry out follow-up processing step, can be in real time and the effective compensation deviation that formerly technology caused on semiconductor wafer, but the reliability of lift elements and promote rate of finished products thus.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art can do a little change and retouching without departing from the spirit and scope of the present invention, thus protection scope of the present invention should with accompanying Claim the person of being defined be as the criterion.
Claims (20)
1, a kind of processing method of semiconductor wafer comprises:
Semiconductor wafer is carried out one first technology;
Obtain and carry out the continuous data on this semiconductor wafer after this first technology, this continuous data reflects same this semiconductor wafer inside critical size everywhere deviation state pockety; And
According to this continuous data same this semiconductor wafer is carried out one second technology, to compensate the critical size deviation pockety that is produced in this first technology.
2, the processing method of semiconductor wafer as claimed in claim 1 wherein before carrying out this second technology, also comprises:
Utilize an advanced technologies controller that this continuous data is carried out the operating parameter that an algorithm obtains this second technology; And
This operating parameter is feedovered to this second technology.
3, the processing method of semiconductor wafer as claimed in claim 1, wherein this first technology be selected from group that depositing operation, photoetching process, etch process and flatening process form one of them.
4, the processing method of semiconductor wafer as claimed in claim 1, wherein this second technology be selected from group that depositing operation, photoetching process, etch process and flatening process form one of them.
5, the processing method of semiconductor wafer as claimed in claim 1, wherein this first technology is depositing operation, and this second technology is etch process.
6, the processing method of semiconductor wafer as claimed in claim 1, wherein this first technology is depositing operation, and this second technology is chemical mechanical milling tech.
7, the processing method of semiconductor wafer as claimed in claim 1, wherein this first technology is etch process, and this second technology is depositing operation.
8, the processing method of semiconductor wafer as claimed in claim 1, wherein this first technology is chemical mechanical milling tech, and this second technology is depositing operation.
9, the processing method of semiconductor wafer as claimed in claim 1, wherein this first technology is photoetching process, and this second technology is depositing operation.
10, the processing method of semiconductor wafer as claimed in claim 1, wherein this first technology is etch process, and this second technology is chemical machinery technology.
11, as the processing method of the described semiconductor wafer of claim I, wherein this first technology is etch process, and this second technology is etch process.
12, the processing method of semiconductor wafer as claimed in claim 1, wherein this continuous data comprise group that semiconductor thickness, gash depth and live width form one of them.
13, a kind of processing method of semiconductor wafer comprises:
Semiconductor wafer is carried out one first technology;
Obtain and carry out one first continuous data on this semiconductor wafer after this first technology, this first continuous data reflects same this semiconductor wafer inside critical size everywhere deviation state pockety;
According to this continuous data same this semiconductor wafer is carried out one second technology, to compensate the critical size deviation pockety that is produced in this first technology;
Obtain and carry out one second continuous data on this semiconductor wafer after this second technology, this second continuous data reflects same this semiconductor wafer inside critical size everywhere deviation state pockety; And
According to this second continuous data same this semiconductor wafer is carried out one the 3rd technology, to compensate the critical size deviation pockety that is produced in this first technology and this second technology.
14, the processing method of semiconductor wafer as claimed in claim 13 wherein before carrying out this second technology, also comprises:
Utilize an advanced technologies controller that this first continuous data is carried out one first operating parameter that an algorithm obtains this second technology; And
This first operating parameter is feedovered to this second technology.
15, the processing method of semiconductor wafer as claimed in claim 13 wherein before carrying out the 3rd technology, also comprises:
Utilize an advanced technologies controller that this second continuous data is carried out one second operating parameter that an algorithm obtains the 3rd technology; And
This second operating parameter is feedovered to the 3rd technology.
16, the processing method of semiconductor wafer as claimed in claim 13, wherein this first technology be selected from group that depositing operation, photoetching process, etch process and flatening process form one of them.
17, the processing method of semiconductor wafer as claimed in claim 13, wherein this second technology be selected from group that depositing operation, photoetching process, etch process and flatening process form one of them.
18, the processing method of semiconductor wafer as claimed in claim 13, wherein the 3rd technology be selected from group that depositing operation, photoetching process, etch process and flatening process form one of them.
19, the processing method of semiconductor wafer as claimed in claim 13, wherein this first continuous data comprise group that semiconductor thickness, gash depth and live width form one of them.
20, the processing method of semiconductor wafer as claimed in claim 13, wherein this second continuous data comprise group that semiconductor thickness, gash depth and live width form one of them.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2005100821324A CN100431096C (en) | 2005-06-29 | 2005-06-29 | Method for processing semiconductor chip |
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| CNB2005100821324A CN100431096C (en) | 2005-06-29 | 2005-06-29 | Method for processing semiconductor chip |
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| CN100431096C true CN100431096C (en) | 2008-11-05 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8229588B2 (en) * | 2009-03-03 | 2012-07-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and system for tuning advanced process control parameters |
| US8224475B2 (en) * | 2009-03-13 | 2012-07-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus for advanced process control |
| CN112366134B (en) * | 2021-01-15 | 2021-05-25 | 晶芯成(北京)科技有限公司 | Chemical mechanical polishing method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030228532A1 (en) * | 2002-03-01 | 2003-12-11 | Applied Materials, Inc. | Method and apparatus for controlling etch processes during fabrication of semiconductor devices |
| US6831742B1 (en) * | 2000-10-23 | 2004-12-14 | Applied Materials, Inc | Monitoring substrate processing using reflected radiation |
| US20050120961A1 (en) * | 2003-12-08 | 2005-06-09 | Matsushita Electric Industrial Co., Ltd. | Rapid thermal processing system, method for manufacuturing the same, and method for adjusting temperature |
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- 2005-06-29 CN CNB2005100821324A patent/CN100431096C/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6831742B1 (en) * | 2000-10-23 | 2004-12-14 | Applied Materials, Inc | Monitoring substrate processing using reflected radiation |
| US20030228532A1 (en) * | 2002-03-01 | 2003-12-11 | Applied Materials, Inc. | Method and apparatus for controlling etch processes during fabrication of semiconductor devices |
| US20050120961A1 (en) * | 2003-12-08 | 2005-06-09 | Matsushita Electric Industrial Co., Ltd. | Rapid thermal processing system, method for manufacuturing the same, and method for adjusting temperature |
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