CN209233811U - One kind trimming circuit - Google Patents
One kind trimming circuit Download PDFInfo
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- CN209233811U CN209233811U CN201821145395.4U CN201821145395U CN209233811U CN 209233811 U CN209233811 U CN 209233811U CN 201821145395 U CN201821145395 U CN 201821145395U CN 209233811 U CN209233811 U CN 209233811U
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Abstract
Present patent application provides one kind and trims circuit, PAD connects metal fuse FUSE by metal wire, resistance R1, metal fuse FUSE other end ground connection, the other end of resistance R1 connects phase inverter I (CMOS1) input terminal, the output termination of phase inverter I (CMOS1) or the input terminal A of door, or the input terminal B of door connects the output end of comparator U, the input of comparator U terminates probe, or the grid of the output termination metal-oxide-semiconductor I of door, the source electrode of metal-oxide-semiconductor I meets power supply AVDD, drain electrode connects II source electrode of metal-oxide-semiconductor, the grid of metal-oxide-semiconductor II connects control section, drain electrode connects the adjustment member of control offset, the offset voltage of chip and the adjustment of temperature drift are carried out using above structure, under small cost, improve the performance indicator of chip.
Description
Technical field
Present patent application is related to semiconductor field more particularly to one kind trims circuit, for adjusting offset voltage
(offset) and its temperature drift improves the overall performance index of chip under small cost.
Background technique
With the development of integrated circuit technology and designing technique, circuit performance requirement is also higher and higher, to meet extensively
Application demand, still, circuit characteristic always will receive the influence of the non-ideal factor of semiconductor fabrication process, these parasitism effect
Should be mainly manifested in current mirror mismatch, resistors match deviation, the temperature coefficient of resistance, resistance capacitance mismatch, resistance absolute deviation,
The temperature coefficient of resistance, resistance capacitance mismatch, transistor mismatch, the temperature drift imbalance introduced by encapsulation stress and input offset voltage
Etc., and these errors are randomness, and there are between chip and chip, between wafer and wafer and batch and batch
Between, effectively it can not be simulated and be predicted by simulation software, by targetedly optimizing technology controlling and process precision, can be subtracted
These few non-ideal factors, but will increase the manufacturing cost of process complexity and chip.
In order to realize high-precision Analogous Integrated Electronic Circuits on standard technology, after manufacturing to chip, adjustment, which becomes, improves
It is reconciliation temperature drift, optimization circuit performance, the mainstream solution for improving chip yield, the technology of trimming is widely used in high-precision
Low imbalance amplifier, low temperature ticket high-performance a reference source, radio circuit, high-performance AD/DA converter and the SoC chip for doing complexity
In, it, can also be by trimming technology to its circuit knot in order to realize different performances on same chip in addition to performance improvement
Structure and a blood parameter are programmed, to meet different application demands.
It is according to document " integrated circuit trim thunder stone more than technology analysis Huang dawn ancestor build rigid Huang Wen Gang once following ",
Presently, there are mainstream integrated circuit trim technology and there is laser trimming, fuse to trim, zener diode, electrical fuse and
Memory trims.
Wherein, the basic principle of laser trimming is by laser beam by making on lens focus to resistive film in TRANSIENT HIGH TEMPERATURE
Under, resistive film is vaporized, and under the effect of continuous laser pulse, with the movement of light beam, is formed one on resistive film and is cut
Mouthful, to change the conductive area (i.e. resistive square block number) of resistance, achieve the purpose that change resistance (increasing resistance value).
Early in just the trimming using thick-film resistor of laser trimming in 1972, film resistor is usually by nichrome or chrome-silicon
Alloy is constituted, local laser heating, to change the microstructure or chemical composition of local material, is increased overall resistance value, is swashed
The border circular areas that Light beam spot diameter is about 3um-10um, moving portion are carried out according to equipment precision slightly difference, mobile spot
Laser bombardment, continuous fine adjustment, while the variation of continuous monitoring resistor value, just stop trimming, essence when obtaining satisfied resistance
Degree precision for other modes is higher, and resistance precision can achieve within 0.05%, while also having high cost, and from
From the point of view of essence, laser resistor trimming is also a kind of damage to resistor body simultaneously.
Utility model content
Present patent application provides one kind to trim circuit, to being adjusted after chip manufacturing, be specifically adjustment temperature drift,
The yield rate of chip is improved, in order to achieve the above object, present patent application uses following technical scheme: including: to trim circuit, visit
Needle, the circuit that trims are placed on chip, and the circuit that trims is connect by lead with the pad in scribe line, and the probe connects
Pad is connect, for introducing electric current to pad.
Preferably, the circuit that trims includes: metal fuse FUSE, resistance R1, phase inverter I (CMOS1), metal-oxide-semiconductor I, MOS
Pipe II, comparator U or door, PAD3 connect metal fuse FUSE, resistance R1, another termination of metal fuse FUSE by metal wire
Ground, the other end of resistance R1 connect phase inverter I (CMOS1) input terminal, the output termination of phase inverter I (CMOS1) or the input terminal of door
The input terminal B of A or door connects the output end of comparator U, the output termination metal-oxide-semiconductor I of the input termination probe or door of comparator U
Grid, the source electrode of metal-oxide-semiconductor I meets power supply AVDD, drain electrode connects II source electrode of metal-oxide-semiconductor, and the grid of metal-oxide-semiconductor II connects control section, drain electrode connects
Control the adjustment member of offset.
It preferably, further include thering is the adjustment member for controlling negative offset to trim part, the adjustment of the negative offset of control
Portions point includes: phase inverter II (CMOS2), metal-oxide-semiconductor III, and the grid of metal-oxide-semiconductor II is connect by lead in phase inverter II
(CMOS2) input terminal, the grid of the output termination metal-oxide-semiconductor III of phase inverter II (CMOS2), the source electrode of metal-oxide-semiconductor III connect through lead
To the common end of metal-oxide-semiconductor I drain electrode and II source electrode of metal-oxide-semiconductor, the drain electrode of metal-oxide-semiconductor III connects the adjustment member for controlling negative offset.
Preferably, the common end that resistance R1 is connect with phase inverter I (CMOS1) also passes through lead and is connected to power vd D.
Preferably, metal fuse FUSE can be imbedded in the passivation layer of scribing rooved face.
The utility model has the advantages that present patent application introduces electric current to PAD by probe, metal fuse is blown, electric current is through resistance R1, anti-
After phase device I (CMOS1), high level is lower level, and through comparator to or the level of door B input terminal be high level, metal-oxide-semiconductor I,
Metal-oxide-semiconductor II is connected, and trims offset, while the tune for controlling negative offset can be also switched to according to the signal that control section inputs
Whole point trim, the offset voltage of chip and the adjustment of temperature drift are carried out using above structure, improves the yields of chip.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of present patent application；
Fig. 2 is to utilize present patent application circuit diagram；
In figure, 1, chip；2, scribe line；3, pad；4, circuit is trimmed；5, probe.
Specific embodiment
As shown in Figure 1 it is found that present patent application includes: probe 5, trims circuit 4, trims circuit 4 and be placed on chip 1, and
It trims circuit 4 to connect by metal wire, probe 5, which draws, connects electric current at the pad (or PAD) 3 into scribe line 2, applies transient voltage
Pulse trims circuit 4 to PAD3, for opening.
The circuit 4 shown in Fig. 2 that trims includes: metal fuse FUSE, resistance R1, phase inverter I (CMOS1), metal-oxide-semiconductor I, MOS
Pipe II, comparator U or door, PAD3 connect metal fuse FUSE, resistance R1, another termination of metal fuse FUSE by metal wire
Ground, the other end of resistance R1 connect phase inverter I (CMOS1) input terminal, the output termination of phase inverter I (CMOS1) or the input terminal of door
The input terminal B of A or door connects the output end of comparator U, the output termination metal-oxide-semiconductor I of the input termination probe or door of comparator U
Grid, the source electrode of metal-oxide-semiconductor I meets power supply AVDD, drain electrode connects II source electrode of metal-oxide-semiconductor, and the grid of metal-oxide-semiconductor II connects control section, drain electrode connects
Control the adjustment member of offset.
Preferably, the common end that resistance R1 is connect with phase inverter I (CMOS1) also passes through lead and is connected to power vd D.
It preferably, further include thering is the adjustment member for controlling negative offset to trim part, the adjustment of the negative offset of control
Portions point includes: phase inverter II (CMOS2), metal-oxide-semiconductor III, and the grid of metal-oxide-semiconductor II is connect by lead in phase inverter II
(CMOS2) input terminal, the grid of the output termination metal-oxide-semiconductor III of phase inverter II (CMOS2), the source electrode of metal-oxide-semiconductor III connect through lead
To the common end of metal-oxide-semiconductor I drain electrode and II source electrode of metal-oxide-semiconductor, the drain electrode of metal-oxide-semiconductor III connects the adjustment member for controlling negative offset.
Preferably, metal fuse FUSE can be imbedded in the passivation layer on 2 surface of scribe line.
Preferably, it can be set that above-mentioned multiple groups are independent to trim circuit in wafer, positioned at different chips and scribe line 2
In, it is uniformly controlled using control section, the voltage swing that can be trimmed as needed, carries out any selection for trimming circuit, more
Item trims the combination selection of circuit.
When normal condition, that is, be in original state shown in Fig. 2 when, do not trim offset:FUSE ground connection, resistance R1 with
The common end FUSE voltage is low level, and resistance R1 and phase inverter I (CMOS1) common end level are low (0), inverted device I
(CMOS1) low level gets higher level change afterwards (0 becomes 1)；Or it is high level that the A input terminal of door, which is the output end of high level or door,
Metal-oxide-semiconductor I is unsatisfactory for Ugs > 0 and is in off state, does not trim offset.
When trimming offset working condition, control section provides control signal (high level), and probe 5 introduces electric current extremely
PAD3, under transient voltage, metal fuse FUSE is blown, and after resistance R1, phase inverter I (CMOS1), high level is lower level electric current
(1 become 0), and through comparator to or the level of door B input terminal be high level, metal-oxide-semiconductor I, metal-oxide-semiconductor II are connected, and trim offset.
Likewise, control section provides negative trim and controls signal (low electricity when trimming the adjustment member for controlling negative offset
It is flat), metal-oxide-semiconductor II ends at this time, and low level becomes high level to inverted device II (CMOS2) afterwards, and metal-oxide-semiconductor III is connected, and trims control
Make the adjustment member of negative offset.
The principles and effects of present patent application are only illustrated in above-described embodiment, not for limitation this patent Shen
Please.Any person skilled in the art can all carry out above-described embodiment under the spirit and scope without prejudice to present patent application
Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the revealed essence of present patent application
All equivalent modifications or change completed under mind and technical idea, the claim that should be asked by this patent are covered.
Claims (5)
1. one kind trims circuit, comprising: trim circuit (4), probe (5), it is characterised in that: the circuit (4) that trims is placed in core
On piece (1), described trim circuit (4) are connect by lead with the pad (3) in scribe line (2), and the probe (5) connects pad
(3), for introducing electric current to pad (3).
2. one kind according to claim 1 trims circuit, it is characterised in that: the circuit (4) that trims includes: metal fuse
FUSE, resistance R1, phase inverter I (CMOS1), metal-oxide-semiconductor I, metal-oxide-semiconductor II, comparator U or door, pad (3) are connected by metal wire
Metal fuse FUSE, resistance R1, metal fuse FUSE other end ground connection, the other end of resistance R1 connect phase inverter I (CMOS1) input
End, the output termination or the input terminal A of the door or input terminal B of door of phase inverter I (CMOS1) connect the output end of comparator U, compare
The grid of the output termination metal-oxide-semiconductor I of the input termination probe or door of device U, the source electrode of metal-oxide-semiconductor I meets power supply AVDD, drain electrode meets MOS
II source electrode of pipe, the grid of metal-oxide-semiconductor II connects control section, drain electrode connects the adjustment member of control offset.
3. one kind according to claim 2 trims circuit, it is characterised in that: further include having the adjustment section for controlling negative offset
Divide and trim part, the adjustment member part of the negative offset of control includes: phase inverter II (CMOS2), metal-oxide-semiconductor III, metal-oxide-semiconductor II
Grid the input terminal in phase inverter II (CMOS2) is connect by lead, the output termination metal-oxide-semiconductor III of phase inverter II (CMOS2)
Grid, the source electrode of metal-oxide-semiconductor III are connected to the common end of metal-oxide-semiconductor I drain electrode and II source electrode of metal-oxide-semiconductor through lead, and the drain electrode of metal-oxide-semiconductor III connects control
Make the adjustment member of negative offset.
4. one kind according to claim 2 trims circuit, it is characterised in that: resistance R1 is connect with phase inverter (CMOS1)
Common end also passes through lead and is connected to power vd D.
5. one kind according to claim 2 trims circuit, it is characterised in that: metal fuse FUSE can be imbedded in scribe line
(2) in the passivation layer on surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821145395.4U CN209233811U (en) | 2018-07-19 | 2018-07-19 | One kind trimming circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821145395.4U CN209233811U (en) | 2018-07-19 | 2018-07-19 | One kind trimming circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209233811U true CN209233811U (en) | 2019-08-09 |
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ID=67497172
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201821145395.4U Active CN209233811U (en) | 2018-07-19 | 2018-07-19 | One kind trimming circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN209233811U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113162605A (en) * | 2020-09-03 | 2021-07-23 | 成都利普芯微电子有限公司 | Chip trimming circuit and trimming method |
-
2018
- 2018-07-19 CN CN201821145395.4U patent/CN209233811U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113162605A (en) * | 2020-09-03 | 2021-07-23 | 成都利普芯微电子有限公司 | Chip trimming circuit and trimming method |
| CN113162605B (en) * | 2020-09-03 | 2022-11-01 | 深圳利普芯微电子有限公司 | Chip trimming circuit and trimming method |
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