CN100359679C - Face-down bonding structure with low-melting point convex point and making method - Google Patents
Face-down bonding structure with low-melting point convex point and making method Download PDFInfo
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- CN100359679C CN100359679C CNB2005100152081A CN200510015208A CN100359679C CN 100359679 C CN100359679 C CN 100359679C CN B2005100152081 A CNB2005100152081 A CN B2005100152081A CN 200510015208 A CN200510015208 A CN 200510015208A CN 100359679 C CN100359679 C CN 100359679C
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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Abstract
The present invention provides a face down bonding structure with a low melting point and convex points and a manufacture method. The convex point manufacture method is improved on the base of the manufacture of general pure gold convex points and bonding pads, which use a Ti/Au structure, and one layer of Au/Sn alloy or other low melting point alloy layers are evaporated on the convex points or the bonding pads corresponding to the convex points; the manufacture method avoids direct friction among the pure gold convex points and the bonding pads, which performs the function of protecting devices. When the convex points are welded, thermal pressure bonding and ultrasonic bonding are combined; compared with the ultrasonic bonding of the pure gold convex points, bonding strength is increased.
Description
Technical field
The present invention relates to a kind of high-power illumination device, particularly a kind of face-down bonding structure of power light-emitting diode belongs to field of semiconductor photoelectron technique.
Background technology
From angle of practical application, installing and using the great power LED device simple, that volume is less relatively will replace traditional low-power LED device in the major part illumination is used.Its benefit is very tangible, and the lighting that low power LED forms is in order to reach the needs of illumination, just must concentrate the luminous energy of many LED can reach designing requirement; Its shortcoming is a complex circuit, and it is not smooth to dispel the heat, for the complicated power supply circuits of the essential design of the current-voltage correlation between each LED of balance.By contrast, the power of great power LED monomer is much larger than the single led summation that equals several low-power LEDs, and supply line is simple relatively, and radiator structure is perfect, and physical characteristic is stable.Thus, the great power LED device replaces the low-power LED device to become the main flow semiconductor lighting device trend that will be inevitable.For the method for packing of great power LED device, can not simply apply mechanically the method for packing and the encapsulating material of traditional low-power LED device.Big dissipation power, big caloric value, high light extraction efficiency have proposed new higher requirement for existing encapsulating material, sealed in unit and packaging technology.
" encapsulation of the high-power illumination level LED " literary composition that is published in 2004 the 5th phases of periodical " semiconductor lighting " has been set forth the method for present stage solution high-power LED encapsulation problem emphatically in conjunction with practical operation and technological requirement.Wherein mentioned the flip chip method that becomes great power LED main flow method for packing, this method is at first prepared the large scale flip chip bonding led chip (Flip Chip LED) that is fit to eutectic welding electrode bump pad, prepare the silicon base plate of corresponding size simultaneously, produce the golden conductive layer that welds for eutectic thereon and draw conductive layer (ultrasonic gold ball bonding receiving electrode is referred to as salient point among the present invention).Then, utilize the eutectic welding equipment that large scale led chip and silicon base plate are welded together.
When adopting flip chip method package power LED device, the tube core flip chip bonding of power LED is connected on the silicon base plate, then the silicon base plate of finishing the upside-down mounting welding is packed in heat sink and the shell, bonding wire encapsulates.This encapsulation is for getting optical efficiency, heat dispersion, and the design that strengthens working current density all is best.But for heat conductivility and the electric conductivity that improves device, the salient point area of upside-down mounting welding becomes big, has brought certain difficulty to welding.Wherein proof gold welding electrode fusing point is higher, generally needs to adopt ultra-sonic welded, easily device is produced damage and the ultrasonic power that the welding of large tracts of land salient point is adopted is too high.
Summary of the invention
The invention provides two kinds welding electrode position fusing point is reduced, improve the flip chip bonding Welding Structure of device welding performance, and provide manufacture method respectively, to address the above problem.
For solving the problems of the technologies described above, two kinds of flip chip bonding packaging structures that the invention provides, a kind of be with stud bump making on silicon base plate, another kind be with stud bump making on device electrode.Following face-down bonding structure is preceding a kind of form:
A kind of face-down bonding structure, comprise have a plurality of be produced on the silicon base plate salient point and with the described silicon base plate device of bonding mutually, be manufactured with metal Ti under the salient point/Au metal level between salient point and the silicon base plate, wherein the n electrode pair is answered under the salient point of salient point and is deposited with passivation layer between the metal Ti/Au layer and silicon base plate; Have on the electrode of device with silicon base plate on the corresponding a plurality of bump pad of salient point, be manufactured with metal Ti under the pad/Au layer under the bump pad; Be coated with Au/Sn or Pb/Sn alloy-layer on salient point or the pad.
The welded making of this kind flip chip bonding mainly comprise have a plurality of be produced on the silicon base plate convex point production method and with the described silicon base plate manufacture method of bump pad on the device of bonding mutually:
A. the bump pad on the device electrode is made according to following method:
(1) tube core etching n electrode;
(2) photoetching p, n electrode pattern, evaporation or sputter device metal ohmic contact;
(3) metallic pattern under photoetching p, the n electrode pad, evaporation or sputter buffering metal Ti/Au;
(4) photoetching p, n electrode pad metallic pattern, evaporation or sputter weld metal Au;
B. the salient point on the silicon base plate is made according to following method:
1) insulating barrier under the making silicon base plate n electrode salient point
(1) silicon base plate deposit SiO
2
(2) optical graving is made n electrode SiO
2The protection figure;
(3) corrosion SiO
2, keep n electrode SiO2 as insulating barrier;
2) make metal under the silicon base plate salient point
(1) metallic pattern under the photoetching making salient point;
(2) silicon base plate sputter or evaporated metal Ti/Au;
(3) silicon base plate removes photoresist, and peels off the Ti/Au alloy;
3) make salient point
(1) photoetching making salient point figure;
(2) electroplate Au, make salient point;
C. according to following method 1) make salient point low-melting alloy layer or according to following method 2) make electrode bump pad low-melting alloy layer:
1) the low-melting alloy layer on the making salient point
(1) evaporation or sputter Au/Sn or Pb/Sn alloy on the silicon base plate of having electroplated salient point;
(2) peel off Au/Sn or Pb/Sn alloy;
2) the low-melting alloy layer on the making welding electrode bump pad
(1) evaporation or sputter Au/Sn or Pb/Sn alloy on the epitaxial wafer of having made the welding electrode bump pad;
(2) peel off Au/Sn or Pb/Sn alloy.
Be with flip chip bonding Welding Structure and the manufacture method of stud bump making on device electrode below:
A kind of face-down bonding structure, comprise have a plurality of be produced on the device electrode salient point and with the described salient point silicon base plate of bonding mutually, be manufactured with metal Ti under the salient point/Au metal level between salient point and the device electrode; Have on the silicon base plate and the corresponding a plurality of bump pad of device electrode salient point, be manufactured with metal Ti under the pad/Au layer under the bump pad, wherein the n electrode pair is answered under the pad of bump pad and is deposited with passivation layer between the metal Ti/Au layer and silicon base plate; Be coated with Au/Sn or Pb/Sn alloy-layer on salient point or the pad.
The manufacture method of above-mentioned welding result mainly comprise have a plurality of manufacture methods that are produced on salient point on the device electrode and with the described salient point manufacture method of bump pad on the silicon base plate of bonding mutually:
A. the salient point on the device electrode is made according to following method:
(1) tube core etching n electrode;
(2) photoetching p, n electrode pattern, evaporation or sputter device metal ohmic contact;
(3) metallic pattern under the photoetching making salient point, sputter or evaporated metal Ti/Au;
(4) epitaxial wafer removes photoresist, and peels off the Ti/Au alloy;
(5) photoetching making salient point figure;
(6) electroplate Au, make salient point;
B. the bump pad on the silicon base plate is made according to following method:
1) insulating barrier under the making silicon base plate n electrode bump pad
(1) silicon base plate deposit SiO
2
(2) optical graving is made n electrode SiO
2The protection figure;
(3) corrosion SiO
2, keep n electrode SiO2 as insulating barrier;
2) make metal under the silicon base plate bump pad
(1) metallic pattern under the photoetching making bump pad;
(2) silicon base plate sputter or evaporated metal Ti/Au;
(3) silicon base plate removes photoresist, and peels off the Ti/Au alloy;
3) photoetching p, n electrode pad metallic pattern, evaporation or sputter weld metal Au
C. according to following method 1) make salient point low-melting alloy layer or according to following method 2) make electrode bump pad low-melting alloy layer:
1) the low-melting alloy layer on the making salient point
(1) evaporation or sputter Au/Sn or Pb/Sn alloy on the epitaxial wafer of having electroplated salient point;
(2) peel off Au/Sn or Pb/Sn alloy;
2) the low-melting alloy layer on the making bump pad
(1) evaporation or sputter Au/Sn or Pb/Sn alloy on the silicon chip of having made the welding electrode bump pad;
(2) peel off Au/Sn or Pb/Sn alloy.
The invention has the beneficial effects as follows at large power semiconductor device encapsulation requirement, employing has the flip chip bonding Welding Structure of low-melting point convex point, evaporation or sputter layer of Au/Sn or Pb/Sn alloy on common au bump, reduced salient point fusing point, strengthened the weld strength of salient point.During welding the pad temperature is brought up to Au/Sn or Pb/Sn alloy melting point and salient point hot pressing, add ultrasonicly behind the temperature stabilization, realize that gold connects gold solder.The Au/Sn alloy has played good adhesive attraction between proof gold welding electrode and pad, strengthened weld strength.The Au/Sn alloy has also played certain cushioning effect to the ultrasonic friction between au bump and the pad in addition, has reduced device damage effectively.
Description of drawings
Fig. 1 is the end view that is positioned at the proof gold bump structure on the silicon base plate
Fig. 2 is the end view with the corresponding proof gold pad structure of proof gold salient point
Fig. 3 is the end view of the bump structure of covering layer of Au Sn alloy
Fig. 4 is corresponding with salient point, covers the end view of the pad structure of layer of Au Sn alloy on the bump pad
Embodiment
The present invention is further described below in conjunction with the embodiment of the encapsulating structure of accompanying drawing and single salient point and welding electrode:
Salient point when all not covering the Au/Sn alloy and pad structure corresponding with it are seen Fig. 1 and Fig. 2 respectively.
Fig. 1 is the end view that is positioned at the proof gold bump structure on the silicon base plate 1.Among the figure, 4 times evaporations of n electrode salient point have metal Ti under the salient point/Au layer 3,, it highly is 0.06 μ m, adopts circular configuration, diameter is 180 μ m.Passivation layer 2 between metal Ti under the salient point/Au layer 3 and the silicon base plate is SiO
2, thickness is 0.3 μ m.Salient point 4 is electroplated by proof gold and is formed, and it is shaped as circle, and diameter 160 μ m highly are 5 μ m.
Fig. 2 is the end view with the corresponding proof gold pad structure of proof gold salient point.Metal is circular Ti/Au layer under the pad that figure bumps pad is made for 7 times, highly is 0.06 μ m, diameter 200 μ m.
It among Fig. 2 end view with salient point corresponding bonding pad structure.Among the figure, bump pad 7 is the proof gold pad on the device electrode, and pad metal Au layer is circular, highly is 2 μ m, diameter 180 μ m.Evaporation has metal Ti under the pad/Au layer 8 between pad 7 and the device solder joint 6, and it highly is 0.03 μ m, diameter 200 μ m.
Embodiment 1:
The end view of bump structure among the figure, covers layer of Au/Sn alloy-layer 5 or other low-melting alloy layer such as Pb/Sn referring to Fig. 3 on the salient point 4, thickness is 0.01 μ m.Au/Sn alloy-layer 5 can utilize evaporation technology to form, and also can adopt sputtering technology to form.See Fig. 2 with the end view of salient point corresponding bonding pad structure.
Embodiment 2:
The end view of bump structure is seen Fig. 1.See Fig. 4 with the end view of salient point corresponding bonding pad structure, among the figure, cover layer of Au/Sn alloy-layer 5 or other low-melting alloy layer such as Pb/Sn on the pad 7, thickness is 0.01 μ m.Au/Sn alloy-layer 5 can utilize evaporation technology to form, and also can utilize sputtering technology to form.
Embodiment 3:
The end view of bump structure among the figure, covers layer of Au/Sn alloy-layer 5 or other low-melting alloy layer such as Pb/Sn referring to Fig. 3 on the salient point 4, thickness is 0.01 μ m.Au/Sn alloy-layer 5 can utilize evaporation technology to form, and also can adopt sputtering technology to form.See Fig. 4 with the end view of salient point corresponding bonding pad structure, among the figure, also cover layer of Au/Sn alloy-layer 5 or other low-melting alloy layer such as Pb/Sn on the pad 7, thickness is 0.01 μ m.Au/Sn alloy-layer 5 can utilize evaporation technology to form, and also can utilize sputtering technology to form.
Introduce a kind of concrete manufacture method that can realize welded pad electrode of flip chip bonding of the present invention and salient point below in detail.
One, bump process
1. silicon base plate n electrode dielectric layer is made
(1) the thick SiO of silicon base plate deposit 0.3 μ m
2
(2) optical graving is made n electrode silicon dioxide protection figure;
(2) HF corrosion SiO
2, keep n electrode SiO
2, finish the n electrode dielectric layer and make.
2. metal is made under the silicon base plate salient point
(1) metallic pattern under the photoetching making salient point;
(2) silicon base plate sputter or evaporate 0.06 μ m Ti/Au;
(3) silicon base plate removes photoresist, and peels off the Ti/Au alloy, finishes metal making under the salient point.
3. stud bump making
(1) is coated with thick glue, photoetching making salient point figure;
(2) electroplate the thick Au of 5 μ m, make salient point.
4, the salient point low-melting alloy is made
(1) Au/Sn or the Pb/Sn alloy alloy of evaporation or sputter 0.01 μ m thickness on the silicon chip of having electroplated salient point;
(2) remove thick glue, peel off Au/Sn or Pb/Sn alloy, finish salient point low-melting alloy layer and make.
Two, tube core technology
1 etching n electrode
(1) the thick SiO of epitaxial wafer deposit 0.4 μ m
2
(2) epitaxial wafer photoetching making table top figure;
(3) dry etching raceway groove SiO
2, reactive ion etching (RIE) table top;
(4) photoetching n electrode pattern;
(5) dry etching n electrode raceway groove SiO
2, reactive ion etching (RIE) n electrode.
2 make electrode
(1) HF removes SiO
2
(2) photoetching p, n electrode pattern, evaporation or sputter device metal ohmic contact Ni/Au;
(3) photoetching p, n electrode pattern, evaporation and buffering metal Ti/Au;
(4) photoetching p, n electrode pattern, evaporation weld metal Au.
The embodiment of above-mentioned manufacture method is the manufacture method of making the low-melting point metal alloy layer on the silicon base plate salient point.Manufacture method as for other embodiment, and on electrode, make salient point, on the corresponding site of silicon base plate, make flip chip bonding Welding Structure of pad and preparation method thereof, because resemble process, and in technical scheme, illustrate, and can directly derive by each above-mentioned embodiment, repeat no more here.
Need to prove, here the detailed explanation that has been center deployment with embodiments of the invention, the imbody of described optimal way or some characteristic, should be understood to this specification only is to describe invention by the mode that provides embodiment, in fact on some details of composition, structure and manufacture method and use, can change to some extent, for example, each of salient point or pad layer thickness of structure, shape, size and concrete process etc. all can change to some extent, and these distortion and using all should belong in the scope of the present invention.In addition, the various processes of mentioning in the present invention, for example reactive ion etching, dry etching, evaporation, sputters etc. all belong to the manufacture method of semi-conductor photoelectronic field routine, and those skilled in the art can realize the present invention without creative work.
Claims (6)
1, a kind of face-down bonding structure, comprise have a plurality of be produced on the silicon base plate salient point and with the described silicon base plate device of bonding mutually, it is characterized in that being manufactured with between described salient point and the silicon base plate metal Ti under the salient point/Au metal level, wherein the n electrode pair is answered under the salient point of salient point and is deposited with passivation layer between the metal Ti/Au layer and silicon base plate; Have on the electrode of described device with silicon base plate on the corresponding a plurality of bump pad of salient point, be manufactured with metal Ti under the pad/Au layer under the bump pad; Be coated with Au/Sn or Pb/Sn alloy-layer on salient point or the pad.
2, face-down bonding structure according to claim 1, the described salient point that is produced on the silicon base plate is the proof gold salient point, highly is 5 μ m, diameter 160 μ m; Metal Ti under the salient point/Au layer is circular, highly is 0.06 μ m, diameter 180 μ m; Bump pad is the proof gold pad on the described device electrode, and pad metal Au layer is circular, highly is 2 μ m, diameter 180 μ m; Metal is circular Ti/Au layer under the pad of making under the described bump pad, highly is 0.06 μ m, diameter 200 μ m; Be coated with Au/Sn or Pb/Sn alloy-layer that thickness is 0.01 μ m on described proof gold salient point or the bump pad; Passivation layer under the salient point of described n electrode salient point between metal Ti/Au and the silicon base plate is SiO
2, thickness is 0.3 μ m.
3, a kind of face-down bonding structure manufacture method, comprise have a plurality of be produced on the silicon base plate convex point production method and with the described silicon base plate manufacture method of bump pad on the device of bonding mutually, its characteristics are:
A. the bump pad on the device electrode is made according to following method:
(1) tube core etching n electrode;
(2) photoetching p, n electrode pattern, evaporation or sputter device metal ohmic contact;
(3) metallic pattern under photoetching p, the n electrode pad, evaporation or sputter buffering metal Ti/Au;
(4) photoetching p, n electrode pad metallic pattern, evaporation or sputter weld metal Au;
B. the salient point on the silicon base plate is made according to following method:
1) insulating barrier under the making silicon base plate n electrode salient point
(1) silicon base plate deposit SiO
2
(2) optical graving is made n electrode SiO
2The protection figure;
(3) corrosion SiO
2, keep n electrode SiO2 as insulating barrier;
2) make metal under the silicon base plate salient point
(1) metallic pattern under the photoetching making salient point;
(2) silicon base plate sputter or evaporated metal Ti/Au;
(3) silicon base plate removes photoresist, and peels off the Ti/Au alloy;
3) make salient point
(1) photoetching making salient point figure;
(2) electroplate Au, make salient point;
C. according to following method 1) make the salient point alloy-layer or according to following method 2) make electrode bump pad alloy-layer:
1) alloy-layer on the making salient point
(1) evaporation or sputter Au/Sn or Pb/Sn alloy on the silicon base plate of having electroplated salient point;
(2) peel off Au/Sn or Pb/Sn alloy;
2) alloy-layer on the making welding electrode bump pad
(1) evaporation or sputter Au/Sn or Pb/Sn alloy on the epitaxial wafer of having made the welding electrode bump pad;
(2) peel off Au/Sn or Pb/Sn alloy.
4, a kind of face-down bonding structure, comprise have a plurality of be produced on the device electrode salient point and with the described salient point silicon base plate of bonding mutually, it is characterized in that being manufactured with between described salient point and the device electrode metal Ti under the salient point/Au metal level; Have on the described silicon base plate and the corresponding a plurality of bump pad of device electrode salient point, be manufactured with metal Ti under the pad/Au layer under the bump pad, wherein the n electrode pair is answered under the pad of bump pad and is deposited with passivation layer between the metal Ti/Au layer and silicon base plate; Be coated with Au/Sn or Pb/Sn alloy-layer on salient point or the pad.
5, a kind of face-down bonding structure according to claim 6, the described salient point that is produced on the device electrode is the proof gold salient point, highly is 5 μ m, diameter 160 μ m; Metal Ti under the salient point/Au layer is circular, highly is 0.06 μ m, diameter 180 μ m; Bump pad is the proof gold pad on the described silicon base plate, and pad metal Au layer is circular, highly is 2 μ m, diameter 180 μ m; Metal is circular Ti/Au layer under the pad of making under the described bump pad, highly is 0.06 μ m, diameter 200 μ m; Be coated with Au/Sn or Pb/Sn alloy-layer that thickness is 0.01 μ m on described proof gold salient point or the bump pad; Passivation layer under the pad of described n electrode bump pad between metal Ti/Au and the silicon base plate is SiO
2, thickness is 0.3 μ m.
6, a kind of face-down bonding structure manufacture method, comprise have a plurality of manufacture methods that are produced on salient point on the device electrode and with the described salient point manufacture method of bump pad on the silicon base plate of bonding mutually, its characteristics are:
A. the salient point on the device electrode is made according to following method:
(1) tube core etching n electrode;
(2) photoetching p, n electrode pattern, evaporation or sputter device metal ohmic contact;
(3) metallic pattern under the photoetching making salient point, sputter or evaporated metal Ti/Au;
(4) epitaxial wafer removes photoresist, and peels off the Ti/Au alloy;
(5) photoetching making salient point figure;
(6) electroplate Au, make salient point;
B. the bump pad on the silicon base plate is made according to following method:
1) insulating barrier under the making silicon base plate n electrode bump pad
(1) silicon base plate deposit SiO
2
(2) optical graving is made n electrode SiO
2The protection figure;
(3) corrosion SiO
2, keep n electrode SiO2 as insulating barrier;
2) make metal under the silicon base plate bump pad
(1) metallic pattern under the photoetching making bump pad;
(2) silicon base plate sputter or evaporated metal Ti/Au;
(3) silicon base plate removes photoresist, and peels off the Ti/Au alloy;
3) photoetching p, n electrode pad metallic pattern, evaporation or sputter weld metal Au
C. according to following method 1) make the salient point alloy-layer or according to following method 2) make electrode bump pad alloy-layer:
1) alloy-layer on the making salient point
(1) evaporation or sputter Au/Sn or Pb/Sn alloy on the epitaxial wafer of having electroplated salient point;
(2) peel off Au/Sn or Pb/Sn alloy;
2) alloy-layer on the making bump pad
(1) evaporation or sputter Au/Sn or Pb/Sn alloy on the silicon chip of having made the welding electrode bump pad;
(2) peel off Au/Sn or Pb/Sn alloy.
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|---|---|---|---|
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|---|---|---|---|
| CNB2005100152081A CN100359679C (en) | 2005-09-27 | 2005-09-27 | Face-down bonding structure with low-melting point convex point and making method |
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| CN100359679C true CN100359679C (en) | 2008-01-02 |
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| CN102543898A (en) * | 2012-01-17 | 2012-07-04 | 南通富士通微电子股份有限公司 | Cylindrical bump packaging structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040188378A1 (en) * | 2003-03-25 | 2004-09-30 | Advanced Semiconductor Engineering, Inc. | Bumping process |
| CN1552951A (en) * | 2003-05-31 | 2004-12-08 | 香港科技大学 | Technology for electrolyzing and manufacturing micro-gap counter-assembled welding projects |
| US20040266162A1 (en) * | 2003-06-30 | 2004-12-30 | Advanced Semiconductor Engineering, Inc. | Semiconductor wafer package and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040188378A1 (en) * | 2003-03-25 | 2004-09-30 | Advanced Semiconductor Engineering, Inc. | Bumping process |
| CN1552951A (en) * | 2003-05-31 | 2004-12-08 | 香港科技大学 | Technology for electrolyzing and manufacturing micro-gap counter-assembled welding projects |
| US20040266162A1 (en) * | 2003-06-30 | 2004-12-30 | Advanced Semiconductor Engineering, Inc. | Semiconductor wafer package and manufacturing method thereof |
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Assignee: Tianjin Polytechnic Hiyu Semiconductor Lighting Co., Ltd. Assignor: Tianjin Polytechnic University Contract fulfillment period: 2009.7.13 to 2014.3.1 contract change Contract record no.: 2009120000212 Denomination of invention: Face-down bonding structure with low-melting point convex point and making method Granted publication date: 20080102 License type: Exclusive license Record date: 2009.9.14 |
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| LIC | Patent licence contract for exploitation submitted for record |
Free format text: EXCLUSIVE LICENSE; TIME LIMIT OF IMPLEMENTING CONTACT: 2009.7.13 TO 2014.3.1; CHANGE OF CONTRACT Name of requester: TIANJIN GONGDA HAIYU SEMICONDUCTOR LIGHTING CO., L Effective date: 20090914 |
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| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080102 Termination date: 20120927 |