CN100347856C - Package with multiple wafers and packaging method thereof - Google Patents
Package with multiple wafers and packaging method thereof Download PDFInfo
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- CN100347856C CN100347856C CNB2004100809192A CN200410080919A CN100347856C CN 100347856 C CN100347856 C CN 100347856C CN B2004100809192 A CNB2004100809192 A CN B2004100809192A CN 200410080919 A CN200410080919 A CN 200410080919A CN 100347856 C CN100347856 C CN 100347856C
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
The present invention relates to a packaging element with multiple wafers and a packaging method thereof. The packaging element comprises a base plate, at least three wafers and a soft electric connection base plate, wherein the soft electric connection base plate is used for electrical connection and primary fixed connection. Firstly, the wafers are correspondingly and electrically connected with one another; then, the soft electric connection base plate is bent and rolled after the wafers are fixedly connected to each predetermined connection port at two opposite side surfaces of the soft electric connection base plate, and the wafers are orderly stacked and connected from top to bottom; finally, the wafers are electrically connected to and fixedly welded on the base plate. A package is finished by the packaging element of at least the three wafers to save the used number of the soft electric connection base plate, the manufacturing steps are decreased and the production cost is lowered.
Description
Technical field
The invention relates to a kind of packaging part and method for packing thereof, be meant a kind of packaging part and method for packing thereof that utilizes soft electrical connection substrate package especially.
Background technology
Consult Fig. 1; traditionally; most wafers 11 are packaged into the encapsulation process of single packaging part 12; be after earlier substrate 13, wafer 11 being piled up weldering even in regular turn; form the gold thread 14 that majority is electrically connected substrate 13, wafer 11 with corresponding to each other in the routing mode again; and then irritate mould and form the packing colloid 15 that coats those wafers 11 of protection, gold thread 14, at last substrate 13 bottom surfaces lay can with most tin balls 16 that circuit board (scheming not shown) is electrically connected after, finish main encapsulation process.
But the packaging part of finishing with these encapsulation processs 12, be electrically connected kenel, stack manner owing to be subject to profile, the wiring of wafer 11, and the arrangement restriction of board routing etc., so demand that also can't develop along with electronic product fully, and have fully in response to complicated and diversified calculation function, simultaneously, the cost of these packaged types also with single packaging part 12 in desire stacked wafers 11 numbers be directly proportional and climb and increase.
And simultaneously, utilize the metallic conduction thing as circuit layout, and cooperate polymer to be pressed into the soft electrical connection substrate of single or multiple lift formula structure, has low price, the design circuit layout is simple, advantages such as convenience, therefore, how developing to introduce utilizes soft electrical connection substrate to replace routing, the electrical connection kenel of wiring, and most wafer package are become single packaging part, advantage by soft electrical connection substrate itself, and make packaging part can have along with the demand of electronic product development in response to the function of complicated various computing, simultaneously, can significantly reduce the procedure for producing cost again, be the new development of industry, the direction of research.
Summary of the invention
Purpose of the present invention is promptly providing a kind of packaging part and method for packing thereof that is packaged with a plurality of wafers, utilizes single soft electrical connection substrate to encapsulate most wafers, is integrated in the packaging part with the function with each wafer, and reduces the procedure for producing cost simultaneously.
So a kind of packaging part that is packaged with a plurality of wafers of the present invention comprises one first wafer, one second wafer, one the 3rd wafer, and a soft electrical connection substrate that can twist.
This soft electrical connection substrate has one first weldering crystal layer, and second a weldering crystal layer in contrast to this first weldering crystal layer.
This first wafer weldering is brilliant on this first weldering crystal layer, this is second years old, remotely weldering is brilliant on this second weldering crystal layer mutually respectively for three wafers, and make this first, two, three wafers borrow this soft electrical connection substrate correspond to each other electric work can integrate, and this soft electrical connection substrate twists, this first weldering crystal layer is connected corresponding to zone and this first wafer that this second weldering crystal layer is welded with this second wafer, and this second wafer stacking is linked on this first wafer, simultaneously, this first weldering crystal layer has the zone of the 3rd wafer and this second wafer to be connected corresponding to this second weldering crystal layer weldering crystalline substance, and the 3rd wafer stacking is linked on this second wafer.
In addition, a kind of method for packing with packaging part of a plurality of wafers of the present invention comprises following steps.
Step 1: the preparation one soft electrical connection substrate that can twist, make have one first weldering crystal layer, second a weldering crystal layer, in contrast to this first weldering crystal layer is arranged at this first weldering, first connectivity port, on crystal layer and is arranged at second connectivity port on this second weldering crystal layer, and one is arranged on this second weldering crystal layer and relatively away from the 3rd connectivity port of this second connectivity port.
Step 2: respectively with one first wafer, one second wafer, and brilliant this first connectivity port, this second connectivity port on this soft electrical connection substrate of one the 3rd wafer difference weldering accordingly, with the 3rd connectivity port.
Step 3: this soft electrical connection substrate that twists makes this first weldering crystal layer be connected corresponding to zone and this first wafer of this second connectivity port, and this second wafer stacking is linked on this first wafer, and this first weldering crystal layer is connected corresponding to zone and this second wafer of the 3rd connectivity port, and make the 3rd wafer stacking be linked to this second wafer.
Description of drawings
Fig. 1 is a schematic side view, illustrates that one is packaged with the packaging part of a plurality of wafers at present;
Fig. 2 is a schematic side view, and a kind of one first preferred embodiment that is packaged with the packaging part of a plurality of wafers of the present invention is described;
Fig. 3 is a part of flow chart, and the leading portion process of encapsulation preparation packaging part as shown in Figure 2 is described;
Fig. 4 is a part of flow chart, and the back segment process that continuity is shown in Figure 3 is described;
Fig. 5 is a schematic side view, the present invention is described when the packaging part that encapsulates as shown in Figure 2, removes first and second weldering crystal layer part presumptive area of soft electrical connection substrate, in order to the soft electrical connection substrate that twists;
Fig. 6 is a schematic side view, after key diagram 5 removes first and second weldering crystal layer part presumptive area of soft electrical connection substrate, and the aspect that the soft electrical connection substrate that twists neatly piles up first, second and third wafer;
Fig. 7 is a schematic side view, and a kind of one second preferred embodiment that is packaged with the packaging part of a plurality of wafers of the present invention is described;
Fig. 8 is a schematic side view, the packaging part of aid illustration Fig. 7, the semi-finished product aspect before encapsulation is not finished.
Embodiment
The present invention is described in detail below in conjunction with drawings and Examples:
Before the present invention is described in detail, be noted that in the following description content similar elements is to represent with identical numbering.
Consult Fig. 2, a kind of one first preferred embodiment that is packaged with the packaging part of a plurality of wafers of the present invention is to finish so that method for packing as shown in Figures 3 and 4 is prepared, and can integrates the calculation function of each wafer, with the user demand in response to electronic product.
First, second and third wafer 22,23,24 is respectively an overlay crystal chip, be laid with a plurality of first electrical connector 221, second electrical connectors 231 that are used to conduct accordingly, and the 3rd electrical connector 241, these a little first, second and third electrical connectors 221,231,241 are the projection of title that industry is practised.
Soft electrical connection substrate 25 is to cooperate the macromolecule insulant to be pressed into the structure of individual layer or a plurality of layers with electric conducting material, and only establishing single layer of conductive material with two layers of insulants folder in this illustration mark is the example explanation.Soft electrical connection substrate 25 has one first weldering crystal layer 251, one the second weldering crystal layer 252 in contrast to the first weldering crystal layer 251, one is located in first, two weldering crystal layers 251, circuit layout 253 between 252, one is arranged at first connectivity port 254 on the first weldering crystal layer 251, one is arranged at second connectivity port 255 on the second weldering crystal layer 252, one is arranged on the second weldering crystal layer 252 and relative the 3rd connectivity port 256 away from second connectivity port 255, and a plurality of be laid in second the weldering crystal layer 252 on and be positioned at second, three connectivity ports 255, electric connection block 257 between 256, first, two weldering crystal layers 251,252 is that material forms with the macromolecule insulant all, circuit layout 253, first, two, three connectivity ports 254,255,256 is to form with electric conducting materials such as for example copper with a plurality of electric connection blocks 257, wins and make, two, three connectivity ports 254,255,256 form predetermined the electrical connection with circuit layout 253 respectively accordingly with a plurality of electric connection blocks 257.
It is cemented fixed and be electrically connected on first connectivity port 254 that first wafer 22 welds accordingly with a plurality of first electrical connectors 221, forms predetermined status of electrically connecting with circuit layout 253; It is cemented fixed and be electrically connected on second connectivity port 255 that second wafer 23 welds accordingly with a plurality of second electrical connectors 231, forms predetermined status of electrically connecting with circuit layout 253; It is cemented fixed and be electrically connected on the 3rd connectivity port 256 that the 3rd wafer 24 welds accordingly with a plurality of the 3rd electrical connectors 241, forms predetermined status of electrically connecting with circuit layout 252; And make first, second and third wafer 22,23,24 borrow the circuit layout ground electric work that corresponds to each other to integrate.
Soft electrical connection substrate 25 twists and makes the cross section become one " 6 " word aspect, and the first weldering crystal layer 251 is connected corresponding to the zone and first wafer, 22 surfaces of second link 255, is linked on first wafer 22 and second wafer 23 is piled up; The first weldering crystal layer 251 is connected corresponding to the zone and second wafer, 23 surfaces of the 3rd connectivity port 256 simultaneously, is linked on second wafer 23 and the 3rd wafer 24 is piled up.
Soft electrical connection substrate 25 is electrically connected accordingly with a plurality of electric connection blocks 251 and substrate 21 and is fixedly connected on substrate 21.
Packing colloid 27 upwards forms from substrate 21, is hedged off from the outer world with first, second and third wafer 22,23,24 with the soft substrate 25 that is electrically connected of substrate 21 common coatings.
A plurality of electrical ties things 28 are glomeration and neat compartment of terrain is laid in substrate 21 bottom surfaces respectively, the circuit board (scheming not shown) that makes substrate 21 be electrically connected a thing and an electronic product whereby a bit is electrically connected and is fixedly connected on circuit board, generally, the therefore a little outward appearance aspects that are electrically connected thing 28 of industry are practised with using material and are called " tin ball ".
Above-mentioned packaging part 2 is after the method for packing explanation that cooperates as shown in Figures 3 and 4, when can clearerly understanding.
Consult Fig. 3 and Fig. 4, the method for packing of encapsulation preparation packaging part as shown in Figure 2 is carry out step 31 earlier, and first, second and third wafer 22,23,24 corresponding to the need encapsulation is integrated prepares soft electrical connection substrate 25.
Then carry out step 32, respectively with first wafer 22, second wafer 23, and brilliant first connectivity port 254, second connectivity port 255 on soft electrical connection substrate 25 of the 3rd wafer 24 difference weldering accordingly, with the 3rd connectivity port 256, and make first, second and third wafer 22,23,24 borrow the circuit layout 253 of the soft electrical connection substrate 25 ground electric work that corresponds to each other to integrate.
Carry out step 33 then, filler 26 is coated with places first wafer 22, second wafer, 23 peripheries.
Carry out step 34 again, the soft electrical connection substrate 25 that twists earlier makes the first weldering crystal layer 251 be connected corresponding to the zone and first wafer, 22 surfaces of second connectivity port 255, is linked on first wafer 22 and second wafer 23 is piled up; Twist again another side of soft electrical connection substrate 25 makes the first weldering crystal layer 251 be connected corresponding to the zone and second wafer, 23 surfaces of the 3rd connectivity port 256, is linked on second wafer 23 and the 3rd wafer 24 is piled up.
Then carry out step 35,, be electrically connected and weld cemented due to substrate 21 surfaces with a plurality of electric connection block 257 correspondences with the prepared goods of finishing of step 34.
Carry out step 36 then, upwards irritate mould from substrate 21 surfaces and form packing colloid, make packing colloid and substrate will weld cemented each member on substrate surface jointly and coat and be isolated with the external world.
Carry out step 37 at last, plant a plurality of electrical connection things 28, use, promptly finish the main encapsulation process of above-mentioned packaging part 2 for the follow-up circuit board that is electrically connected at substrate 21 bottom surface cloth.
Consult Fig. 5, Fig. 6, what this will be illustrated especially be, carrying out step 34 when twisting soft electrical connection substrate 25, can be subject to soft electrical connection substrate 25 first, two weldering crystal layers 251, the characteristic of 252 materials, make and win, two, three wafers 22,23,242 pile up difficult, therefore, can be with first, two weldering crystal layers 251,252 carry out the follow-up subregion that twists corresponding to needs, with first of this zone, two weldering crystal layers 251,252 remove, as shown in Figure 5, or only remove the first weldering crystal layer 251 or the second weldering crystal layer 252, or part removes, by the ductility and the plasticity of the circuit layout 253 conducting metal materials of retaining, and the soft electric connection board 25 that can simple and easyly twist, make and win, two, three wafers 22,23,24 can be as shown in Figure 6 as, neatly and elasticity is not piled up the location with coming off each other again.
Certainly, the skill personage who is familiar with encapsulation all knows, generally in actual production, encapsulation process for example still includes outward appearance detection, testing electrical property, impresses, electroplates or the like implementation step, but because these a little steps are not emphasis of the present invention place, so do not add to give unnecessary details at this.
Consult Fig. 7, a kind of one second preferred embodiment that is packaged with the packaging part of a plurality of wafers of the present invention, be similar to above-mentioned packaging part 2, encapsulation process is also roughly identical, its packaging part 2 ' that only is this second preferred embodiment that do not exist together more comprises one the 4th wafer 4, cooperate and consult Fig. 8, and soft electrical connection substrate 25 more comprises the 4th connectivity port 5 that is arranged on the first weldering crystal layer 251, the 4th connectivity port 5 is more relative to 254 settings of first connectivity port to the 3rd connectivity port 256 directions with second connectivity port 255, and supply the 4th wafer 4 to weld brilliant the binding accordingly, win and make, two, three, four wafers 22,23,24 borrow the circuit layout 253 ground electric work that corresponds to each other to integrate.
Similar to precedent, soft electrical connection substrate 25 ' twists and makes its cross section become one " 6 " font, and after first, second and third wafer 22,23,24 piled up binding from bottom to top in regular turn, the side area of correspondence the 4th connectivity port 5 of soft electrical connection substrate 25 again twists, the second weldering crystal layer 252 is connected corresponding to the zone and the 3rd wafer 24 of the 4th connectivity port 5 of the first weldering crystal layer 251, and then the 4th wafer 4 is piled up be linked on the 3rd wafer 25.Because other each member details is roughly similar, forgives and not repeat in detail one by one.
Certainly, the method for packing of above-mentioned packaging part 2 ' also with first preferred embodiment in illustrated method for packing approximate, it does not exist together and only is the details of soft electrical connection substrate 25 preparations, and the soft electrical connection substrate 25 that twists is also given unnecessary details at this no longer one by one to pile up the process that links each wafer.
In addition, description according to creation spirit of the present invention and above-mentioned two preferred embodiments, be familiar with the function that this skill personage certainly looks actual required by electronic product simply, weld brilliant wafer number on soft electrical connection substrate 25 and adjust, wafer position, and change the stack manner of the mode that twists of soft electrical connection substrate 25 with this each wafer, and at packaging part 2, encapsulation in 2 ', integrate more wafer, make packaging part 2,2 ' brings into play more strong functions, because the variation of this kind space kenel is numerous, and it is required and fine setting changes to look the actual package processing procedure, so illustrate no longer one by one at this.
As shown in the above description, the present invention is packaged with the packaging part 2 of a plurality of wafers, 2 ' and method for packing, mainly be to use soft electrical connection substrate 25 to have low price, the design circuit layout is simple, advantage easily, corresponding in advance required encapsulation, wafer number and the function integrated, prepare soft electrical connection substrate 25 with most connectivity ports, again that the corresponding weldering of wafer is brilliant on each connectivity port of soft electrical connection substrate 25, again by soft electrical connection substrate 25 itself can circumnutate the bending characteristic, each wafer simply piled up connect to predetermined aspect, and then can directly weld and be connected in substrate 21, irritate mould and form packing colloid 27, cloth is planted processes such as being electrically connected thing 28 (tin ball) .., and a complete packaging part 2 is finished in encapsulation, 2 ', and then application is attached on the circuit board of electronic product; Or directly will use most wafers that soft electrical connection substrate piles up integration, use on the circuit board of borrowing soft electrical connection substrate to be attached at electronic product and use, with growth requirement in response to electronic product, and corresponding complicated and diversified calculation function is provided, can simplify simultaneously encapsulation procedure, reduce the procedure for producing cost, reach goal of the invention of the present invention really.
Claims (12)
1. packaging part that is packaged with a plurality of wafers is characterized in that the described packaging part that is packaged with a plurality of wafers comprises:
One first wafer;
One second wafer;
One the 3rd wafer;
The one soft electrical connection substrate that can twist has one first weldering crystal layer, and second a weldering crystal layer in contrast to this first weldering crystal layer;
This first wafer weldering is brilliant on this first weldering crystal layer, this is second years old, remotely weldering is brilliant on this second weldering crystal layer mutually respectively for three wafers, and make this first, two, three wafers borrow this soft electrical connection substrate correspond to each other electric work can integrate, and this soft electrical connection substrate twists, this first weldering crystal layer is connected corresponding to zone and this first wafer that this second weldering crystal layer is welded with this second wafer, and this second wafer stacking is linked on this first wafer, simultaneously, this first weldering crystal layer has the zone of the 3rd wafer and this second wafer to be connected corresponding to this second weldering crystal layer weldering crystalline substance, and the 3rd wafer stacking is linked on this second wafer.
2. be packaged with the packaging part of a plurality of wafers according to claim 1, it is characterized in that: this packaging part that is packaged with a plurality of wafers more comprises a substrate that can be electrically connected with a circuit board, and the second weldering crystal layer of this soft electrical connection substrate is electrically connected also fixedly connected on this substrate corresponding to the zone that this first weldering crystal layer is welded with this first wafer with this circuit board.
3. as being packaged with the packaging part of a plurality of wafers as described in the claim 2, it is characterized in that: this packaging part that is packaged with a plurality of wafers more comprises a plurality of electrical ties things that are laid under this substrate, and this substrate is borrowed these a plurality of electrical connection things and this circuit board to be electrically connected and be fixedly connected on this circuit board.
4. be packaged with the packaging part of a plurality of wafers according to claim 1, it is characterized in that: this packaging part that is packaged with a plurality of wafers more comprises one the 4th wafer, be to weld on the crystal layer in first of this soft electrical connection substrate to the more relative crystalline substance that welds away from this first wafer of the 3rd wafer orientation with this second wafer, borrow this soft electrical connection substrate and this first, two, three wafers correspond to each other ground electric work can integrate, and this soft electrical connection substrate twists and makes this second weldering crystal layer have the zone of the 4th wafer and the 3rd wafer to be connected corresponding to this first weldering crystal layer weldering crystalline substance, and the 4th wafer stacking is linked on the 3rd wafer.
5. be packaged with the packaging part of a plurality of wafers according to claim 1, it is characterized in that: this packaging part that is packaged with a plurality of wafers more comprises a filler with elasticity and insulation, be selectively to be coated with to place arbitrary wafer perimeter, make when this soft electrical connection substrate twists, to keep the smooth curved arcuation, to keep the internal electrical connection status of this soft electrical connection substrate.
6. as being packaged with the packaging part of a plurality of wafers as described in claim 1 or 4, it is characterized in that: this packaging part that is packaged with a plurality of wafers more comprises a packing colloid, coats this soft electrical connection substrate and all and softly is electrically connected the wafer of substrate electrical ties and is hedged off from the outer world with this.
7, a kind of method for packing with packaging part of a plurality of wafers is characterized in that:
This method for packing comprises:
Step 1: the preparation one soft electrical connection substrate that can twist, make have one first weldering crystal layer, second a weldering crystal layer, in contrast to this first weldering crystal layer is arranged at this first weldering, first connectivity port, on crystal layer and is arranged at second connectivity port on this second weldering crystal layer, and one is arranged on this second weldering crystal layer and relatively away from the 3rd connectivity port of this second connectivity port;
Step 2: respectively with one first wafer, one second wafer, and brilliant this first connectivity port, this second connectivity port on this soft electrical connection substrate of one the 3rd wafer difference weldering accordingly, with the 3rd connectivity port;
Step 3: this soft electrical connection substrate that twists makes this first weldering crystal layer be connected corresponding to zone and this first wafer of this second connectivity port, and this second wafer stacking is linked on this first wafer, and this first weldering crystal layer is connected corresponding to zone and this second wafer of the 3rd connectivity port, and make the 3rd wafer stacking be linked to this second wafer.
8. as having the method for packing of the packaging part of a plurality of wafers as described in the claim 7, it is characterized in that: this step 1 makes this soft electrical connection substrate more comprise the 4th connectivity port that is arranged on this first weldering crystal layer, and the 4th connectivity port is more relative to this first connectivity port setting to the 3rd connectivity port direction with this second connectivity port; This step 2 is more welded one the 4th wafer brilliant in the 4th connectivity port accordingly; And will this soft electrical connection substrate in the depth of the night of this step twisting makes this second weldering crystal layer be connected corresponding to the zone and the 3rd wafer of the 4th connectivity port, and the 4th wafer stacking is linked on the 3rd wafer.
9. as having the method for packing of the packaging part of a plurality of wafers as described in claim 7 or 8, it is characterized in that: this method for packing more comprises a step 4 of implementing before step 3, be to weld crystal layer at contiguous this first wafer perimeter and first of this soft electrical connection substrate respectively to join the zone mutually, and contiguous the 3rd wafer perimeter and second of this soft electrical connection substrate weld crystal layer and join the area side edge regions mutually, coating one has the filler of elasticity and insulation, make and carry out step 3 when twisting this soft electrical connection substrate, this filler hold fill in this first, three wafer sides and this soft electrical connection between the substrate keep this soft electrical connection substrate to become the smooth curved arcuation to keep corresponding status of electrically connecting.
10. as having the method for packing of the packaging part of a plurality of wafers as described in claim 7 or 8, it is characterized in that: this method for packing more comprises a step 5 of implementing after step 3, and being that goods that step 3 is finished are corresponding is electrically connected and welds cemented scheduling on the substrate.
11. as having the method for packing of the packaging part of a plurality of wafers as described in the claim 10, it is characterized in that: this method for packing more comprises a step 6 of implementing after step 5, be upwards to form a packing colloid, coat and be isolated with the external world and will weld all objects that stick on substrate jointly with this substrate from this substrate.
12. as having the method for packing of the packaging part of a plurality of wafers as described in the claim 11, it is characterized in that: this method for packing more comprises a step 7 of implementing after step 6, be the electrical ties thing of laying a plurality of and the corresponding electrical connection of this substrate from this substrate bottom surface, relative fixed is linked on this substrate to make this substrate borrow these a plurality of electrical connection things and a circuit board to be electrically connected also.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100809192A CN100347856C (en) | 2004-09-27 | 2004-09-27 | Package with multiple wafers and packaging method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100809192A CN100347856C (en) | 2004-09-27 | 2004-09-27 | Package with multiple wafers and packaging method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1755931A CN1755931A (en) | 2006-04-05 |
| CN100347856C true CN100347856C (en) | 2007-11-07 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100809192A Expired - Fee Related CN100347856C (en) | 2004-09-27 | 2004-09-27 | Package with multiple wafers and packaging method thereof |
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| Country | Link |
|---|---|
| CN (1) | CN100347856C (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1155760A (en) * | 1995-12-15 | 1997-07-30 | 国际商业机器公司 | Controlled profile multiple chip modules |
| CN1239831A (en) * | 1998-06-24 | 1999-12-29 | 日本电气株式会社 | Semiconductor device and method for fabricating the same |
| JP2002237568A (en) * | 2000-12-28 | 2002-08-23 | Texas Instr Inc <Ti> | Chip-scale package stacked on interconnect body folded for vertical assembly on substrate |
| US20020164838A1 (en) * | 2001-05-02 | 2002-11-07 | Moon Ow Chee | Flexible ball grid array chip scale packages and methods of fabrication |
| US6686655B2 (en) * | 1998-08-21 | 2004-02-03 | Micron Technology, Inc. | Low profile multi-IC chip package connector |
-
2004
- 2004-09-27 CN CNB2004100809192A patent/CN100347856C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1155760A (en) * | 1995-12-15 | 1997-07-30 | 国际商业机器公司 | Controlled profile multiple chip modules |
| CN1239831A (en) * | 1998-06-24 | 1999-12-29 | 日本电气株式会社 | Semiconductor device and method for fabricating the same |
| US6686655B2 (en) * | 1998-08-21 | 2004-02-03 | Micron Technology, Inc. | Low profile multi-IC chip package connector |
| JP2002237568A (en) * | 2000-12-28 | 2002-08-23 | Texas Instr Inc <Ti> | Chip-scale package stacked on interconnect body folded for vertical assembly on substrate |
| US20020164838A1 (en) * | 2001-05-02 | 2002-11-07 | Moon Ow Chee | Flexible ball grid array chip scale packages and methods of fabrication |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1755931A (en) | 2006-04-05 |
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