CN100346485C - 象限光电探测器象限分离的制造方法 - Google Patents

象限光电探测器象限分离的制造方法 Download PDF

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CN100346485C
CN100346485C CNB021280282A CN02128028A CN100346485C CN 100346485 C CN100346485 C CN 100346485C CN B021280282 A CNB021280282 A CN B021280282A CN 02128028 A CN02128028 A CN 02128028A CN 100346485 C CN100346485 C CN 100346485C
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朱华海
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Abstract

本发明公开了一种硅象限光电探测器象限分离的制作方法，用于硅象限光电探测器象限间隔离区的制作，其特征是：在硅象限光电探测器pn结衬底背面高低结电极接触区域上，采用半导体器件制造工艺，制作所需图形实现象限分离。采用的半导体器件制造工艺是：用光刻法，将高低结的n+层或p+层刻蚀沟槽分区(如图A所示)；也可以是掩模分区选择扩散或离子注入制作n+层或p+层；还可以是掩模分区选择Ar+离子或N+离子轰击将n+层或p+层隔离分区等工艺。本发明提供的象限分离制作方法可用于四象限、八象限(双四象限)等象限光电探测器及多元线列、阵列光电探测器等的象限间、象元间的分离。与现有的硅象限光电探测器相比，在同等的光敏面积下，其光敏面边界总长度大大减小，器件漏电流小、噪声低、探测灵敏度大为提高，探测器的均匀性、一致性好，成品率、优品率显著提高。

Description

象限光电探测器象限分离的制造方法
技术领域    本发明涉及一种硅象限光电探测器象限分离的制作方法，用于硅象限光电探测器象限间隔离区的制作。
背景技术    半导体硅象限光电探测器，无论是用高阻p型或n型硅单晶材料来制作象限(或阵列)硅PIN光电二极管(Si-PIN-PD)，还是用高阻p型硅单晶材料来制作象限硅拉通型雪崩光电二极管(Si-RAPD)等类型硅象限光电探测器时，都是在象限光电探测器芯片的正面采用pn结隔离来进行象限分离。这样，象限光电探测器总的光敏面面积及其光敏面边界总长度是以象限光敏元数和每个光敏元面积之和及其光敏面边界长度之和来计算的。于是，光敏面积越大，象限数越多，象限光电探测器主要性能就难保证；再有，象限数越多，光敏面边界总长度也就越大，其探测器边缘击穿的几率就越多，探测器的表面漏电流就越大(探测器表面漏电流的主要部份与探测器边界长度成比例)；漏电流增大，导致探测器噪声增加，从而将降低探测器的探测灵敏度。
发明内容    本发明的目的是：针对现有硅象限光电探测器在光敏面采用pn结隔离进行象限分离制作方法的不足之处，提供一种硅象限光电探测器象限分离的制作新方法，用于硅象限光电探测器象限间(象元间)隔离区的制作，减小象限光电探测器光敏面边界总长度，减小器件漏电流，降低噪声，提高探测灵敏度及探测器均匀性一致性。其特征是：在探测器芯片pn结衬底背面高低结的电极接触区域上采用半导体器件制造工艺，制作所需的“四象限”形、“八象限”形、“线列”形和“阵列”形等多象限图形以实现象限分离。采用的半导体器件制造工艺是：用光刻刻蚀工艺，将n+层或p+层刻蚀沟槽分区，沟槽深度大于n+层或p+层厚度(即高低结深度)；也可以是用与衬底同型杂质的高浓度掩膜分区选择热扩散或分区离子注入制作n+层或p+层；还可以是掩膜分区选择Ar+离子或N+离子进行轰击，其轰击的深度大于高低结深度，此轰击区构成隔离区。具体技术方案如下：用n型或p型高阻硅单晶材料作衬底制作Si-PIN-PD(硅PIN光电二极管)象限光电探测器，或者用p型高阻硅单晶材料作衬底制作Si-RAPD(硅拉通型雪崩光电二极管)象限光电探测器时，在硅单晶衬底的正面制作pn结后，在pn结衬底背面研磨减薄抛光后，对n型Si进行高磷扩散，对p型Si进行高硼扩散，而后，用光刻方法对上述的高磷扩散层(n+)或高硼扩散层(p+)刻蚀沟槽制作隔离区，刻蚀的沟槽深度应超过n+层或p+层的厚度(即高低结的结深度)。其后按常规工艺完成芯片金属化，倒扣封装即成。用本发明提供的象限分离方法制作的硅象限光电探测器与现有的硅象限光电探测器相比，在同等的光敏面积下，其光敏面边界的总长度大大减小，从而漏电亦为减小，噪声大为降低，探测灵敏度大为提高，边缘击穿几率降低，探测器的均匀性、一致性好，成品率显著提高。
附图说明    附图1是本发明用光刻方法刻蚀沟槽实现象限分离的四象限硅光电探测器管芯芯片示意图。图中A是管芯芯片的侧视图，[n]是本征硅(n-si)衬底；[p+]是硼扩散层(p+-Si)；[n+]是磷扩散层(n+-Si)沟槽刻蚀层；B为管芯芯片的顶视图。
附图2是本发明用光刻法刻蚀沟槽制作四象限硅光电探测器象限分离的工艺流程示意图。
图中[1]、[4]是SiO2层；[2]是本征硅(n-si)衬底层；[3]是硼扩散(p+-Si)层；[5]是磷扩散(n+-Si)层；[6]是刻蚀的沟槽；[7]是Si3N4层；[8]是电极窗口；[9]是金属电极。
具体实施方式    下面结合附图2介绍本发明的一个实施例，该实施例是用光刻法刻蚀沟槽实现四象限硅光电探测器象限分离的制作过程。
1、在n型(n-Si)衬底[2]上生长SiO2层[1]，并光刻硼扩散窗口，如图中(a)所示；
2、通过扩散窗口进行硼扩散，形成p+-Si层[3]，并在[3]上生长SiO2层[4]，如图中(b)所示；
3、对n-Si衬底[2]背面进行研磨抛光、然后进行磷扩散，扩散层深为1-2μm，形成n+-Si层[5]，如图中(c)所示；
4、在n+-Si层[5]，用光刻法刻蚀沟槽[6]，其沟槽深度大于高低结深度，如图中(d)所示；
5、在n+-Si层[5]上及沟槽[6]中生长增透膜Si3N4层[7]，如图中(e)所示；
6、光刻Si3N4层[7]和SiO2[4]，形成电极蒸发窗口[8]，如图中(f)所示；
7、在电极蒸发窗口[8]上，用真空镀膜方法，分别蒸发铝(Al)，刻蚀形成电极接触层[9]，如图中(g)所示，制作完成。
另外：①将步骤4改为：在n+-Si层[5]刻蚀沟槽[6]以外的位置，采用掩模分区按象限图形选择热扩散或离子注入实现掺杂构成高低结；②将步骤4改为：在n+-Si层[5]刻蚀沟槽[6]的位置，采用掩模分区进行Ar+离子或N+离子轰击，离子轰击深度大于高低结深度。其余步骤同以上各步骤，前者①就是用热扩散法和用离子注入法掺杂实现分离象限的实施例，后者②就是用离子轰击，实现隔离以分离象限的实施例。
以上方法也可用于八象限(双四象限)线列、阵列等多象限光电探测器象限分离的制作。

Claims (4)

1、一种硅象限光电探测器象限分离的制造方法，不用通常在探测器芯片正面的pn结隔离来实现象限的分离，而是在探测器芯片pn结衬底的背面高低结的电极区域上制作“四象限”形、“八象限”形、“线列”形、“阵列”形多象限图形来实现象限的分离。
2、根据权利要求1所述的硅象限光电探测器象限分离的制作方法，在硅象限光电探测器芯片pn结衬底背面的高低结电极接触区域上按象限图形要求，用光刻法刻蚀沟槽形成隔离区，沟槽深度大于高低结深度，以实现象限分离。
3、根据权利要求1所述的硅象限光电探测器象限分离的制作方法，在硅象限光电探测器芯片pn结衬底背面，用与衬底同型杂质按象限图形进行掩膜分区高浓度扩散或离子注入掺杂形成高低结，而未掺杂的区域则构成隔离区，以此实现象限的分离。
4、根据权利要求1所述的硅象限光电探测器象限分离的制作方法，在硅象限光电探测器芯片pn结衬底背面高低结的电极区域上按象限图形进行掩膜分区，用Ar+离子或N+离子轰击，离子轰击的深度大于高低结深度，被轰击的区域构成隔离区以实现象限的分离。
CNB021280282A 2002-12-16 2002-12-16 象限光电探测器象限分离的制造方法 Expired - Fee Related CN100346485C (zh)

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CN105977337B (zh) * 2016-07-18 2017-08-25 苏州北鹏光电科技有限公司 低暗电流高速pin探测器及其加工方法
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CN109427923B (zh) * 2017-08-25 2020-06-16 中国科学院大连化学物理研究所 一种半导体薄膜四象限光照传感器及其制备方法
CN109946676B (zh) * 2017-12-21 2024-01-23 中国科学院沈阳自动化研究所 应用十二象限激光探测器计算光斑中心位置偏移量的方法
CN111106201A (zh) * 2019-12-09 2020-05-05 中国电子科技集团公司第四十四研究所 一种新型结构的apd四象限探测器及其制备方法
CN112054075B (zh) * 2020-07-31 2023-01-06 重庆鹰谷光电股份有限公司 一种超高精度的硅象限光电探测器

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