CN100343972C - Method for forming shallow-channel isolation region - Google Patents
Method for forming shallow-channel isolation region Download PDFInfo
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- CN100343972C CN100343972C CNB021458278A CN02145827A CN100343972C CN 100343972 C CN100343972 C CN 100343972C CN B021458278 A CNB021458278 A CN B021458278A CN 02145827 A CN02145827 A CN 02145827A CN 100343972 C CN100343972 C CN 100343972C
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- dielectric layer
- isolation regions
- trench isolation
- shallow trench
- raceway groove
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Abstract
The present invention relates to a method for forming shallow trench isolation regions, which comprises the following steps: a semiconductor substrate is provided; a mask layer is formed on the semiconductor substrate; the shape of the mask layer is defined by a photolithography process and an etching program; the etching program is performed by using the shape of the mask layer to form a plurality of trenches on the semiconductor substrate; a sidewall spacing layer is formed in the trenches; a high density electric slurry chemical vapor deposition program is performed, and a first dielectric layer is deposited on the semiconductor substrate; the first dielectric layer is filled into the trenches; a depletion layer is deposited on the semiconductor substrate; the depletion layer is filled into the trenches grooves and is positioned on the first dielectric layer; the depletion layer and the first dielectric layer on the surfaces of the trenches are removed in a wet etching mode; the depletion layer which is positioned in the trenches is removed; a second dielectric layer is deposited on the semiconductor substrate; the trenches are filled with the second dielectric layer; a flatting process is performed to remove the second dielectric layer on the surfaces of the trenches to complete the manufacture of shallow-channel isolation regions.
Description
Technical field
The present invention relates to the manufacturing of semiconductor integrated circuit, and be particularly related to the manufacture process that a kind of Improvement type high density plasma enhanced chemical vapor deposition technology forms shallow trench isolation regions (shallow trench isolation), insert the effect of raceway groove to improve dielectric layer.
Background technology
In recent years, along with the development of semiconductor integrated circuit manufacturing technology, the quantity of contained element constantly increases in the chip, and size of component is also constantly dwindled because of the lifting of integrated level, and the line width that uses on the production line has entered the tiny scope of inferior micron.Yet no matter how downsizing of component size still must have suitably insulation or isolates between each element in chip, can obtain good component properties.The technology of this respect is commonly referred to as element separation technology (device isolation technology), its main purpose is to form spacer between each element, and guaranteeing under the situation of good isolation effect, dwindle the zone of spacer as far as possible, hold more element to vacate more chip area.
In various element separation technology, localized oxidation of silicon method (LOCOOS) and shallow trench isolation regions (shallow trench isolation) manufacture process is the most normal adopted two kinds of technology, especially the latter have area of isolation little and finish after still keep advantage such as substrate flatness, quite valued recently especially semiconductor fabrication.Be to utilize the chemical vapor deposition (CVD) program earlier traditionally, form a dielectric layer with in the raceway groove of inserting substrate, etch-back (etch back) or remove the unnecessary dielectric layer in surface with chemical mechanical lapping program (CMP) more afterwards is to finish the trench isolation regions manufacture process.But along with integrated circuit density improves constantly and development that component size is day by day dwindled, there is the problem of covering power in above-mentioned deposition technique, and is difficult for dielectric layer is filled up raceway groove fully, causes the isolation effect of element to be affected.
For improving the problems referred to above, a kind of high density plasma enhanced chemical vapor deposition (HDPCVD) technology is suggested, and it is mainly with oxygen (O
2) and silicomethane (SiH
4) be used as reactant and come dielectric layer, reach and improve the effect that dielectric layer is inserted raceway groove.In order further to clearly demonstrate the content of this technology, below promptly with reference to Figure 1A to 1C, its manufacturing process is described.
At first, see also Figure 1A, in semiconductor substrate 10, form a mask layer, for example be on a silicon wafer surface, change into regular way with chemical vapour deposition technique (CVD) or hot gas and form the cushion steam layer (pad oxide layer) 12 of a thickness between 50 and 200 , on pad oxide 12 surfaces, deposit the silicon nitride layer 14 of a thickness between 500 and 2000 with the CVD method then, the two constitutes mask layer jointly.Then,, define the pattern of silicon nitride layer 14 and pad oxide 12, in order to expose the part that desire of the semiconductor-based ends 10 forms element isolation zone with little shadow imaging (photolithography) and etching program.
Secondly, see also figure B, utilize the pattern of silicon nitride layer 14 and cushion steam layer 12 to be used as mask, implement an etching program and form raceway groove 15 on the semiconductor-based end 10, its degree of depth is between 3500 and 5000 .Then, with thermal oxidation program (thermal oxidation) growth one thin gasification layer 16, cover on the bottom and sidewall of raceway groove 15, in order to be used as lining (liner), its thickness is about 180 .
Then, implement high density plasma enhanced chemical vapor deposition (HDPCVD) program, for example use O
2And SiH
4Be used as reactant, impose Ar electricity slurry simultaneously and splash and deposit a dielectric layer 18, fill up raceway groove 15, obtain the structure shown in Fig. 1 C to form an element isolated area.
But because the ditch ability of filling out of high density plasma enhanced chemical vapor deposition (HDPCVD) only is suitable for the raceway groove of depth-to-width ratio (aspect ratio) less than 4, otherwise, as shown in Figure 2, when the depth-to-width ratio of raceway groove is excessive, cause raceway groove 15 tops to seal ahead of time, but the effect that not exclusively has influence on isolation is filled in the raceway groove 15 inner cavities (void) that produce.
Summary of the invention
One object of the present invention is to provide a kind of Improvement type semiconductor element to isolate manufacture process, and it can improve the ability that dielectric layer is inserted raceway groove, the quality of lift elements.
Another object of the present invention is to provide a kind of with boron-phosphorosilicate glass (BPSG) material as depletion layer, HPCVD is filled the step of raceway groove, be divided into for two stages to implement, help to reduce the depth-to-width ratio of raceway groove, auxiliary HDPCVD ditch is filled out ability, avoids producing the method in cavity (void).
For reaching above-mentioned purpose, the shallow trench isolation regions formation method that the invention provides comprises the following steps at least, one has the semiconductor-based end of mask layer, type sample with mask layer defines the part of substrate shallow trench isolation regions and etches raceway groove, and form laying at the raceway groove inwall, and remove the laying part on this trench bottom surface by reactive ion etching, to form a side wall spacer layer, wherein, this side wall spacer layer is an insulating barrier, implement a high density plasma enhanced chemical vapor deposition (HDPCVD) program, deposit one first dielectric layer on the semiconductor-based end, first dielectric layer is inserted raceway groove inside; Deposit a depletion layer on the semiconductor-based end, and depletion layer to be filled in raceway groove inner and be positioned on first dielectric layer; The depletion layer of planarization channel surface and first dielectric layer; Remove this depletion layer fully; Implement a high density plasma enhanced chemical vapor deposition (RDPCVD) program, deposit one second dielectric layer on the semiconductor-based end and this first dielectric layer, second dielectric layer is filled up this raceway groove; Impose a planarization process, remove this raceway groove second dielectric layer in addition, and finish the manufacture process of shallow trench isolation regions.
The present invention also provides a kind of shallow trench isolation regions formation method, and it comprises the following steps: to provide the semiconductor substrate; Form a mask layer on this semiconductor-based end; Define the type sample of this mask layer, in order to expose the part that this desire of semiconductor-based end forms shallow trench isolation regions; Utilize the type sample of this mask layer to be used as mask, implement an etching program, and on this semiconductor-based end, form a raceway groove; Form a laying in this raceway groove, and remove the laying part on this trench bottom surface by reactive ion etching, to form a side wall spacer layer, wherein, this side wall spacer layer is an insulating barrier; Implement a high density plasma enhanced chemical fluorine and deposit program mutually, deposit one first dielectric layer on this semiconductor-based end, this first dielectric layer is inserted this raceway groove inside; The deposition boron-phosphorosilicate glass on this semiconductor-based end, and this boron-phosphorosilicate glass to be filled in this raceway groove inner and be positioned on this first dielectric layer; Carry out the heat flow program, make this boron-phosphorosilicate glass planarization and insert this raceway groove interior void; The boron-phosphorosilicate glass of this channel surface of planarization and first dielectric layer; Remove this boron-phosphorosilicate glass fully; Implement a high density plasma enhanced chemical vapor deposition program, deposit one second dielectric layer on this semiconductor-based end and this first dielectric layer, this second dielectric layer is filled up this raceway groove; Impose a cmp program, remove this raceway groove second dielectric layer in addition, and finish the manufacture process of shallow trench isolation regions.
Particularly,, provide the semiconductor-based end with mask layer, define the part of substrate shallow trench isolation regions and etch raceway groove with the type sample of mask layer, and form laying in trench sidewalls according to preferred embodiment of the present invention; Insert in raceway groove in the dielectric layer step, deposit the dielectric layer of certain depth earlier with HDPCVD, but raceway groove is not filled up as yet, and keep the opening of raceway groove, aumospheric pressure cvd (SACVD) is inserted the BPSG material as depletion layer in proper order again; Though this moment, raceway groove sealed, the part of inner BPSG deposition still has the cavity, and solid this must carry out a heat flow (flow) effect again, makes the increase of BPSG flatness, and can fill and last time deposited the part that fashion is not filled up; Utilize the wet etching mode to remove unnecessary dielectric layer and BPSG again; because the etching selectivity of dielectric layer material and BPSG; can stay the dielectric layer that part BPSG protects trench bottom last time to deposit with HDPCVD in raceway groove; utilize hydrofluoric acid vapor (VHF) to remove BPSG again; this moment raceway groove depth-to-width ratio oneself more at the beginning for reducing; just can be once more with the RDPCVD dielectric layer to filling up raceway groove, carry out cmp (CMP) planarization at last again, can finish the shallow trench isolation regions manufacture process.
According to the present invention, because of BPSG itself also has dielectric property, thus can not need BPSG is removed fully with VHF again, and in directly carrying out the HDPCVD dielectric layer again and BPSG being coated on, also can be used as shallow trench isolation regions.
By method of the present invention, applicable to the filling of the bigger shallow trench isolation regions of depth-to-width ratio, and utilize split-level and BPSG as depletion layer, reduce the depth-to-width ratio of shallow channel, fill out the deficiency place of ability with auxiliary HDPCVD ditch.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. elaborates.
Description of drawings
Figure 1A to 1C is profile, illustrates the manufacturing process that forms shallow trench isolation regions with existing high density plasma enhanced chemical vapor deposition technology;
Fig. 2 shows that existing HDPCVD is applied to the high-aspect-ratio raceway groove, and ditch is filled out incomplete schematic diagram;
Fig. 3-12 shows an embodiment generalized section of shallow trench isolation regions formation method of the present invention;
Figure 13 shows the shallow trench isolation regions schematic diagram that another embodiment of the present invention forms.
Embodiment
See also Fig. 3-12, the generalized section of shallow trench isolation regions formation method one embodiment of the present invention is described, shallow trench isolation regions formation method of the present invention is common at semiconductor-based the end 10, for example a silicon wafer.
Please refer to Fig. 3, it shows the initial step of present embodiment.At first, form a mask layer 20 in semiconductor substrate 10, mask layer 20 preferable thickness are 200-3500 , and it can be the stacked structure of single layer structure or several layers.As shown in FIG., mask layer 20 preferably is made up of the thicker silicon nitride layer 24 of one deck pad oxide 22 and one deck.Cushion steam layer 22 available heat oxidizing process form, or (10w pressure chemical vapor deposition, LPCVD) deposition forms with existing normal pressure (atmospheric) or Low Pressure Chemical Vapor Deposition.Silicon nitride layer 24 on cushion steam layer 22 can utilize Low Pressure Chemical Vapor Deposition (LPCVD), with dichlorosilane (SiCl
2H
2) and ammonia (NH
3) form for reaction raw materials deposits.Then, cover the zone that follow-up desire forms active member with a photo-resistive mask (not expressing among the figure), silicon nitride layer 24 and pad oxide 22 are carried out universe etching, and along etching outline continuation etching substrate 10 to one desired depths, can be 5500-6500 , to form several shallow channel 30 (representing with a shallow channel in the diagram).
After etching finishes, as shown in Figure 4, with photoresistance pattern (not expressing among the figure) from substrate 10 surface removals, madial wall at raceway groove 30 forms a cushion oxide layer then, at first can LPCVD or PECVD at the insulating barrier of the 850-850 ℃ of about 200-2000 of deposit one layer thickness, for example silica or silicon nitride; Again, if make combined type (composite) laying (liner), then can deposit the above insulating barrier of one deck, promptly be to adopt the composite type lining layer in the present embodiment, form silica and deposit a silicon nitride layer with the madial wall of thermal oxidation method earlier in sidewall at raceway groove 30, after deposition finishes, use SF
6, CF
4, CHF
3, or C
2F
6Be used as the etching source, carry out the etching of anisotropic, just can form insulation liner layer 32 with the reactive ion etching program.
Next, as shown in Figure 5, insert in the raceway groove 30 with high-density electric slurry sedimentation chemical vapour deposition (CVD) (HDPCVD) dielectric layer 42.This moment is because the deposition characteristics of high-density electric slurry sedimentation chemical vapour deposition (CVD) own, cause the also raising fast of dielectric layer 42 of raceway groove 30 outer surfaces, promptly sealed for avoiding causing dielectric layer 42 not fill up raceway groove 30 as yet, spray chemical etching (spray chemical etching) manufacture process so need impose one, being about to the dielectric layer 42 of raceway groove 30 outsides earlier removes partly, as shown in Figure 6.
Next repeat once as Fig. 5,6 described steps, the result increases dielectric layer 42 thickness as shown in Figure 7, and wherein dielectric layer 42 can be a gasification silicon, and each HDPCVD manufacture process can use 0
2And SiH
4Be used as reactant, impose simultaneously that Ar electricity slurry splashes and the silica that deposits about 2000-3000 .
At this moment, at become because of the relation of HDPCVD both thick of the dielectric layer 42 of raceway groove 30 outsides and make before next the deposition program is difficult to go deep into raceway groove inside, deposition one depletion layer 44 is in substrate earlier, as shown in Figure 8) wherein depletion layer 44 can be the boron-phosphorosilicate glass (BPSG) that utilizes aumospheric pressure cvd (APCVD), because in raceway groove 30, inserted dielectric layer 42 before, depletion layer 44 reduces the depth-to-width ratio of raceway groove 30, so can fill up raceway groove 30 smoothly; If use BPSG, more can utilize heat flow (flow) mode to make its planarization and fully insert the cavity that may exist (void) in the raceway groove 30 as depletion layer 44 materials.
Next, as shown in Figure 9, utilize the wet etching mode to remove the depletion layer 44 and the dielectric layer 42 of raceway groove 30 outsides, stay part depletion layer 44 in the raceway groove 30 to protect the dielectric layer 42 of its bottom; For example, in the present embodiment, dielectric layer 42 is a silica, and depletion layer 44 is BPSG, then utilizes etching selectivity, stays the silica of the BPSG of raceway groove 30 inside with protection lower floor.
Again as shown in figure 10, remove whole depletion layers 44, for example in the present embodiment, depletion layer 44 is removed for BPSG then can use hydrofluoric acid vapor (VHF).
At last, as shown in figure 12, impose a planarization process, remove the unnecessary dielectric layer 42 ' in raceway groove 30 outsides, finish this shallow trench isolation regions manufacture process, wherein, this planarization process can be used etch-back (etchback) or chemical mechanical milling method (chemical mechanical polishing; CMP) remove.
According to said process, can be common to depth-to-width ratio and fill in the HDPCVD mode, but, get final product effectively filling up raceway groove if the depth-to-width ratio of raceway groove less than 6, also can reduce the number of times of HDPCVD program according to circumstances greater than the raceway groove more than 6.
And in another embodiment of the present invention, also can not need depletion layer to be removed fully as the step of Figure 10, if with BPSG as depletion layer 44 materials, because of itself also has dielectric property, so can not need remove and the dielectric layer inserted once more afterwards 42 ' coats, as the part of dielectric layer, its shallow trench isolation regions of finishing as shown in figure 13, can thereby omit the step that removes depletion layer 44, next HDPCVD deposition program also can be simplified simultaneously.
Though the present invention is open with preferred embodiment; right its is not in order to qualification the present invention, any those of ordinary skill in the art, without departing from the spirit and scope of the present invention; can do some equivalence and change and modification, so protection scope of the present invention is as the criterion with claim.
Claims (19)
1. a shallow trench isolation regions formation method is characterized in that it comprises the following steps:
(a) provide the semiconductor substrate;
(b) form a mask layer on this semiconductor-based end;
(c) define the type sample of this mask layer, in order to expose the part that this desire of semiconductor-based end forms shallow trench isolation regions;
(c) utilize the type sample of this mask layer to be used as mask, implement an etching program, and on this semiconductor-based end, form a raceway groove;
(e) form a laying at this raceway groove inwall, and remove the laying part on this trench bottom surface by reactive ion etching, to form a side wall spacer layer, wherein, this side wall spacer layer is an insulating barrier;
(f) implement a high density plasma enhanced chemical vapor deposition program, deposit one first dielectric layer on this semiconductor-based end, this first dielectric layer is inserted this raceway groove inside;
(g) deposition one depletion layer is on this semiconductor-based end, and this depletion layer to be filled in this raceway groove inner and be positioned on this first dielectric layer;
(h) depletion layer of this channel surface of planarization and first dielectric layer;
(i) remove this depletion layer fully;
(j) implement a high density plasma enhanced chemical vapor deposition program, deposit one second dielectric layer on this semiconductor-based end and this first dielectric layer, this second dielectric layer is filled up this raceway groove;
(k) impose a planarization process, remove this raceway groove second dielectric layer in addition, and finish the manufacture process of shallow trench isolation regions.
2. shallow trench isolation regions formation method as claimed in claim 1 is characterized in that described mask comprises silica or silicon nitride.
3. shallow trench isolation regions formation method as claimed in claim 1 is characterized in that described side wall spacer layer comprises silica or silicon nitride.
4. shallow trench isolation regions formation method as claimed in claim 1 is characterized in that described first dielectric layer is a silica.
5. shallow trench isolation regions formation method as claimed in claim 1 is characterized in that described depletion layer is a boron-phosphorosilicate glass.
6. shallow trench isolation regions formation method as claimed in claim 5 is characterized in that described boron-phosphorosilicate glass silicon after deposition, carries out the heat flow program again, with planarization and fill up cavity in this raceway groove.
7. shallow trench isolation regions formation method as claimed in claim 5 is characterized in that described boron-phosphorosilicate glass removes with the hydrofluoric acid vapor etching.
8. shallow trench isolation regions formation method as claimed in claim 1, the depth bounds that it is characterized in that described raceway groove is 5500-6500 .
9. shallow trench isolation regions formation method as claimed in claim 1 is characterized in that described second dielectric layer is a silica.
10. shallow trench isolation regions formation method as claimed in claim 1 is characterized in that described planarization process is cmp or etch-back program.
11. shallow trench isolation regions formation method as claimed in claim 1 is characterized in that, behind high density plasma enhanced chemical vapor deposition, comprises that also one sprays the chemical etching program, to remove the partly aforementioned dielectric layer of raceway groove outside.
12. a shallow trench isolation regions formation method is characterized in that it comprises the following steps:
(a) provide the semiconductor substrate;
(b) form a mask layer on this semiconductor-based end;
(c) define the type sample of this mask layer, in order to expose the part that this desire of semiconductor-based end forms shallow trench isolation regions;
(d) utilize the type sample of this mask layer to be used as mask, implement an etching program, and on this semiconductor-based end, form a raceway groove;
(e) form a laying in this raceway groove, and remove the laying part on this trench bottom surface by reactive ion etching, to form a side wall spacer layer, wherein, this side wall spacer layer is an insulating barrier;
(f) implement a high density plasma enhanced chemical vapor deposition program, deposit one first dielectric layer on this semiconductor-based end, this first dielectric layer is inserted this raceway groove inside;
(g) the deposition boron-phosphorosilicate glass is on this semiconductor-based end, and this boron-phosphorosilicate glass to be filled in this raceway groove inner and be positioned on this first dielectric layer;
(h) carry out the heat flow program, make this boron-phosphorosilicate glass planarization and insert this raceway groove interior void;
(i) boron-phosphorosilicate glass of this channel surface of planarization and first dielectric layer;
(j) remove this boron-phosphorosilicate glass fully;
(k) implement a high density plasma enhanced chemical vapor deposition program, deposit one second dielectric layer on this semiconductor-based end and this first dielectric layer, this second dielectric layer is filled up this raceway groove;
(l) impose a cmp program, remove this raceway groove second dielectric layer in addition, and finish the manufacture process of shallow trench isolation regions.
13. shallow trench isolation regions formation method as claimed in claim 12 is characterized in that described mask comprises silica or silicon nitride.
14. shallow trench isolation regions formation method as claimed in claim 12 is characterized in that described side wall spacer layer comprises silica or silicon nitride.
15. shallow trench isolation regions formation method as claimed in claim 12 is characterized in that described first dielectric layer is a silica.
16. shallow trench isolation regions formation method as claimed in claim 12 is characterized in that described boron-phosphorosilicate glass removes with the hydrofluoric acid vapor etching.
17. shallow trench isolation regions formation method as claimed in claim 12, the depth bounds that it is characterized in that described raceway groove is 5500-6500 .
18. shallow trench isolation regions formation method as claimed in claim 12 is characterized in that described second dielectric layer is a silica.
19. shallow trench isolation regions formation method as claimed in claim 12 is characterized in that, behind high density plasma enhanced chemical vapor deposition, comprises that also one sprays the chemical etching program, to remove the partly aforementioned dielectric layer of raceway groove outside.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021458278A CN100343972C (en) | 2002-10-14 | 2002-10-14 | Method for forming shallow-channel isolation region |
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|---|---|---|---|
| CNB021458278A CN100343972C (en) | 2002-10-14 | 2002-10-14 | Method for forming shallow-channel isolation region |
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| CN1490866A CN1490866A (en) | 2004-04-21 |
| CN100343972C true CN100343972C (en) | 2007-10-17 |
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| CNB021458278A Expired - Lifetime CN100343972C (en) | 2002-10-14 | 2002-10-14 | Method for forming shallow-channel isolation region |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100745987B1 (en) * | 2005-08-09 | 2007-08-06 | 삼성전자주식회사 | Fabrication method of trench isolation of semiconductor device |
| CN101330035B (en) * | 2007-06-18 | 2010-05-19 | 中芯国际集成电路制造(上海)有限公司 | Isolation structure of shallow plough groove and manufacturing method thereof |
| CN104062045B (en) * | 2014-06-13 | 2017-09-15 | 江苏英特神斯科技有限公司 | A kind of piezoresistive pressure sensor and its manufacture method |
| CN114583013A (en) * | 2022-03-10 | 2022-06-03 | 常州时创能源股份有限公司 | BSG removing method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0846024A (en) * | 1994-07-26 | 1996-02-16 | Toshiba Microelectron Corp | Manufacture of semiconductor device |
| JPH09252049A (en) * | 1996-03-15 | 1997-09-22 | Mitsubishi Electric Corp | Multilayer embedded trench isolation |
| US6146974A (en) * | 1999-07-01 | 2000-11-14 | United Microelectronics Corp. | Method of fabricating shallow trench isolation (STI) |
| US6150238A (en) * | 1999-03-04 | 2000-11-21 | Mosel Vitelic, Inc. | Method for fabricating a trench isolation |
-
2002
- 2002-10-14 CN CNB021458278A patent/CN100343972C/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0846024A (en) * | 1994-07-26 | 1996-02-16 | Toshiba Microelectron Corp | Manufacture of semiconductor device |
| JPH09252049A (en) * | 1996-03-15 | 1997-09-22 | Mitsubishi Electric Corp | Multilayer embedded trench isolation |
| US6150238A (en) * | 1999-03-04 | 2000-11-21 | Mosel Vitelic, Inc. | Method for fabricating a trench isolation |
| US6146974A (en) * | 1999-07-01 | 2000-11-14 | United Microelectronics Corp. | Method of fabricating shallow trench isolation (STI) |
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