CN100334721C - Shrinkage controllable leadframe and flip chip type semiconductor package having same - Google Patents
Shrinkage controllable leadframe and flip chip type semiconductor package having same Download PDFInfo
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- CN100334721C CN100334721C CNB021231907A CN02123190A CN100334721C CN 100334721 C CN100334721 C CN 100334721C CN B021231907 A CNB021231907 A CN B021231907A CN 02123190 A CN02123190 A CN 02123190A CN 100334721 C CN100334721 C CN 100334721C
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- chip
- pin
- height
- semiconductor package
- semiconductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
Abstract
The present invention relates to a flip chip type semiconductor packaging device with a lead wire frame which can control the back-welding collapse degree of solder lugs, wherein the lead wire frame is composed of a chip base and a plurality of pins. The height of the chip base is bigger than the thickness of the pins to form a certain height difference, and the height difference does not exceed the plumb height of a plurality of solder projections welded by flip chips. Since the good wetability of the lead wire frame can lead the solder lugs of low melting point alloy to continuously collapse when back welding is carried out, a semiconductor chip originally bridged above the chip base by the solder lugs can gradually move down because of the traction of the weight of the semiconductor chip. At this moment, the chip base with larger height can block the movement of the chip to force the solder lugs to stop collapse and maintain a fixed height, and therefore, welding quality can not be influenced by brittleness generated by excessive collapse of the solder lugs.
Description
Technical field
The invention relates to a kind of semiconductor package part, particularly connect the pin connecting-type semiconductor package part of putting semiconductor chip about a kind of crystalline substance that on lead frame, covers.
Background technology
For adapting to the compact developing trend of electronic product, semiconductor device is many towards low cost now, the direction of high-performance and Highgrade integration develops, manufacturing cost at semiconductor device, make every effort on performance and the memory capacity after the improvement, the volume of semiconductor device and integral thickness also require exquisite as far as possible, Sequare shape pin-free planar formula (Quad-Flat Non-leaded:QFN) packaging part only is slightly larger than semiconductor chip packaged in it because of its finished product overall dimensions, and can use cheaply lead frame form (Leadframe Based) to make in batch, now become the main flow of conventional package goods.
Make the Sequare shape pin-free planar semiconductor packaging part and generally be earlier to have on the lead frame of chip carrier and many pins and be equipped with at least one chip semiconductor chip one, routing one by one then, and with many gold threads provide semiconductor chip and and this pin between be electrically conducted, coat this chip with a packing colloid at last.Yet when implementing the operation of gold thread routing, the factors such as too intensive or chip layout (Layout) complexity that often distribute because of pin cause that bank is interlaced with each other behind the routing interts, make that gold thread leans on too near and (Electric Interference) take place electrically to disturb; In addition, when carrying out the colloid encapsulation, long bank often can't bear mould and flow impact and produce gold thread skew (Wire Sweep), touches initiation short circuit problems such as (Short) sometimes even mutually.
Moreover along with maturation is more attained in the development of the manufacturing process of flip chip (Flip Chip) semiconductor package part, using solder bump (Solder Bumps) reflow, to connect method as electrical lotus root to the weld pad general day by day.With the traditional welding operation one by one the electrically conducting manner of routing compare, solder bump adopts automatic contraposition (Self-Alignment) once to plant to connect to be finished time and labour saving more; In view of this, United States Patent (USP) the 5th, 677, No. 567 cases " Leads Between Chips Assembly " invention a kind of lead frame Flip Chip (Flip Chip On Leadframe).As 5 in accompanying drawing not, thisly cover brilliant packaging system 4 to lead frame and comprise the lead frame of making just like metal materials such as copper (not icon), mainly constituted by many pins different in size 42; Several semiconductor chips 43, it has an action face 430 and a non-action face 431, and connects on this action face 430 and be equipped with many solder pad 432; A plurality of solder bumps 44 are to plant on this solder pad 432, make chip 43 action face 430 adopt the mode that faces pin 42, the affixed chip 43 of each reflow on these pin 42 tow sides; And one be formed at the packing colloid 45 that is used for coating this semiconductor chip 43 on the pin 42.
This technology be characterised in that with cover crystal type with these semiconductor chip 43 conductive solder to this pin 42.In the reflow operation after solder bump 44 heating of this leypewter (being generally the soft metal that tin 63%/plumbous 37% alloy is constituted) material reaches uniform temperature, crumple (Collapse) can take place, and and 421 metal congruent meltings (Eutectic) that produce moment of these pin 42 welding contact sites, and then guiding solder bump 44 and 421 " the interface alloy is changed thing altogether " (Intermetallic Compound) thin layers (not icon) that form the firm welding of one deck of pin 42 welding contact sites, just moistening step (Wetting).Because of this lead frame (not icon) is to be made by solderability metals such as copper, possesses good wet characteristic (Wetability), make solder bump 44 welderings appropriate to last pin 42 predeterminated positions (promptly welding contact site 421) of lead frame (not icon), still continue to take place crumple, fusion weld tin projection 44 unrestrictedly expands outwardly, heap stagnates on pin 42 surfaces, as shown in Figure 6.The result of the excessive crumple of solder bump not only makes the solder joints position produce fragility (Brittleness), very easily causes Welding Structure to break even electrically lost efficacy; Difference in height between semiconductor chip and pin also can seriously hinder the enforcement of subsequent handling because of the excessive deformation of solder bump (Deformation) falls sharply simultaneously.
Based on the problems referred to above, as shown in Figure 7, United States Patent (USP) the 6th, 060, No. 769 cases " Flip Chipon Leads Device " have been invented a kind of scolder curtain cover 47 (Solder Mask) that applies in addition on pin 42 predeterminated positions, on it and offer the opening 470 of at least one default bore, plant for these solder bump 44 correspondences and connect.This technical characterstic is to utilize opening size S on the scolder curtain cover 47 to limit the shrinkage of solder bump 44.Heal when big when opening 470 bores on the scolder curtain cover 47, more can allow solder bump 44 to expand (being that shrinkage is bigger) outward, relatively the plumb height h of this solder bump 44 is just little; Can get final product the difference in height of 42 of pre-defined semiconductor chip 43 and pins by opening bore control solder bump 44 shrinkages of scolder curtain cover 47, avoid solder bump the situation of excessive crumple to occur.
But on the lead frame metal surface, impose a scolder curtain cover, need be through very loaded down with trivial details processing procedure (as net-point printing (Screen Printing) or light lithography patterning (Photo-lithographic Patterning) etc.), and the cost costliness is therefore quite difficult in actual production.If form to change the material of solder bump own, for example heighten ratio (tin 5%/lead 95%) plumbous in the leypewter and improve the solder bump fusing point, though can avoid the excessive crumple of solder bump, the solder bump cost often increases more than the twice.
Summary of the invention
The purpose of this invention is to provide the lead frame that produces suitable difference in height between a kind of chip carrier and pin, make the semiconductor chip with a plurality of solder bump reflows to this pin the time, owing to be subjected to stopping of chip carrier, and then the excessive crumple of inhibition solder bump, guarantee to keep preset height between chip in the encapsulating structure and pin, and can promote the semiconductor package part of solder bump soldering reliability.
Another object of the present invention provides a kind of lead frame with chip carrier of good heat sinking function, after making the semiconductor chip borrow a plurality of solder bump reflows to this lead frame, be bonded with each other between chip and chip carrier and make the chip surface heat be able to, and then promote the semiconductor package part of packaging part integral heat sink usefulness by the chip carrier rapid release.
For reaching aforementioned and other purpose, the semiconductor package part that the present invention suppresses excessive crumple is to comprise: the lead frame of a metal material, as forming by materials such as copper, it has a chip carrier and many pins, wherein this chip carrier height must be greater than this pin thickness, and the difference in height between chip carrier and pin must not surpass provides the plumb height that covers brilliant solder bump, pre-definedly on this pin again goes out the welding contact site that several provide the solder bump correspondence to connect to put; One insulating properties heat conduction adhesive is to coat this chip carrier end face, bonding between chip after the reflow and chip carrier; At least one chip semiconductor chip covers brilliant reflow so as to this solder bump to the welding contact site of pin with chip, and one is formed on this lead frame in order to coat the packing colloid of this semiconductor chip.
After above-mentioned packaging system imposes reflow heating and reaches uniform temperature, low-melting soft solder bump begins fusion, crumple, because the copper material lead frame possesses good wet characteristic (Wetability), can continue the crumple of guiding solder bump, make semiconductor chip be subjected to weight own to draw and move down gradually; After semiconductor chip was crimped to insulating properties conduction gluing layer, chip moves the chip carrier that can be subjected to big height to be stopped and stagnates, and forced solder bump to stop to continue crumple and kept a level altitude.
Decide the shrinkage of solder bump by the chip carrier and the difference in height on pin plane on every side, can allow and possess carry out of suitable distance between chip and pin in order to follow-up manufacturing process; And, stop to suppress the lasting crumple of solder bump by chip carrier, also can avoid the solder joints position to produce because of excessive crumple causes fragility, guarantee the structural strength and the electrical quality at solder bond position.
Description of drawings
Below describe characteristics of the present invention and effect in detail with the specific embodiment conjunction with figs.:
Accompanying drawing 1 is the generalized section for the Sequare shape pin-free planar semiconductor packaging part of first embodiment of the invention;
Accompanying drawing 2A is the top view for this lead frame in the semiconductor package part of first embodiment of the invention;
Accompanying drawing 2C to accompanying drawing 2D be making flow chart for the semiconductor package part of first embodiment of the invention;
Accompanying drawing 3A is the generalized section for the Sequare shape pin-free planar semiconductor packaging part of second embodiment of the invention;
Accompanying drawing 3B is the semiconductor package part part section enlarged drawing for second embodiment of the invention;
Accompanying drawing 4 is the generalized sections for the semiconductor package part of third embodiment of the invention;
Accompanying drawing 5 is to be United States Patent (USP) the 5th, 677, the generalized section of the semiconductor package part of No. 567 inventions;
Accompanying drawing 6 is the state simplified schematic diagram of carrying out the solder bump reflow on the existing conducting wire frame structure; And,
Accompanying drawing 7 is to be United States Patent (USP) the 6th, 060, the generalized section of the semiconductor package part of No. 769 inventions.
Label declaration
1,2,3,4 semiconductor package parts, 10 lead frames
11,21,31 chip carriers, 110,310 chip continuing surfaces
111 chip carrier protrusions, 112,212,312 insulating properties heat conduction gluing layers
12,22,32,42 pin ones, 20,320 pin end faces
121 welding contact sites, 421 pin Metal Contact faces
222,322 shallow slots, 13,23,33,43 semiconductor chips
The non-action face of 130,230,430 chip action face, 131,331,431 chips
132,432 solder pad, 14,24,34,44 solder bumps
15,25,35,45 packing colloids, 36 embedded heat sinks
47 scolder curtains cover 470 scolder curtain cover openings
H1, h solder bump height H 2 chip carrier protrusion height
H3 chip carrier and the difference in height of welding contact site
W chip and ridge gaps S scolder curtain cover opening size
Specific embodiment
Below be that conjunction with figs. 1 to accompanying drawing 3 and accompanying drawing 4 describes two embodiment that the present invention suppresses the semiconductor package part of excessive crumple respectively in detail.Its characteristics are, directly are electrically conducted the tool practicality of Sequare shape pin-free planar formula encapsulating products of external device (ED) with chip carrier, then the Sequare shape pin-free planar semiconductor packaging part are described as most preferred embodiment.
Embodiment 1
As shown in Figure 1, the semiconductor package part 1 of the excessive crumple of inhibition of first embodiment of the invention is to comprise a lead frame 10, be many pin ones 2 that have a chip carrier 11 and be peripherally installed with, and this chip carrier 11 highly is greater than these pin one 2 thickness, poor to form a preset height; At least one semiconductor chip 13 towards these chip carrier 11 modes, borrows a plurality of solder bump 14 reflows to be solidly connected on this pin one 2 with its action face 130; One insulating properties heat conduction adhesive 112 (Non-conductive thermal adhesive), in order to coat on this chip carrier, reflow is finished after this semiconductor chip 13 must be so as to being adhered on this chip carrier 11; And one be formed at the packing colloid 15 in order to coat this semiconductor chip 13 on this lead frame 10.
Consult shown in accompanying drawing 2A (top view) and the accompanying drawing 2B (cutaway view), this lead frame 10 is many pin ones 2 that comprise a chip carrier 11 and be peripherally installed with, and wherein respectively has a chip continuing surface 110 and a pin end face 120 on this chip carrier 11 and this pin one 2; This lead frame 10 is by making as metal materials such as copper or iron-nickel alloys, can use existing punching press (Punch) method that these chip carrier 11 central portions are struck out the protrusion 111 of a height greater than pin one 2 thickness, and the chip continuing surface 110 of its protrusion 111 must not surpass the not preceding original height of reflow of this solder bump (not icon) apart from the difference in height of this pin end face 120, and design by predefined shrinkage.
Again, provide the welding contact site 121 of the corresponding welding of this solder bump (not icon) on it defining at least one on this pin end face 120 in addition, because pin one 2 is made of the strong metal material of solderabilities such as copper, have good wet characteristic (Wetability), then need not be more silver-plated in addition on this welding contact site 121, nickel etc. helped the weldering metal level.After treating that this lead frame 10 completes, coating one insulating properties heat conduction adhesive (shown in accompanying drawing 2C last 112) can continue and cover brilliant step on the chip continuing surface 110 of these chip carrier 11 protrusions 111.
Shown in accompanying drawing 2C, this semiconductor chip 13, it has an action face 130 (promptly being equipped with the chip surface of many electronic circuits and electronic building brick) and a relative non-action face 131, and be equipped with several solder pad 132 on this action face 130, weld on it for the soft metal scolder (not icon) of many leypewters (as tin 63%/plumbous 37% low-melting alloy such as grade) and form several solder bumps 14; Then, this semiconductor chip 13 contrapositions, bridge joint of planting appropriate a plurality of solder bump 14 all connects each solder bump 14 in this pin end face 120 and puts on the corresponding welding contact site 121 towards these chip carrier 11 modes so as to action face 130.Because the bump height H2 of these chip carrier 11 protrusions 111 is less than the plumb height H1 of solder bump 14, make 111 of semiconductor chip 13 and chip carrier 11 protrusions have a gap W, know preceding these semiconductor chip 13 real tops that are suspended on this insulating properties heat conduction gluing layer 112 of reflow enforcement then.
Then, treat that reflow is heated to uniform temperature after, shown in accompanying drawing 2D, the 14 beginning fusion crumples (Collapse) of the soft solder bump of low-melting alloy, then this semiconductor chip 13 is subjected to weight traction own and moves down gradually.Because pin one 2 has good wet characteristic, can continue the 14 generation crumples of guiding solder bump causes chip 13 constantly to move down, have only after the action face 130 of this semiconductor chip 13 is crimped to insulating properties conductive adhesive 112, chip 13 moves and can be subjected to stopping of chip carrier 11 protrusions 111 and stagnate, force this solder bump 14 to stop to continue crumple to keep a level altitude, thereby chip 13 and 2 of pin ones possess the enforcement of the unlikely impairment subsequent handling of a suitable spacing, and the generation of fragility phenomenon more can not excessively be caused at the solder joints position of this solder bump 14 and 2 formation of pin one because of crumple.
In addition, because the packaging system of the embodiment of the invention is to be a Sequare shape pin-free planar semiconductor packaging part, therefore the semiconductor chip 13 finished of reflow is borrowed a heat conduction gluing layer 112 to connect to put to the chip continuing surface 110 of this chip carrier 11, therefore the heat that chip 13 runnings produce can all benefit for the lifting of packaging part heat dissipation and the maintenance of chip performance by transcalent chip carrier 11 rapid release.
Embodiment 2
Shown in accompanying drawing 3A, semiconductor package part of the present invention removes as among above-mentioned first embodiment, making one in punching press (Punch) mode has outside the chip carrier (not icon) of protrusion (not icon), also can adopt the method for present embodiment, be chosen on this pin two 2, several welding contact sites 222 that provides solder bump 24 to plant to put are provided in half erosion (Half-etching), and the degree of depth of this welding contact site 222 is prefabricated the finishing of shrinkage of cooperation solder bump 24.When this packaging system 2 carried out the reflow step, shown in accompanying drawing 3B, these solder bump 24 fusion crumples caused chip 23 to move down; After then the action face 230 of this semiconductor chip 23 was crimped to insulating properties heat conduction adhesive 212, chip 23 moved and can be subjected to stopping of chip carrier 21 and stagnate.Therefore, utilize half erosion mode to make this chip carrier 21 and 222 of welding contact sites constitute a suitable height difference H 3, still can obtain and the identical effect of preceding embodiment chip carrier protrusion (not icon), can control the crumple of solder bump effectively.
Embodiment 3
As shown in Figure 4, its structure of the semiconductor package part of third embodiment of the invention is roughly with aforementioned first embodiment, it is to be applied to the four sides to draw flat packaging (Quad Flat Package:QFP) or thin-type small-size encapsulation packaged types such as (Thin Small OutlinePackage:TSOP) that difference is in this flip chip structure, forms one and has many semiconductor package parts 3 as J-shaped or wing shape (Gull Wing) external pin 32.Utilize impact style on many pins 32, to form the welding contact site 322 that sinks downwards and also must make 32 formation one of chip continuing surface 310 and pin of this chip carrier 31 cooperate the suitable difference in height of solder bump 34 shrinkages, and reach the effect equal with the various embodiments described above.
The above is preferred embodiment of the present invention only, is not in order to limit essence technology contents scope of the present invention.Essence technology contents of the present invention is broadly to be defined in claims.Any technology entity that other people are finished, if identical with the definition in claims, or be the change of an equivalence, all will be considered as being covered by within this scope of patent protection.
Claims (6)
1. a flip chip semiconductor package part is characterized in that, this semiconductor package part comprises:
One lead frame, be many pins that have a chip carrier and dispose in abutting connection with this chip carrier, wherein this lead frame material is a metallic copper, and this chip carrier height is greater than this pin thickness, and the height that provides semiconductor chip and this pin to electrically connect a plurality of solder bumps of usefulness is provided the difference in height between this chip carrier and this pin, wherein produces suitable difference in height between this chip carrier and this pin to avoid the excessive crumple of solder bump;
At least one semiconductor chip, this semiconductor chip distance from bottom chip carrier have one at interval, so as to a plurality of solder bumps this semiconductor chip are electrically connected on this pin; And
One packing colloid is in order to coat this semiconductor chip and a plurality of solder bump on this lead frame.
2. as the described flip chip semiconductor package part of claim claim 1, it is characterized in that this difference in height depends on the shrinkage of this solder bump.
3. flip chip semiconductor package part as claimed in claim 1 is characterized in that, this chip carrier has a chip continuing surface, is coated with an insulating properties heat conduction adhesive on it.
4. flip chip semiconductor package part as claimed in claim 1 is characterized in that, this chip carrier central portion is to be formed with a protrusion.
5. flip chip semiconductor package part as claimed in claim 1 is characterized in that, the pin surface that provides a plurality of solder bumps to connect on this pin to put is that half erosion is formed with several weldering knot contact sites.
6. flip chip semiconductor package part as claimed in claim 1 is characterized in that this solder bump is made of low-melting soft metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021231907A CN100334721C (en) | 2002-06-28 | 2002-06-28 | Shrinkage controllable leadframe and flip chip type semiconductor package having same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021231907A CN100334721C (en) | 2002-06-28 | 2002-06-28 | Shrinkage controllable leadframe and flip chip type semiconductor package having same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1466203A CN1466203A (en) | 2004-01-07 |
| CN100334721C true CN100334721C (en) | 2007-08-29 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021231907A Expired - Fee Related CN100334721C (en) | 2002-06-28 | 2002-06-28 | Shrinkage controllable leadframe and flip chip type semiconductor package having same |
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| Country | Link |
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| CN (1) | CN100334721C (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI557856B (en) * | 2014-07-04 | 2016-11-11 | 立錡科技股份有限公司 | Integrated circuit device and package structure thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11165165A (en) * | 1997-12-04 | 1999-06-22 | Tokyo Yogyo Co Ltd | Under sink type water purifier for hair/face washing and kitchen |
| CN1288261A (en) * | 1999-09-10 | 2001-03-21 | 松下电子工业株式会社 | Lead-frame and resin sealing member with same, and photoelectronic device |
| JP2001189345A (en) * | 1999-12-28 | 2001-07-10 | Sony Corp | Connecting method of semiconductor element, and semiconductor device |
| CN1344024A (en) * | 2000-09-15 | 2002-04-10 | 三星Techwin株式会社 | Lead frame and semiconductor pack having same and mfg. method of semiconductor pack |
-
2002
- 2002-06-28 CN CNB021231907A patent/CN100334721C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11165165A (en) * | 1997-12-04 | 1999-06-22 | Tokyo Yogyo Co Ltd | Under sink type water purifier for hair/face washing and kitchen |
| CN1288261A (en) * | 1999-09-10 | 2001-03-21 | 松下电子工业株式会社 | Lead-frame and resin sealing member with same, and photoelectronic device |
| JP2001189345A (en) * | 1999-12-28 | 2001-07-10 | Sony Corp | Connecting method of semiconductor element, and semiconductor device |
| CN1344024A (en) * | 2000-09-15 | 2002-04-10 | 三星Techwin株式会社 | Lead frame and semiconductor pack having same and mfg. method of semiconductor pack |
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| Publication number | Publication date |
|---|---|
| CN1466203A (en) | 2004-01-07 |
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