CH621201A5 - - Google Patents

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Publication number
CH621201A5
CH621201A5 CH355876A CH355876A CH621201A5 CH 621201 A5 CH621201 A5 CH 621201A5 CH 355876 A CH355876 A CH 355876A CH 355876 A CH355876 A CH 355876A CH 621201 A5 CH621201 A5 CH 621201A5
Authority
CH
Switzerland
Prior art keywords
priority
request
block
level
processor
Prior art date
Application number
CH355876A
Other languages
English (en)
French (fr)
Inventor
Earnest M Monahan
Garvin W Patterson
Original Assignee
Honeywell Inf Systems
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Inf Systems filed Critical Honeywell Inf Systems
Publication of CH621201A5 publication Critical patent/CH621201A5/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/461—Saving or restoring of program or task context
    • G06F9/462—Saving or restoring of program or task context with multiple register sets
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G06F9/4818—Priority circuits therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)
CH355876A 1975-03-26 1976-03-22 CH621201A5 (cs)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/562,314 US4028664A (en) 1975-03-26 1975-03-26 Apparatus for dispatching data of the highest priority process having the highest priority channel to a processor

Publications (1)

Publication Number Publication Date
CH621201A5 true CH621201A5 (cs) 1981-01-15

Family

ID=24245776

Family Applications (1)

Application Number Title Priority Date Filing Date
CH355876A CH621201A5 (cs) 1975-03-26 1976-03-22

Country Status (9)

Country Link
US (1) US4028664A (cs)
JP (1) JPS51120145A (cs)
BE (1) BE840015A (cs)
BR (1) BR7601358A (cs)
CA (1) CA1070849A (cs)
CH (1) CH621201A5 (cs)
DE (1) DE2611975A1 (cs)
FR (1) FR2305788A1 (cs)
NL (1) NL7602495A (cs)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4080649A (en) * 1976-12-16 1978-03-21 Honeywell Information Systems Inc. Balancing the utilization of I/O system processors
US4181941A (en) * 1978-03-27 1980-01-01 Godsey Ernest E Interrupt system and method
US4470111A (en) * 1979-10-01 1984-09-04 Ncr Corporation Priority interrupt controller
US4402040A (en) * 1980-09-24 1983-08-30 Raytheon Company Distributed bus arbitration method and apparatus
US4604685A (en) * 1982-02-19 1986-08-05 Honeywell Information Systems Inc. Two stage selection based on time of arrival and predetermined priority in a bus priority resolver
US4535330A (en) * 1982-04-29 1985-08-13 Honeywell Information Systems Inc. Bus arbitration logic
FR2610745B1 (fr) * 1987-02-07 1994-05-27 Nec Corp Systeme de commande de priorite de processus
JPH01303543A (ja) * 1988-05-31 1989-12-07 Fujitsu Ltd メモリアクセス制御装置
US5311461A (en) * 1988-12-30 1994-05-10 International Business Machines Corp. Programmable priority and selective blocking in a compute system
US5203007A (en) * 1988-12-30 1993-04-13 International Business Machines Corporation Overriding programmable priority and selective blocking in a computer system
US5197130A (en) * 1989-12-29 1993-03-23 Supercomputer Systems Limited Partnership Cluster architecture for a highly parallel scalar/vector multiprocessor system
US5371872A (en) * 1991-10-28 1994-12-06 International Business Machines Corporation Method and apparatus for controlling operation of a cache memory during an interrupt
FR2725287B1 (fr) * 1994-09-30 1996-12-20 Sgs Thomson Microelectronics Processeur de commande d'un circuit de compression d'images mobiles
US5923900A (en) * 1997-03-10 1999-07-13 International Business Machines Corporation Circular buffer with n sequential real and virtual entry positions for selectively inhibiting n adjacent entry positions including the virtual entry positions
CN105389203B (zh) * 2015-10-19 2017-11-17 广东欧珀移动通信有限公司 一种指纹识别设备的调用方法、装置及移动终端
CN113162606B (zh) * 2021-03-30 2023-04-07 西南电子技术研究所（中国电子科技集团公司第十研究所） 多优先级控制电路

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3421150A (en) * 1966-08-26 1969-01-07 Sperry Rand Corp Multiprocessor interrupt directory
US3702462A (en) * 1967-10-26 1972-11-07 Delaware Sds Inc Computer input-output system
US3648252A (en) * 1969-11-03 1972-03-07 Honeywell Inc Multiprogrammable, multiprocessor computer system
US3676861A (en) * 1970-12-30 1972-07-11 Honeywell Inf Systems Multiple mask registers for servicing interrupts in a multiprocessor system
GB1397438A (en) * 1971-10-27 1975-06-11 Ibm Data processing system
US3812463A (en) * 1972-07-17 1974-05-21 Sperry Rand Corp Processor interrupt pointer

Also Published As

Publication number Publication date
DE2611975A1 (de) 1976-10-07
CA1070849A (en) 1980-01-29
BE840015A (fr) 1976-07-16
NL7602495A (nl) 1976-09-28
US4028664A (en) 1977-06-07
FR2305788B1 (cs) 1979-07-20
JPS51120145A (en) 1976-10-21
FR2305788A1 (fr) 1976-10-22
BR7601358A (pt) 1976-09-28
AU1157376A (en) 1977-09-08

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Legal Events

Date Code Title Description
PL Patent ceased
PL Patent ceased