CH620049A5 - Method for producing an integrated circuit and integrated circuit produced in accordance with the method - Google Patents

Description

The present invention relates to a method for producing an integrated circuit from a base body made of semiconducting material of a first conductivity type, the base body having at least one P-channel field effect transistor with an insulated gate and one N-channel field effect transistor with an insulated gate and one between contains the two field effect transistors lying separation zone. Furthermore, it relates to an integrated circuit produced by this method.

In a known embodiment, integrated circuits containing an insulated gate field effect transistor are made from a base body of semiconducting material, usually a material of the N-conductivity type, which has a main surface. P-type well zones are formed adjacent to this surface at localized locations on the substrate body. N-channel transistors are produced within the boundaries of the well zones, and P-channel transistors outside the well zones mentioned.

Each of the transistors with such a known structure contains a source zone and a drain zone, which are separated from one another by a channel zone. Transistors are often isolated from leakage effects of undesired surface inversions by so-called protective tapes that surround each transistor to be isolated. Because of the risk of electrical breakdowns, space must be left between each protective tape and the transistor that surrounds it, outside the protective tapes between adjacent protective tapes. This means that a lot of «space» is required for each transistor. Thus, there has been a need for a structure that enables a higher circuit component density than was previously possible.

An important feature of the integrated circuit according to the invention is the closed geometry of the transistors contained therein, since these have a relatively narrow drain zone which is surrounded by a frame-like gate structure, which is preferably of the self-aligning type. The source of each transistor is a zone

which surrounds the frame-like gate structure. In the case of discrete transistors, circuits with such a structure have been known for some time. Integrated circuits are also known in which transistors with a closed geometry have been used. For high frequency operation or those applications where a high operating speed is required, the closed geometry is superior to an open or linear geometry, since it can be used to produce transistors which have a relatively small substrate drain capacitance, a parameter which makes the operating speed known Has limited field effect transistors with an insulated gate and open geometry.

These disadvantages of known embodiments are avoided in the integrated circuit which is produced by the method according to the invention. This method is characterized by the features of claim 1, according to which an integrated circuit is designed according to claim 5.

The subject matter of the invention is described below using an exemplary embodiment and the drawing. In it show:

1 is a plan view of part of an integrated circuit, which shows the structure of a field effect transistor with an insulated gate and an N-channel and a P-channel,

2 shows a section along the line 2-2 in FIG. 1,

3 shows a section along the line 3-3 in FIG. 1,

4 shows a section along the line 4-4 in FIG. 1,

5 shows a section along the line 5-5 in FIG. 1,

6 to 10 are a series of sections which explain the different steps of the described method, and

11 shows a partial floor plan of an integrated circuit to explain the way in which N-channel and P-channel transistors can be combined with one another to form certain switching functions.

A part of the integrated circuit 10 of a complementary field effect transistor with an insulated gate, which has the features of the described integrated circuit, is shown in FIG. 1. The circuit 10 contains a base body 12 made of semiconducting material, such as silicon, which initially has only one type of conductivity (N-conductivity in the present example) and which has a surface 14 (see FIGS. 2, 3, 4 and 5 ). In the present example, the base body 12 is a solid silicon body, but other types of semiconducting material can also be used. For example, the base body 12 can be an epitaxial layer on an insulating substrate, produced using the so-called silicon-on-sapphire technology.

Parts of the main body 12, namely source, drain and channel regions in the main body 12, and the gate electrode on the surface 14, define a field effect transistor 16 with an insulated gate and P-channel, and a similar transistor 18 of this type, but with N channel; this also includes a separation zone 20 which separates the P-channel transistor 16 from the N-channel transistor 18. These different zones include a first frame-like structure 22, which is hereinafter referred to as a protective gate, a second frame-like structure 24 and a third frame-like structure 26, both of which are hereinafter referred to as an active gate. Each of these gate structures includes a layer 28 (FIGS. 2 through 5) of insulating material and, on layer 28, a layer 30 of conductive material. Although layers 28 and 30 in each gate structure are separated from the corresponding layers in all other frame-like structures, the same reference number is used to designate them for the sake of clarity.

Each of the gate structures 22, 24 and 26 has a closed geometry. This means that the gate structures have a shape that corresponds to that of a closed pattern with an opening arranged therein. Rectangular structures are shown, but any other topologically closed form can be used. The rectangular one

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Shape is a preferred shape because it is well suited for integrated circuit structures with a relatively high packing density.

The protective gate 22 surrounds a first part 32 of the surface 14 and is surrounded by a second part 34 of the surface 14. The active gate 24 is arranged on the first part 32 of the surface 14, and the active gate 26 is arranged on the second part 34 of the surface 14. While the active gate 24 in FIG. 1 is arranged lying in the middle of the protective gate 22, this form is not necessary; in practice, the protective gate 22 can be much longer than shown in relation to the active gate 24, so that other frame-like structures, such as the active gate 24, can be arranged on the first part 32 of the surface 14. In this regard, see Fig. 11, the structure of which will be described later.

A well zone 36 with a conductivity type opposite to the conductivity type of the base body 12 - P-conductivity in the present example - is arranged in the base body 12 adjacent to the first part 32 of the surface 14. A zone 38 with N + conductivity is located within the P-well zone 36, adjacent to a portion of the surface 14 that is surrounded by the active gate 24. Another N + conductivity type zone 40 is located within P-well zone 36 adjacent to a portion of surface 14 that surrounds active gate 24. Zones 38 and 40 define the ends of a channel zone 41 of transistor 18.

A zone 42 of the P + conductivity type is arranged in the base body 12 at the part of the surface 14 which is surrounded by the active gate 26, and a further zone 44 of the P + conductivity type is arranged in the base body 12 at the part of the surface 14 which surrounds the active gate 26. Zones 42 and 44 define the ends of a channel zone of transistor 16.

According to the method of manufacturing the integrated circuit 10 using the self-alignment technique, each of the gate structures 22, 24 and 26 has an inner peripheral boundary layer and an outer peripheral boundary layer. For the sake of clarity, the outer peripheral boundary layers of the gate structures are designated with the transfer number 46, the inner ones with 48. Each of zones 38, 40, 42, and 44 has an intermediate surface boundary layer that is substantially directly adjacent to other, inner and outer, peripheral boundary layers of a gate structure, respectively.

A contact arrangement consisting of a section of the first part 32 of the surface 14 is provided to form an ohmic contact to the well zone 36. In the present example, this contact arrangement consists of a zone 50 with P + conductivity with a doping density that is higher than the doping density of the well zone 36. The zone 50 is arranged at the portion of the first part 32 of the surface 14 which lies between the protective gate 22 and the active gate 24. In the present example, although not required, zone 50 surrounds zone 40.

An insulating layer 52 is arranged essentially over the entire surface of the integrated circuit 10 and has openings 54 for contacting the various zones and conductive layers. Layer 52 can be chemically vaporized glass, for example.

Part of a source substrate conductor 56 extends through opening 54 for contacting both P + zone 50 and N + zone 40. Part of a drain conductor 58 projects through opening 54 for contacting zone 38. A gate conductor 60 projects through Opening 54 for contacting the conductive layer 30 of the active gate 24. A drain conductor 62 contacts the zone 42 of the transistor 16. A gate conductor 64 contacts the conductive layer 30 of the active gate 26, and a source conductor 66 is in contact with the zone 44.

The protective gate 22 separates the transistor 16 from the transistor

18. When the circuit is operating, this gate can be regarded as a permanently blocking gate. To produce this state, the layer of conductive material 30 in the protective gate 22 must be electrically connected to the P + zone 44. As shown in FIGS. 1 and 5, this connection consists of a conductor 68 which projects through the window 54 for contacting the protective gate 22 and the zone 44.

The various conductors shown in Figs. 1 through 5 do not connect transistors 16 and 18 to achieve certain circuit functions. Because the structure described here is generally applicable to many different types of circuits. Structure changes and examples of how such a modified structure can be connected to various circuit configurations will be described later in connection with FIG. 11. However, the method according to the invention is first described.

A preferred embodiment of the method is described with reference to FIGS. 6 to 10, in particular its use using a semiconductor base body with a substrate connection. For the sake of clarity, only the parts lying in the sectional plane are shown in FIGS. 6 to 10, those behind are not shown.

In the present example, the method begins with the provision of a semiconductor base body 12 made of silicon with N conductivity, which has a surface 14. In the first step, the insulating layer 28 is grown on the surface 14. This is preferably done by heating the body 12 to a temperature of about 875 ° C in a steam atmosphere and a small amount of HCl gas for a time sufficient to allow the layer 28 to grow to a thickness of about 1000 Â to let.

After the end of the growth of the insulating layer 28, the base body 12 is introduced into a precipitation reactor in which the layer 30 of conductive material, preferably polycrystalline silicon, is deposited thereon. All known precipitation processes can be used for this, preferably the thermal degradation reaction of silane (SiRi). The process is carried out for a time sufficient for layer 30 to grow to a thickness of approximately 3000 Â. Using conventional photolithographic techniques, portions of the layer 30 are etched away using a photomask (not shown) so that the frame-like gate structures 22, 24 and 26 are formed (see FIG. 7).

The next step is to deposit a layer of photoresist (FIG. 8) on the surface of the base body 12 and, using a second photomask, to apply a layer of photoresist in such a pattern that this delimits the boundaries of the P-well zone 36 can be set. It should be noted that the boundaries 72 of the photoresist layer 70 lie within the inner edges of the layer 48 in the protective gate 22. The reason for this is described in the following steps.

The base body 12 is introduced with the photoresist layer 70 into an ion dosing device, and boron is doped in with sufficient energy so that it penetrates both through the polycrystalline material 30 of the active gate 24 and through the gate oxide layer 28. The ion doping is indicated schematically in FIG. 8 by a series of arrows. As a result, a zone 36S is obtained in the body 12 below the active gate 24 and below a part of the surface 14 which surrounds the active gate 24 and another part which is surrounded by the active gate 24.

The photoresist layer is not removed after the ion doping step, and in the next step, the crystal wafer is placed in a solvent for silicon dioxide, such as buffered HF, to remove those parts of the layer 28 that are not either the photoresist or the poly5

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crystalline silicon 30 of the active gate 24 are covered. The result of this step, after the subsequent removal of the photoresist, is shown in FIG. 9, which figure also explains the next step of the method.

After the removal of the photoresist layer 70, this consists of distributing the donors in the zone 36S differently, namely in order to form the P-well zone 36 by heating the intermediate product to a temperature of about 1200 ° C. for about 20 hours. After the end of the doping diffusion into the P-well zone 36, the next step of the method is to diffuse phosphorus into the base body 12 through its unmasked surface parts, as shown in FIG. 9, in order to produce the N + zones 38 and 40. This step is carried out in a conventional manner, and the result is the diffusion of the phosphor into the polycrystalline material of the conductive layer 30.

Without using an additional photomask at this time, the semi-finished integrated circuit 10 is contacted with a solvent for silicon dioxide in order to remove those remaining parts of the layer 28 which are not covered by the polycrystalline silicon material of the various gate structures. This step therefore completes the manufacture of gates 22, 24 and 26.

The next step is to diffuse boron into the uncovered portions of surface 14 in a conventional manner. The result of this step is shown in Fig. 10. After on-board diffusion, P + zones 42, 44 and 50 were created. Boron is also diffused into parts of the N + zones that are exposed during this step, and the concentration of the donor in this zone 40 should be sufficiently high, i.e. around 1021 atoms / cm3, so that this material does not enter through the boron diffusion one of the P conductivity type is converted.

In the next step, the glass coating 52 is applied. This can be done in any viable way, but preferably by a chemical vapor precipitation process. The final steps of the process are conventional; a third and fourth photomask are used. The third photomask is used to form the openings 54 in the glass coating 52. A continuous layer of aluminum is then deposited on the surface, and the fourth photomask is used to form the various conductors 56, 58, etc. The manufacture of the integrated circuit is thus ended.

In this manufacturing method, the contacting of the upper side of the circuit board with the material of the base body 12 is difficult. The reason for this is that all N + -diffused parts are surrounded by a P-well zone and thus contact with the substrate is not possible without an interposed PN junction. However, contact with the body 12 can be made directly on the rear side (not shown) of the semiconductor crystal wafer.

It is possible to manufacture integrated circuits for which the four-mask technique described here was developed by a simpler method using five photomasking steps. In the five photomasking steps, well zone 36 is conventionally formed prior to the first step in the process described above. The N + zones 38 and 40 are then produced by the method at suitable points in time by photomasking steps, using a mask which is constructed in such a way that both the area of the well zone 36 is exposed and at least one additional area outside the area Well zone 36 into which phosphorus can be diffused. The rest of the manufacturing process is the same. The advantages of the five-photomask process are: doping with high energy boron is not required, contact with the N substrate can be made in a conventional manner via an N + zone (not shown), and the N + layer, which is no longer must be identical to the diffusing sources, can be used as a channel lock, diffused power supply rail, etc.

11 shows, for example, how transistors which have been produced in accordance with the structure and method described above can be connected to one another in order to carry out certain logic circuit functions. 11 is a plan view of the integrated circuit 74. The parts of the logic circuit are a NOT gate 75 shown in the upper part of the figure, a transmission link 76 shown in the middle part of the figure, and one NAND gate 78, which is shown in the lower part of the figure.

The logic circuit shown in FIG. 11 contains at least one N-channel transistor and one P-channel transistor. In the illustrated embodiment, there is a P-well zone, which is constructed like the P-well zone 36 and lies within the boundary layers of a protective gate 80, which is used to separate all N-channel transistors from all P-channel transistors. A P + zone 82 can be seen in the inner boundary layer of the protective gate 80 in FIG. 11, which corresponds to the P + zone 50 in FIG. 1. A planar N + zone 84 is arranged within the P + zone 82. Both zones, namely the P + zone 82 and the N + zone 84 are contacted by a conductor 85, which connects them to a source of relatively low voltage Vss. This connection is also made to the P-well zone of the active gate 74 via the zone 82.

A planar P + source zone 86 is arranged outside the boundary layers or boundaries of the protective gate 80. A conductor 88 is connected to the protection gate 80 and to the planar source zone 86. It can also be connected to a terminal of relatively high potential VDd.

The NON gate 75 includes an N-channel transistor 90 and a P-channel transistor 92. The source of the N-channel transistor 90 is formed by the planar N + source zone 84. The gate 94 of the transistor has a frame-like structure similar to the other frame-like structures. The drain of transistor 90 is formed by a region 96 of the N + conductivity type within gate 94. The source of the P-channel transistor 92 is the P + source zone 86. The transistor 92 has a gate 98 and a drain 99 of the P + conductivity type. A conductor 100 connects the gate 94 to the gate 98 of the transistors 90 and 92 and can be connected to an input terminal labeled A. A conductor 102 connects the drain 96 to the drain 99 of the transistors 90 and 92 and can be connected to an output terminal A. The operation of the NON gate 75 is the same as the operation of known CMOS type NON gate.

The transmission element 76 contains two transistors 104 and 106. Of particular importance in the circuit described is that, thanks to the technology used in its manufacture, it is possible to separate the transistors 104, 106 from the other transistors, namely from their N + source zone 84 or P + source zone 86. This is done by surrounding transistor 104 with a isolation gate 108 and providing a conductor 109 that connects gate 108 to zone 84 to keep the zone under gate 108 permanently off . Thus, there is another N + conductivity type zone 110 that results from the operation of gate 108, and zone 110 forms the source zone for transistor 104. The gate of transistor 104 is formed by a gate 112 and its drain is one therein arranged N + zone 114.

A separation gate 115, which is equivalent to the separation gate 108, surrounds the transistor 106 and defines a further P + zone 117, which forms the source of the transistor 106. The gate of transistor 106 is formed by gate 118 and the drain of the

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Transistor 106 is the P + zone 120 therein. A conductor 116 connects the protection gate 115 to the P + source zone 86 to keep the zone under the gate 115 in the permanently blocked state.

A conductor 122 is connected to the gate 112 of the transistor 104 and can be connected to a terminal of the integrated circuit in order to tap a control signal at a terminal B of the gate 112. A conductor 124 is assigned to the gate 118 of the transistor 106 and is intended to be connected to a terminal of the integrated circuit for applying a control signal Ë, the polarity of which is opposite to the polarity of the control signal applied to the conductor 122. An input signal conductor 126 is connected to the corresponding source zones 110 and 117. This arrangement works like a complementary transmission gate and similar to transmission elements of the known CMOS type.

The NAND link 78 demonstrates how transistors can be connected in series and in parallel using the technology described. The NAND gate 78 consists of two N-channel transistors 130 and 132, the source and drain line channels of which are connected in series as described below, and two P-channel transistors 134 and 136, the source and drain line channels of which are connected in parallel. The N + source zone 84 forms the source of the transistor 130. The gate of the transistor 130 is formed by a structure 138 which, like the other frame-like structures, surrounds a zone 140 with N + conductivity. This latter zone 140 forms a common drain for transistor 130 and the source for transistor 132. Transistor 132 has a gate 142 and a drain 144, which is formed by an N + zone within gate 142. Transistor 134 has a source formed by P + source region 86, a gate 146, and a P + drain region 148. Similarly, transistor 136 has a source formed by P + source region 86, a gate 150, and one P + drain zone 152 is formed.

A conductor 154 connects the gate 138 of the transistor 130 to the gate 150 of the transistor 136 and can be connected to a terminal labeled C of the component unit. A conductor 156 connects the drain 144 of the transistor 132 to the drain 148 of the transistor 134 and the drain 152 of the transistor 136. It forms the output signal conductor for this NAND gate and is labeled C.D. A conductor 158 is connected to the gate 142 of transistor 132 and to the gate 146 of transistor 134. It can be connected to a terminal labeled D on the component unit.

In operation of the NAND gate 78, when a high potential, that is to say the potential VDD, is applied to both terminals C and D, the transistor 132 will conduct and both transistors 134 and 136 will block. In this case the signal appearing at the output terminal C.D will be substantially equal to Vss. When a low signal, i.e. Vss, is applied to both terminals C and D, transistors 130 and 132 are blocked, transistors 134 and 136, on the other hand, are conductive, so that the output signal occurring at terminal C.D is essentially equal to VDd. If high potential is applied to C and low potential is applied to D, the

Transistor 130; transistor 132 is turned off. In this state, the potential VDD also occurs at the output C.D. If a high potential is applied to D and a low potential is applied to C, transistor 130 is blocked and transistor 132 conducts, transistor 134 is blocked and transistor 136 conducts, which is why the output signal VDD also occurs at C.D. There is therefore only one logical state in which the signal Vss occurs at the output C.D. This is the case when the potential VDo is applied to both C and D. In other words, this circuit behaves like a logic NAND gate.

Other logic functions can also be implemented with this technique. They are not described here because their structure is quite obvious to those skilled in the art who have become familiar with the present description. Multiple transistors can be connected in series in the same way as transistors 130 and 132 by surrounding the gates of these transistors with an additional gate, not shown, but there is a limit to this technique in that each transistor connected in series is wider than the transistor it surrounds, so that the counter conductance of the different transistors is different. In most circuits, however, large deviations in the conductance of the transistors used therein are undesirable.

The structure described here and the method described here have several advantages over the known CMOS technology. The integrated circuit does not require protective tapes to separate the switching elements or zones contained therein. It is therefore not necessary to reserve space for the protective tapes. Therefore, the packing density can be higher compared to integrated circuits which have been manufactured using CMOS technology. The construction of the transistor with a closed geometry has the advantage that the ratio of the counter conductance to the drain capacitance is improved for the transistors; this makes them faster than known integrated circuits. Due to the planar structure described in FIG. 11, a source contact is not required for every transistor in a given integrated circuit.

In the method described, only four photomasks are required to fabricate any given integrated circuit. This results in lower costs and simpler fabrication, so that integrated circuits can be manufactured more economically. The economy is also improved by the fact that three diffusions can be made with a single photomask setting (that is, with the setting required to form the photoresist layer 70 in FIG. 8). This setting is not critical since the limits of the photoresist layer 70 can change greatly in position from one integrated circuit to another integrated circuit without the operating behavior or the production being adversely affected thereby. The four-mask process has the above-mentioned disadvantage that substrate contacting is relatively difficult. Conversely, this problem does not occur with five-mask technology.

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Claims (15)

620049 PATENT CLAIMS 1. A method for producing an integrated circuit from a base body made of semiconducting material of a first conductivity type, characterized by the steps: producing a coherent first film (28) from insulating material on the surface (14, FIG. 6) of the base body; Forming a continuous second film (30) of conductive material on the first film (28) of insulating material; Removing portions of the second film (30) to form a pattern therein having at least a first frame-like structure (22) and a second frame-like structure (24) disposed within the first frame-like structure (22), and a third frame-like structure (26) which is arranged completely outside the first frame-like structure (22) (FIG. 7); Creation of a marking coating (70) on the base body (12) from a material which is impermeable to donor atoms, wherein a pattern is formed in the masking coating (70) such that only the second frame-like structure (24) with the surface of the first film ( 28) lies uncovered therein, and the edge of the masking covering (70) comes to lie within the first, frame-like structure (22) and outside of the second, frame-like structure (24), and surrounds the second, frame-like structure (24) (FIG . 8th); Doping acceptor atoms into the base body (12) to form a coherent zone (36) of a second opposite conductivity type under at least the parts of the first film (28) which are uncovered during the formation of the masking coating (70) and under the second frame-like Structure (24) (Fig. 8); Removing the uncovered portions of the first film (28) (Fig. 9); Doping donor atoms into the base body (12) in order to form zones (40) of the first conductivity type (N +) directly adjacent to the parts of the surface (14) which lie inside and outside the second frame-like structure (24) (FIG . 9); Removing all remaining portions of the first film (28) except those underlying the first (22), second (24) and third (26) frame-like structures (Fig. 10); and doping acceptor atoms into those parts (42, 44, 50) of the base body (12) which directly adjoin the parts of the surface (14) which are not different from the first (22), second (24) and third (26) , frame-like structure are covered (Fig. 10). 2. The method according to claim 1, characterized in that the contiguous zone (36) of the opposite conductivity type (P) after the formation of the masking coating (70) by doping ions of the opposite conductivity type (P) into the base body (12) with a Energy is generated which is not sufficient to penetrate the masking coating (70), but is sufficient to penetrate the first film (28) and the combination of the first (28) with the second (30) film. 3. The method according to claim 1, characterized in that the doping of donor atoms into the base body (12) to form zones (40) of the first conductivity type (N +), the diffusion of the acceptor atoms into the base body (12) through the surface parts within and includes outside the frame-like structure. 4. The method according to claim 3, characterized in that the base body is of the N conductivity type, the donor atoms are phosphorus atoms, the concentration of the phosphorus in the zones of the first N conductivity type (N +) is greater than 1021 atoms / cm3, and that Doping acceptor atoms into those parts (42, 44, 50) of the base body (12) which directly adjoin the parts of the surface (14) which are not different from the first (22), second (24) and third (26), frame-like structure are covered, the diffusion of boron atoms in the base body (12) to a concentration which is not sufficient to convert zones of the N + conductivity type into zones of the P conductivity type. 5. Integrated circuit produced by the method according to claim 1 with at least one P-channel field-effect transistor with insulated gate and an N-channel field-effect transistor with insulated gate, and a separation zone for separating the P-channel field-effect transistor with insulated Gate of the N-channel field effect transistor with insulated gate, characterized by first (22), second (24) and third (26), frame-like structures, each of which has a layer (28) of insulating material on the surface (14) and a layer ( 30) of conductive material on the layer (28) of insulating material, the first, frame-like structure (22) having a closed geometry by surrounding a first part (32) of the surface (14) and a second part ( 34) of the surface (14), the second, frame-like structure (24) also has a closed geometry and is arranged on the first part (32) of the surface (14), and the third, frame-like structure (26) also has a closed geometry and is arranged on the second part (34) of the surface (14); a well zone (36) with a conductivity type opposite to the conductivity type of the base body (12), which is arranged in the base body (12) directly adjacent to the first part (32) of the surface (14); a contact arrangement (50) consisting of a part of the first part (32) of the surface (14) and making an ohmic contact with the well zone (36); a zone (38) with a conductivity type equal to the conductivity type of the base body (12), which is arranged within the well zone (36) directly at that part of the surface (14) which is surrounded by the second, frame-like structure (24) ; a zone (40) having a conductivity type equal to the conductivity type of the base body (12), which is arranged within the well zone (36) directly adjacent to that part of the surface (14) which surrounds the second, frame-like structure (24); a zone (42) with a conductivity type that is opposite to the conductivity type of the base body (12) and that is arranged directly adjacent to the part of the surface (14) which is surrounded by the third frame-like structure (26); and a zone (44) with a conductivity type that is opposite to the conductivity type of the base body (12) and that is arranged directly adjacent to the part of the surface (14) that surrounds the third, frame-like structure (26). 6. Integrated circuit according to claim 5, characterized in that the contact arrangement (50), which is in ohmic contact with the well zone (36), a zone with a conductivity type opposite to the conductivity type of the base body and a higher doping than the well Zone (36), and the region of the first part (32) of the surface (14) is arranged, which lies between the first (22) and second (24), frame-like structure. 7. Integrated circuit according to claim 6, characterized in that the zone (50) of higher doping directly surrounds the zone of the same conductivity type as the base body within the well zone (36) which surrounds the second, frame-like structure (24). 8. Integrated circuit according to claim 7, characterized in that each of the frame-like structures (22, 24, 26) has an inner, peripheral boundary layer (48) and an outer, peripheral boundary layer (46), and that the zone (50) is higher Doping is provided with a surface intermediate boundary layer which is practically directly adjacent to the inner, peripheral boundary layer (48) of the first, frame-like structure (22). 9. Integrated circuit according to claim 8, characterized in that the zones of the same and opposite conductivity type are provided with a surface intermediate boundary layer which is practically directly adjacent to at least one of the inner or outer peripheral boundary layers of a frame-like structure. 2nd 5 10th 15 20th 25th 30th 35 40 45 50 55 60 b5 3rd 620049 10. Integrated circuit according to claim 5, characterized in that the zone (44) of opposite conductivity type, which surrounds the third frame-like structure (26), also surrounds the first frame-like structure (22). 11. Integrated circuit according to claim 10, characterized in that the layer of conductive material (30) in the first frame-like structure (22) is connected to the zone (44) of opposite conductivity type, which is the first (22) and third (26 ), frame-like structure surrounds. 12. Integrated circuit according to claim 5, characterized by a fourth, frame-like structure which is arranged like the first, second and third, frame-like structure on the first part of the surface. 13. Integrated circuit according to claim 12, characterized in that the fourth frame-like structure surrounds the second frame-like structure. 14. Integrated circuit according to claim 12, characterized by a fifth, frame-like structure which, like the other frame-like structures, is arranged on the second part of the surface. 15. Integrated circuit according to claim 14, characterized in that the fifth frame-like structure surrounds the third frame-like structure.