CA1057413A - Integrated circuit device including both n-channel and p-channel insulated gate field effect transistors - Google Patents
Integrated circuit device including both n-channel and p-channel insulated gate field effect transistorsInfo
- Publication number
- CA1057413A CA1057413A CA253,457A CA253457A CA1057413A CA 1057413 A CA1057413 A CA 1057413A CA 253457 A CA253457 A CA 253457A CA 1057413 A CA1057413 A CA 1057413A
- Authority
- CA
- Canada
- Prior art keywords
- frame
- region
- type
- conductivity
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000005669 field effect Effects 0.000 title claims description 5
- 238000000034 method Methods 0.000 claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 claims abstract description 8
- 239000004020 conductor Substances 0.000 claims description 29
- 239000000463 material Substances 0.000 claims description 11
- 239000003607 modifier Substances 0.000 claims description 11
- 239000011248 coating agent Substances 0.000 claims description 9
- 238000000576 coating method Methods 0.000 claims description 9
- 230000002093 peripheral effect Effects 0.000 claims description 8
- 229910052796 boron Inorganic materials 0.000 claims description 6
- 239000011810 insulating material Substances 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 239000011574 phosphorus Substances 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- 230000008878 coupling Effects 0.000 claims description 2
- 238000010168 coupling process Methods 0.000 claims description 2
- 238000005859 coupling reaction Methods 0.000 claims description 2
- 230000000873 masking effect Effects 0.000 claims 5
- 125000004429 atom Chemical group 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 125000004437 phosphorous atom Chemical group 0.000 claims 1
- 239000007787 solid Substances 0.000 claims 1
- 230000000295 complement effect Effects 0.000 abstract description 6
- 230000008569 process Effects 0.000 description 17
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 238000009792 diffusion process Methods 0.000 description 8
- 239000000758 substrate Substances 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 3
- 238000010276 construction Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- NLZUEZXRPGMBCV-UHFFFAOYSA-N Butylhydroxytoluene Chemical compound CC1=CC(C(C)(C)C)=C(O)C(C(C)(C)C)=C1 NLZUEZXRPGMBCV-UHFFFAOYSA-N 0.000 description 1
- 241000282337 Nasua nasua Species 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 150000001638 boron Chemical class 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0927—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising a P-well only in the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
- Element Separation (AREA)
- Semiconductor Memories (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Abstract A complementary MOS integrated circuit device, adapted for fabrication with relatively high circuit density, includes relatively fast transistors with a closed gate geometry. Permanently-off gates surround transistors to isolate them from other transistors.
A method of making this structure involves self-aligned gate techniques in which the sources and drains are defined as regions which surround the gates and are surrounded by the gates, respectively.
A method of making this structure involves self-aligned gate techniques in which the sources and drains are defined as regions which surround the gates and are surrounded by the gates, respectively.
Description
RCA 66,383 .
- .
~)S~7~:i3 This invention relates to integrated circuit devices of the type which include insulated gate field effect transistors (IGFETs) as active elements therein.
The invention is a novel structure for a complementary insulated gate field effect integrated circuit device and a novel me~hod of making that structure.
In one known form, complementary IGFET integrated circuit devices are made from a substrate body of semiconductive material, usually silicon of N type conductivity, which has a principal surface. Well regions of P type conductivity are formed adjacent to this surface `
in localized portions of the substrate body. N-channel transistors are fabricated within the boundaries of the well regions and P-channel transistors are formed outside the well regions.
Each transistor in such known structures comprises a source region and a drain region spaced apart by a channel region. Transistors often are isolated from the leakage effects of undesired surface inversion by means of so-called guard bands, one of which surrounds each transistor which must be isolated. Because of breakdown effects, space must ~ "
be left between each guard band and the transistor which it 25 surrounds and space must be left outside the guard bands -. . , between adjacent guard bands. The result of these spacings is that substantial silicon "real estate" is required for each transistor. A need has existed for a structure which ;~
can provide higher circuit component density than has previously been available.
- .
~)S~7~:i3 This invention relates to integrated circuit devices of the type which include insulated gate field effect transistors (IGFETs) as active elements therein.
The invention is a novel structure for a complementary insulated gate field effect integrated circuit device and a novel me~hod of making that structure.
In one known form, complementary IGFET integrated circuit devices are made from a substrate body of semiconductive material, usually silicon of N type conductivity, which has a principal surface. Well regions of P type conductivity are formed adjacent to this surface `
in localized portions of the substrate body. N-channel transistors are fabricated within the boundaries of the well regions and P-channel transistors are formed outside the well regions.
Each transistor in such known structures comprises a source region and a drain region spaced apart by a channel region. Transistors often are isolated from the leakage effects of undesired surface inversion by means of so-called guard bands, one of which surrounds each transistor which must be isolated. Because of breakdown effects, space must ~ "
be left between each guard band and the transistor which it 25 surrounds and space must be left outside the guard bands -. . , between adjacent guard bands. The result of these spacings is that substantial silicon "real estate" is required for each transistor. A need has existed for a structure which ;~
can provide higher circuit component density than has previously been available.
-2-RCA 66,383 105'74~1L3 -1An important feature of the present novel device is a closed geometry for the transistors thereof. Each transistor in the present device comprises a relatively small drain region surrounded by a frame-like gate structure, which ~-5 ls preferably of the self-aligned type. The source of each -transistor is a region which surrounds the frame-like gate -~ ' -structure. In discrete transistor orm~ devices hlaving this geometry have been known for some time. Integrated circuit devices are also known in which transis~ors having closed 10 geometries have been employed. For high frequency or fast ~ ~
applications~ the closed geometry is superior to an open ;~ ;
or linear geometry because it provides a transistor having a relatively low drain-to-substrate capacitance, a parameter -;~
which has limited the speed of known open-geometry insulated ,~
gate ~ield-effect transistors.
In the drawings~
PIGURE 1 is a plan view of a portion of an integrated circuit device, illustrating the construction :
of one ~-channel and one P-channel insulated gate field 20 effect transistor therein. -~
FIGURE 2 is a cross-section taken along the line 2 - 2 o f F I GURE 1 . ``: :
FIGURE 3 is a cross-section taken along the line
applications~ the closed geometry is superior to an open ;~ ;
or linear geometry because it provides a transistor having a relatively low drain-to-substrate capacitance, a parameter -;~
which has limited the speed of known open-geometry insulated ,~
gate ~ield-effect transistors.
In the drawings~
PIGURE 1 is a plan view of a portion of an integrated circuit device, illustrating the construction :
of one ~-channel and one P-channel insulated gate field 20 effect transistor therein. -~
FIGURE 2 is a cross-section taken along the line 2 - 2 o f F I GURE 1 . ``: :
FIGURE 3 is a cross-section taken along the line
3-3 of FI GURE 1 . : . .
FIGURE 4 is another cross-section taken along `
the line 4- 4 of FIGIJR~
FIGURE 5 is a partial cross-section taken along - 3~
; ~:
, .. -.. ~, . . . , ., . , . ..... ~ . . . .. . .
-- RCA 66,383 10~ l3 l the line 5-5 of FIGIJ~E l.
FIGURES 6-10 are a series of cross-sections illustrating various steps in the present novel method.
FIGURE 11 is a partial plan view of an integrated circuit device illustrating the manner in which N-channel and P-channel transistors may be combined to provide certain circuit functions.
A portion of an integrated device 10 of the complementary IGFET type having the features of the present invention is illustrated in FIGURE 1. The device 10 comprises a body 12 of semiconductive material such as silicon, which is initially of one type conductivity ~N type in this example) and which has a surface 14 (See FIGURES 2,3,4,and 5).
In this example, the body 12 is a bulk silicon body, but 15 other forms of semiconductor material may also be used. For ;
exampleg the body 12 may be an epitaxial layer on an insulating substrate,in the so-called silicon-on-sapphire technology.
Means including the body 12, that is, source, drain and channel regions in the body 12 and gate electrode means on the surface 14, define a P channel IGFET 16 and an N channel IGFET 18, together with means 20 for isolating the P channel transistor 16 from the N channel transistor 18.
These various means comprise a first frame-like structure 22, 25 hereafter called a guard gate, a second frame-like structure ~-24, and a third frame-like structure 26, each hereafter called an active gate. Each of these gate structures includes a layer 28 (FIGURES 2 to 5) of insulating material and a layer 30 of conductive material on the layer 28 of insulating material. Although the y -. . ..
RCA 66,383 ~35~
.
in any one gate structure are separa~e from the corresponding layers in each of the other frame-like structures, the same reference numeral is applied to each of ~he respective insulating and conductive layers for convenience.
Each of the gate structures 22, Z4 and 26 has a closed geometry. By this is meant that the gate structures have the configuration of a closed pattern which has an opening therein. While rectangular structures are shown, ; -any suitable topologically closed shape may be adopted. The rectangular shape i5 preferred, for its adaptability to ~ `
integrated circuit structures of relatively high packing density.
The guard gate 22 surrounds a first portion 32 of ;
the surface 14 and is surrounded by a second portion 34 of the surface 14. The active gate 24 is disposed on the ~ ~
first portion 32 of the surface 14 and the active gate 26 is `~ ~`
disposed on the second portion 34 of the surface 14. While -. ~ .
the active gate 24 is shown in FIGURE 1 as centered within the guard gate 22, this configuration is not required and in ~
fact9 the guard gate 22 may be much larger with respect to ~ -the active gate 24 than is shown, so that other frame-like ~-gate structures like the active gate 24 may be disposed on the first portion 32 of the surface 14. See FIGURE 11 for example, the structure of which will be described later.
A well region 36 of conductivity type opposite to that of the body 12, P type in this example, is in the body 12 adjacent to the first portion 32 of the surface 14 A region 38 of N~ type conductivity is within the P well region 36 adjacent to a part of the surface 14 which is surrounded by the active gate 24. Another region 40 of N~
,~
.
.. , . , . ~, . . .. .
.: . .: , - . . ., ~ , :
: . . . , .. .... , ,: .
RCA 66,383 ~(~574~;~
l type conductivity is within the P well region 36 adjacent to a part of the surface 14 which surrounds the active gate 24. The regions 38 and 40 define the ends of a channel zone 41 for the transistor 18.
A region 42 of P+ ~ype conductivity is in the body 12 adjacent to `a part of the surface 14 which is surrounded by ~he active gate 26, and another region 44 of P+ type conductivity is in the body 12 adjacent to a ;
part of the surface 14 which surrounds the active gate 26. .- `
The regions 42 and 44 define the ends of a channel zone 45 for the transistor 16.
Owing to ~he process which is used to make the ~ ~
device 10, which process involves se~f-aligned gate ~ `
techniques, each of the gate structures 22, 24 and 26 has an inner peripheral boundary and an outer peripheral boundary.
~or convenience, the outer peripheral boundaries of the gate structures are each designated by the reference numeral 46 and the inner peripheral ~4Dn~ari2s are desi~nated b~ the ~ ;:
reference numeral 48.Each of the regions 38, ~0, 42, and 44 has ~ .
. -aSurface-intercept boundary substantially contiguous with one or the other of an inner or an outer pe~ipheral boundary : ~.
of a gate structure.
Means including a part of the first portion 32 of the surface 14 is provided for establishing ohmic contact to the well region 36. In this example, this means includes a region 50 of P+ type conductivity, of doping density higheT
than the doping density in the well region 36. The region 50 lies adjacent to that part of the first portion 32 of ~he RCA 66,383 105~
1 surface 14 which lies between the guard gate 22 and the active gate 24. In this example, although not required, the region 50 surrounds the region 40.
An insulating coating 52 overlies substantially all o~ the surface of the device lO and has apertures 54 : ;~
therein for permitting contact to be made to the various regions and conductive layers. The layer 52 may be composed of, for example, a chemical vapor deposited glass.
A source-substrate conductor 56 has a portion -~ .
10 thereof extending through an opening 54 into contact with . ;~ :
both the P+ type region 50 and the N+ type region 40. A
.. ~ . , .
drain conductor 58 has a portion thereof extending through ~`
an opening 54 into contact with the region 38. A gate ,. . . .
conductor 60 extends through an opening 54 into contact with the conductive layer 30 of the active gate 24. A
drain conductor 62 extends into contact with the region 42 in the transistor 16. A gate conductor 64 extends into contact with the conductive layer 30 of the active gate 26, and a source conductor 66 extends into contact with the .`. ~-region 44.
The guard gate 22 provides a means for isolating the transistor 16 from the transistor 18. In the operation ~ .
of the device, this gate may be considered to be a ~ :
permanently-off gate and in order to produce the permanently- ~:~
off condition, means are provided for electri-cally coupling .
the layer of conductive material 30 in the guard gate 22 with the P+ type region 44. As shown in FIGURES 1 and 5 this latter means comprises a conductor 68 which extends through apertures 54 into contact with the guard gate 22 and the region 44.
, .. -- RCA 66,383 :
1(~574~3 ~:
I The several conductors shown in FIGURES 1 to 5 do not interconnect the transistors 16 and 18 together to perform any circuit function, inasmuch as the structure described here is generally applicable to many dif~erent circuit configurations. Modifications of the structure thus far described and examples of the ways in which the modified structures may be connected in certain circuit `
configurations will be described below with respect to FIGURE 11. Before that however, the present novel method will be described FIGURES 6 to 10 illustrate one embodiment of the present novel method. particularly the application of ,~
the method to a bulk semiconductor body. For convenience, the cross-sections of FIGURES 6 to 10 show only the -~
configuration in the plane o the cross-section. .
In this example, the process begins with a semiconductor body 12 of silicon of N type conductivity which has a surface 14. The first step in the present process is to grow the insulating layer 28 on the surface 14.
Preferably, this step is accomplished by heating the body 12 to a temperature of about 875C in an atmosphere of steam and a small quantity of HCl gas for a time sufficient - O .
to grow the layer Z8 to a thickness of approximatel~ l,OO~A.
After the completion of the grow~h of the ~-insulating layer 28, the body 12 is placed in a deposition reactor and the layer 30 of conductive materlal, preferabl~
polycrystalline silicon, is deposited thereon. Any~ kno~n deposition reaction ma~ be emplored, preera~1y the thermal -decomposition reaction of silane ~SiH4) The process is ~` -carried out for a time sufficient to grow the la~er 30 to a ~8-.... .. .... .
RCA 66,383 ~0S741~3 l thickness of approximately 3000A. Using conventional : ~;
photolithographic technology involving a first photomask ~not shown) the layer 30 is next defined into the pattern of ~.
the frame-like gate structures 22, 24, and 26. See FIGURE 7.
The next step is to deposit a layer 70 of photoresist (FIGURE 8) on the upper surface of the body 12 and to define this layer of photoresist, using a second ~:
photomask, into the pattern which defines the boundaries ~ -of the P well 36. Note that the boundaries 72 of the .
10 photoresist layer 70 lie well inside the inner edge of the ~ :
layer 48 in the guard gate 22. The reason ~or this will be `~
made clear in the description of the succeeding steps. ~ . :
With the layer 70 of photoresist in place, the :~
body 12 is placed in an ion implantation machine and boron 15 is implanted at sufficiently high energy so that it :
penetrates both the polycrystalline material 30 of the active gate 24 and the gate oxide layer 28. The ion implantation is schematicall~ shown by a series of arrows in FIGURE 8, and the result of the implantation is a ~ .
20 region 36S in the body 12 beneath the active gate 24 and beneath a part of the surface 14 which surrounds *he active gate 24 and another part which is surrounded b~ the active .
gate 24, The photoresist coati~g is left in place after the `~
25 ion implantation step and the wafer is next placed in a ..
solvent for silicon dioxide such as buffered HF in order to ~: :
remove those porkions of the layer 28 which are not covered by either the photoresist or the polycrystalline silicon 3~
of the active gate 24. The result of this step, after the ~ ;
su~sequent removal of the photoresist, is shown in FIGURE 9, :
g RCA 66,383 ~(~5 ~
1 which also illustrates the next step in the process.
After the removal of the photoresist layer 70 the next step is ~o redistribute the conductivity modifiers in the regions 36S to form the P well region 36, by heating the device to a temperature of about 1200C for about 20 hours After the completion of the drive-in diffusion of the P well 36, the next step in the process is to diffuse phosphorus into the body 12 through the unmasked areas thereof as shown in FIGURE 9 to form the N+ type regions 38 and 40. This step is conventionall~ performed and results also in the diffusion of phosphorus into the polycrystalline silicon material of the conductive layer 30.
Without employing an additional photomask at `-~
this point, the device 10 is contacted ~ith a solvent for silicon dioxide to remove those remaining portions of t~e layer 28 which are not covered by the pol~crystalline ;~
silicon material of the several gate structures. This ste therefore completes the fabrication of the gates Z2, 24 and 26.
The next step is to difuse ~oron, b~ conven~ional processes~ into the uncovered portions. of the surface 14.
The result of this step is illustrated in FIGURE 10. After t~e boron diffusion, P+ type regions 42~ 44 and 50 are present. Boron will also be diffused into portions of the N+ type region 40, which are also exposed during this step, and the concentration of modifiers in the region 40 should ~
be sufficiently high, i.e. about 1021 atom/cm3, so that the ` ~ ~ -material thereof is not reconY~rted to P type by this boron -diffusion.
-10- `
RCA 66,383 ' ~
1(~5 7 ~ ~ ~
1 The next step is to deposit the glass coating 52.
This may be accomplished in any desired manner and preferably is done by chemical vapor deposition processes.
The final steps in the method are conventional,involving the use of a third and a fourth photomask. The third photomask is used to define the locations of the apertures 54 in the glass coating 52. After that definition step, a continuous layer of aluminum is deposited on the surface and the fourth photomask is used to define the various conductors 56, 58 etc. The fabrication of the device is then complete.
As a result of this processing, the establishing of contact from the top side of the device to the material ~
of the body 12 is difficult. This is so because all N~ ~ ;
l5 type diffusions are surrounded by a P well and consequently ~;
contact to the substrate without an interposed PN junction is not possible. Contact can be readily made however to ~-the body 12 at the back side of the wafer ~not shown).
~ It is possible to fabricate devices designed for the four photomask technology described here using a more conventional process using five photomasking steps. In the five photomask process, the well region 36 is created in the ~ ~ ;
conventional manner prior to the first step in the sequence described above. The N+ type regions 38-and 40 are then defined in a photomasking step at the appropriate time in the . , process by using a mask designed to expose the area of the well region 36 as well as at least one additional area outside the well region 36, into which phosphorus diffusion may take place. The remainder of the fabrication sequence îs identical. Advantages of the five photomask process are -RcA 66,383 5'74~;3 that a high energy boron implant is not required, contact to the N type substrate can be made in the conventional manner via the additional N~ type area (not shown), and the N+ layer which need no longer be identical with the well diffusion can be used for channel stoppers, diffused power buses, etc.
FIGURE 11 illustrates by way of example, how transistors constructed with the structure and by the process described above c~n be interconnected to perform ~;~
certain logic functions. The structure shown in FIGURE 11 is a plan view of a portion of an integrated circuit device 74. The logic circuit arrangements are an inverter 75, located at the top of the figure~ a transmissiDn gate 76, located in the central portion of the figure, and a two `~
input NAND gate 78, located at the lower portion of the figure. `
The logic circuit arrangements shown in FIGURE 11 each include at least one N channel transistor and one P
channel transistor. In the embodiment shown, there is one P well region, made like the P well region 36, which lies ~ ~
within the boundaries of a guard gate 80 serving to isolate ~!
all the N channel transistors from all the P channel transistors. Visible ad~acent to the inside boundary of the guard gate 80 in FIGURE 11 is a P+ type region 82 similar to the P~ type region 50 of FIGURE 1. An N~ type source plane region 84 lies inside the P+ type region 82, ~ .
and both the P+ type region 82 and the N~ type region 84 are contacted by a ~conductor 85 adapted to be coupled to a s~urce of relatively low voltage, designated Vss. This ~CA 66,383 1(1S'7~3 1~
,~1 connection is also made to the P well of the device ~4 via the region 82.
Outside the boundaries of the guard gate 80 there is a P~ type source plane region 86. A conductor 88 is coupled to both the guard gate 80 and the source plane region 86 and may be connected to a terminal for providing a source of relatively high potential desi~nated VDD.
The inverter 75 comprises an N channel transistor 90 and a P channel transistor 92. The source of the N
channel transistor 90 is the N~ type source plane region 84.
The gate 94 of the transistor is a frame-like structure like the other frame-like structures. The drain of the transistor 90 is a region 96 of N+ type conductivity inside the gate 94. The source of the P channel transistor g2 is the P~ type source plane region 86. The transistor 92 has a gate 98, and a drain 99 of P+ type conductivity.
A conductor 100 interconnects the gate 94 and the gate 98 of the ~ransistors 90 and 92 respectively and may be connected to an input terminal labelled A. A conductor 102 interconnects the drain 9,6 and the drain 98 of the transistors 90 and 92 respectively and may be connected to an ~ ~ -output terminal labelled ~. The operation of the in~erter 75 is the same as the operation of known complementary metal-oxide-silicon (CMOS) inverters. ;
The transmission gate 76 comprises two transistors 104 and 106. An important feature of the present invention is that means are ccnveniently available in this technology to isolate the transistors 104 and 106 from the other transistors either in the N~ type source plane 84 or the P~
type source plane 86. This may be accomplished by surrounding -13~
. -. . . : , , . .
, , , RCA 66,383 ~0574~
I the transistor 104 by an isolating gate 108 and then pro-viding a conductor 109 which couples that gate 108 with the region 84 in order to maintain the region under the gate 108 in a permanently off condition. Consequently, there -is another region 110 of N+ type conductivity which results when the gate 108 is used and the region 110 constitutes the source region for the transistor 104. The gate of the transistor 104 is a gate 112 and the drain thereof is an -N+ type region 114 therewithin.
IO An isolating gate ~5 similar to the isolating ~ ;
gate 108 surrounds the transistor 106 and defines another l~'\
A P-~ type region ~, which constitutes the source of the transistor 106. The gate of the transistor 106 is a gate 118 and the drain of the transistor 106 is the P+ region 120 therewithin. A conductor 116 couples the guard gate 115 with the P+ type source plane 86 to maintain the area under the gate 115 in a permanently off condition.
A conductor 122 is coupled to the gate 112 of the ~
transistor 104 and may be connected to a terminal of the ; ;
device for providing on the gate 112 a control signal designated B. A conductor 124 is coupled to the gate 118 ~0~ , of the transistor 116 and is adapted to be connected to a terminal of the device for the application of a control ;
signal B having a polarity opposite to that of the control ~`
signal applied to the conductor 122. An input conductor 126 is coupled to the respective source regions 110 and 117. An ~ -output conductor 128 is connected to the respective drain regions 114 and 120. This cons~ruction operates as a complementary transmission gate in known manner similar to the operation of transmission gates in known CMOS structures.
The NAND gate 78 illustrates how transistors can i ;
.: ' .
RCA 66,383 l~)S7~3 1 be connected in series and in parallel in the present technology. The NAND gate 78 comprises two N channel transistors 130 and 132 having their source to drain conduction channels connected in series, as will appear hereinafter, and two P channel transistors 134 and 136, having their source to drain conduction channels connected in parallel. The source of the transistor 130 is the N+
type source plane 84. The gate of the transistor 130 is a structure 138, like the other frame-like structures, which surrounds a region 140 of N+ type conductivity. This latter region 140 is a common drain for the transistor 130 ~ ~ `
and source for the transistor 132. The transistor 132 has a gate 142 and a drain 144 constituted by an N+ type `
region within the gate 142. The transistor 134 has a source constituted by the P+ type source plane 86, a gate 146, and a P~ type drain region 148. Similarly, the transistor 136 has a source constituted by the P+ type source plane 86, a gate 150, and a P+ type drain region 152.
~ A conductor 154 connects the gate 138 of the transistor 130 with the gate 150 of the transistor 136 and may be connected to a terminal of the device designated by the letter C. A conductor 156 interconnects the drain 144 of the transistor 132, the drain 148 of the transistor 134 and the drain 152 of the transistor 136 and constitutes ~25 an output conductor for this NAND gate, labelled C-D. A
conductor 158 is connected to the gate 142 of the transistor 132 and to the gate 146 of the transistor 134 and may be connected to a terminal of the device labelled D.
In the operation of the NAND gate 78 7 if the potentials at terminals C and D are both high, that is at . .
..
, ~ . ; . . ~ :' ' RCA 66,383 ~;
1~5'~
1 VDD, the transistor 130 will be on, the transistor 132 will be on, and both the transistors 134 and 136 will be off.
In this case, the signal appearing on the output terminal C-D will be substantially equal to Vss. If both the terminals C and D are low, i.e. at Vss, the transistors 130 and 132 will be off~ while the transistors 134 and 136 will be on, in which case the output appearing at the terminal C D will be substantially equal to VDD. When C is high and -D is low, the transistor 130 will be on, the transistor 132 will be off. Under these conditions, the output at C-D will also be at the potential of VDD. If D is high and C is low ~he transistor 130 will be off and the transistor 132 will be on, the transistor 134 will be off and the transistor ~0 will be on, in which case the output at C D will also be at VDD. There is hence only one logic state in which the output at C D will be at Vss, that is, when both C and D
are at VDD, so that the structure performs the logic NAND
- function.
Other logic functions can be reali~ed in this ~0 technology and are not described here as their construction will be apparent to those of ordinary skill when provided with this disclosure. More transistors may be connected in series in the manner of the connection of transistors 130 and 132 by surrounding the gates of these transistors 2S with an additional gate, not shown, but there is a limit to this technique inasmuch as each transistor in the series is much wider than the transistor next within it ;~
and thus the transconductances of the se~eral transistors will be much different. In most circuits too wide a variation in the transconductances of the several '''` ~': "
RC~ 66,383 1 transistors therein is not desirable.
The structure and the method disclosed herein has several advantages over known CMOS technology. The device does not rely on guardbands for isolation of devices and therefore does not require the guardband spacings of prior devices, making it adaptable to circuit densities much higher than have been obtained in known CMOS devices heretofore. The construction of the transistors in the closed-geometry form has the benefit of providing improved transconductance-to-drain-capacitance ratios for the transistors, which makes them faster than known I~ devices.
Owing to the ground plane feature disclosed in FIGURE ll, source contact is not required for each transistor in a given integrated circuit device.
In the present novel process as few as four `
photomasks may be used to make any given device. This leads to lower cost and simpler fabrication thus raising yields and making fabrication of the devices more economical. ~
Yields are also improved by the fact that in the process ; ;
three diffusions are put in from one photomask alignment, ; -:;
that is, the alignment required to form the photoresist layer 70 ~FIGURE 8). This alignment is not a critical -alignment because the boundaries 72 of the photoresist ~
layer 70 may vary in location widely from device to device ~- , ;
without sacrificing performance or yield. The four mask ;
process does have the disadvantage pointed out above of making top substrate contact relatively difficult. However, the five mask technique does not possess this problem.
. .
. .
, : , . . . . . .
,., ': , ' , : "' .
FIGURE 4 is another cross-section taken along `
the line 4- 4 of FIGIJR~
FIGURE 5 is a partial cross-section taken along - 3~
; ~:
, .. -.. ~, . . . , ., . , . ..... ~ . . . .. . .
-- RCA 66,383 10~ l3 l the line 5-5 of FIGIJ~E l.
FIGURES 6-10 are a series of cross-sections illustrating various steps in the present novel method.
FIGURE 11 is a partial plan view of an integrated circuit device illustrating the manner in which N-channel and P-channel transistors may be combined to provide certain circuit functions.
A portion of an integrated device 10 of the complementary IGFET type having the features of the present invention is illustrated in FIGURE 1. The device 10 comprises a body 12 of semiconductive material such as silicon, which is initially of one type conductivity ~N type in this example) and which has a surface 14 (See FIGURES 2,3,4,and 5).
In this example, the body 12 is a bulk silicon body, but 15 other forms of semiconductor material may also be used. For ;
exampleg the body 12 may be an epitaxial layer on an insulating substrate,in the so-called silicon-on-sapphire technology.
Means including the body 12, that is, source, drain and channel regions in the body 12 and gate electrode means on the surface 14, define a P channel IGFET 16 and an N channel IGFET 18, together with means 20 for isolating the P channel transistor 16 from the N channel transistor 18.
These various means comprise a first frame-like structure 22, 25 hereafter called a guard gate, a second frame-like structure ~-24, and a third frame-like structure 26, each hereafter called an active gate. Each of these gate structures includes a layer 28 (FIGURES 2 to 5) of insulating material and a layer 30 of conductive material on the layer 28 of insulating material. Although the y -. . ..
RCA 66,383 ~35~
.
in any one gate structure are separa~e from the corresponding layers in each of the other frame-like structures, the same reference numeral is applied to each of ~he respective insulating and conductive layers for convenience.
Each of the gate structures 22, Z4 and 26 has a closed geometry. By this is meant that the gate structures have the configuration of a closed pattern which has an opening therein. While rectangular structures are shown, ; -any suitable topologically closed shape may be adopted. The rectangular shape i5 preferred, for its adaptability to ~ `
integrated circuit structures of relatively high packing density.
The guard gate 22 surrounds a first portion 32 of ;
the surface 14 and is surrounded by a second portion 34 of the surface 14. The active gate 24 is disposed on the ~ ~
first portion 32 of the surface 14 and the active gate 26 is `~ ~`
disposed on the second portion 34 of the surface 14. While -. ~ .
the active gate 24 is shown in FIGURE 1 as centered within the guard gate 22, this configuration is not required and in ~
fact9 the guard gate 22 may be much larger with respect to ~ -the active gate 24 than is shown, so that other frame-like ~-gate structures like the active gate 24 may be disposed on the first portion 32 of the surface 14. See FIGURE 11 for example, the structure of which will be described later.
A well region 36 of conductivity type opposite to that of the body 12, P type in this example, is in the body 12 adjacent to the first portion 32 of the surface 14 A region 38 of N~ type conductivity is within the P well region 36 adjacent to a part of the surface 14 which is surrounded by the active gate 24. Another region 40 of N~
,~
.
.. , . , . ~, . . .. .
.: . .: , - . . ., ~ , :
: . . . , .. .... , ,: .
RCA 66,383 ~(~574~;~
l type conductivity is within the P well region 36 adjacent to a part of the surface 14 which surrounds the active gate 24. The regions 38 and 40 define the ends of a channel zone 41 for the transistor 18.
A region 42 of P+ ~ype conductivity is in the body 12 adjacent to `a part of the surface 14 which is surrounded by ~he active gate 26, and another region 44 of P+ type conductivity is in the body 12 adjacent to a ;
part of the surface 14 which surrounds the active gate 26. .- `
The regions 42 and 44 define the ends of a channel zone 45 for the transistor 16.
Owing to ~he process which is used to make the ~ ~
device 10, which process involves se~f-aligned gate ~ `
techniques, each of the gate structures 22, 24 and 26 has an inner peripheral boundary and an outer peripheral boundary.
~or convenience, the outer peripheral boundaries of the gate structures are each designated by the reference numeral 46 and the inner peripheral ~4Dn~ari2s are desi~nated b~ the ~ ;:
reference numeral 48.Each of the regions 38, ~0, 42, and 44 has ~ .
. -aSurface-intercept boundary substantially contiguous with one or the other of an inner or an outer pe~ipheral boundary : ~.
of a gate structure.
Means including a part of the first portion 32 of the surface 14 is provided for establishing ohmic contact to the well region 36. In this example, this means includes a region 50 of P+ type conductivity, of doping density higheT
than the doping density in the well region 36. The region 50 lies adjacent to that part of the first portion 32 of ~he RCA 66,383 105~
1 surface 14 which lies between the guard gate 22 and the active gate 24. In this example, although not required, the region 50 surrounds the region 40.
An insulating coating 52 overlies substantially all o~ the surface of the device lO and has apertures 54 : ;~
therein for permitting contact to be made to the various regions and conductive layers. The layer 52 may be composed of, for example, a chemical vapor deposited glass.
A source-substrate conductor 56 has a portion -~ .
10 thereof extending through an opening 54 into contact with . ;~ :
both the P+ type region 50 and the N+ type region 40. A
.. ~ . , .
drain conductor 58 has a portion thereof extending through ~`
an opening 54 into contact with the region 38. A gate ,. . . .
conductor 60 extends through an opening 54 into contact with the conductive layer 30 of the active gate 24. A
drain conductor 62 extends into contact with the region 42 in the transistor 16. A gate conductor 64 extends into contact with the conductive layer 30 of the active gate 26, and a source conductor 66 extends into contact with the .`. ~-region 44.
The guard gate 22 provides a means for isolating the transistor 16 from the transistor 18. In the operation ~ .
of the device, this gate may be considered to be a ~ :
permanently-off gate and in order to produce the permanently- ~:~
off condition, means are provided for electri-cally coupling .
the layer of conductive material 30 in the guard gate 22 with the P+ type region 44. As shown in FIGURES 1 and 5 this latter means comprises a conductor 68 which extends through apertures 54 into contact with the guard gate 22 and the region 44.
, .. -- RCA 66,383 :
1(~574~3 ~:
I The several conductors shown in FIGURES 1 to 5 do not interconnect the transistors 16 and 18 together to perform any circuit function, inasmuch as the structure described here is generally applicable to many dif~erent circuit configurations. Modifications of the structure thus far described and examples of the ways in which the modified structures may be connected in certain circuit `
configurations will be described below with respect to FIGURE 11. Before that however, the present novel method will be described FIGURES 6 to 10 illustrate one embodiment of the present novel method. particularly the application of ,~
the method to a bulk semiconductor body. For convenience, the cross-sections of FIGURES 6 to 10 show only the -~
configuration in the plane o the cross-section. .
In this example, the process begins with a semiconductor body 12 of silicon of N type conductivity which has a surface 14. The first step in the present process is to grow the insulating layer 28 on the surface 14.
Preferably, this step is accomplished by heating the body 12 to a temperature of about 875C in an atmosphere of steam and a small quantity of HCl gas for a time sufficient - O .
to grow the layer Z8 to a thickness of approximatel~ l,OO~A.
After the completion of the grow~h of the ~-insulating layer 28, the body 12 is placed in a deposition reactor and the layer 30 of conductive materlal, preferabl~
polycrystalline silicon, is deposited thereon. Any~ kno~n deposition reaction ma~ be emplored, preera~1y the thermal -decomposition reaction of silane ~SiH4) The process is ~` -carried out for a time sufficient to grow the la~er 30 to a ~8-.... .. .... .
RCA 66,383 ~0S741~3 l thickness of approximately 3000A. Using conventional : ~;
photolithographic technology involving a first photomask ~not shown) the layer 30 is next defined into the pattern of ~.
the frame-like gate structures 22, 24, and 26. See FIGURE 7.
The next step is to deposit a layer 70 of photoresist (FIGURE 8) on the upper surface of the body 12 and to define this layer of photoresist, using a second ~:
photomask, into the pattern which defines the boundaries ~ -of the P well 36. Note that the boundaries 72 of the .
10 photoresist layer 70 lie well inside the inner edge of the ~ :
layer 48 in the guard gate 22. The reason ~or this will be `~
made clear in the description of the succeeding steps. ~ . :
With the layer 70 of photoresist in place, the :~
body 12 is placed in an ion implantation machine and boron 15 is implanted at sufficiently high energy so that it :
penetrates both the polycrystalline material 30 of the active gate 24 and the gate oxide layer 28. The ion implantation is schematicall~ shown by a series of arrows in FIGURE 8, and the result of the implantation is a ~ .
20 region 36S in the body 12 beneath the active gate 24 and beneath a part of the surface 14 which surrounds *he active gate 24 and another part which is surrounded b~ the active .
gate 24, The photoresist coati~g is left in place after the `~
25 ion implantation step and the wafer is next placed in a ..
solvent for silicon dioxide such as buffered HF in order to ~: :
remove those porkions of the layer 28 which are not covered by either the photoresist or the polycrystalline silicon 3~
of the active gate 24. The result of this step, after the ~ ;
su~sequent removal of the photoresist, is shown in FIGURE 9, :
g RCA 66,383 ~(~5 ~
1 which also illustrates the next step in the process.
After the removal of the photoresist layer 70 the next step is ~o redistribute the conductivity modifiers in the regions 36S to form the P well region 36, by heating the device to a temperature of about 1200C for about 20 hours After the completion of the drive-in diffusion of the P well 36, the next step in the process is to diffuse phosphorus into the body 12 through the unmasked areas thereof as shown in FIGURE 9 to form the N+ type regions 38 and 40. This step is conventionall~ performed and results also in the diffusion of phosphorus into the polycrystalline silicon material of the conductive layer 30.
Without employing an additional photomask at `-~
this point, the device 10 is contacted ~ith a solvent for silicon dioxide to remove those remaining portions of t~e layer 28 which are not covered by the pol~crystalline ;~
silicon material of the several gate structures. This ste therefore completes the fabrication of the gates Z2, 24 and 26.
The next step is to difuse ~oron, b~ conven~ional processes~ into the uncovered portions. of the surface 14.
The result of this step is illustrated in FIGURE 10. After t~e boron diffusion, P+ type regions 42~ 44 and 50 are present. Boron will also be diffused into portions of the N+ type region 40, which are also exposed during this step, and the concentration of modifiers in the region 40 should ~
be sufficiently high, i.e. about 1021 atom/cm3, so that the ` ~ ~ -material thereof is not reconY~rted to P type by this boron -diffusion.
-10- `
RCA 66,383 ' ~
1(~5 7 ~ ~ ~
1 The next step is to deposit the glass coating 52.
This may be accomplished in any desired manner and preferably is done by chemical vapor deposition processes.
The final steps in the method are conventional,involving the use of a third and a fourth photomask. The third photomask is used to define the locations of the apertures 54 in the glass coating 52. After that definition step, a continuous layer of aluminum is deposited on the surface and the fourth photomask is used to define the various conductors 56, 58 etc. The fabrication of the device is then complete.
As a result of this processing, the establishing of contact from the top side of the device to the material ~
of the body 12 is difficult. This is so because all N~ ~ ;
l5 type diffusions are surrounded by a P well and consequently ~;
contact to the substrate without an interposed PN junction is not possible. Contact can be readily made however to ~-the body 12 at the back side of the wafer ~not shown).
~ It is possible to fabricate devices designed for the four photomask technology described here using a more conventional process using five photomasking steps. In the five photomask process, the well region 36 is created in the ~ ~ ;
conventional manner prior to the first step in the sequence described above. The N+ type regions 38-and 40 are then defined in a photomasking step at the appropriate time in the . , process by using a mask designed to expose the area of the well region 36 as well as at least one additional area outside the well region 36, into which phosphorus diffusion may take place. The remainder of the fabrication sequence îs identical. Advantages of the five photomask process are -RcA 66,383 5'74~;3 that a high energy boron implant is not required, contact to the N type substrate can be made in the conventional manner via the additional N~ type area (not shown), and the N+ layer which need no longer be identical with the well diffusion can be used for channel stoppers, diffused power buses, etc.
FIGURE 11 illustrates by way of example, how transistors constructed with the structure and by the process described above c~n be interconnected to perform ~;~
certain logic functions. The structure shown in FIGURE 11 is a plan view of a portion of an integrated circuit device 74. The logic circuit arrangements are an inverter 75, located at the top of the figure~ a transmissiDn gate 76, located in the central portion of the figure, and a two `~
input NAND gate 78, located at the lower portion of the figure. `
The logic circuit arrangements shown in FIGURE 11 each include at least one N channel transistor and one P
channel transistor. In the embodiment shown, there is one P well region, made like the P well region 36, which lies ~ ~
within the boundaries of a guard gate 80 serving to isolate ~!
all the N channel transistors from all the P channel transistors. Visible ad~acent to the inside boundary of the guard gate 80 in FIGURE 11 is a P+ type region 82 similar to the P~ type region 50 of FIGURE 1. An N~ type source plane region 84 lies inside the P+ type region 82, ~ .
and both the P+ type region 82 and the N~ type region 84 are contacted by a ~conductor 85 adapted to be coupled to a s~urce of relatively low voltage, designated Vss. This ~CA 66,383 1(1S'7~3 1~
,~1 connection is also made to the P well of the device ~4 via the region 82.
Outside the boundaries of the guard gate 80 there is a P~ type source plane region 86. A conductor 88 is coupled to both the guard gate 80 and the source plane region 86 and may be connected to a terminal for providing a source of relatively high potential desi~nated VDD.
The inverter 75 comprises an N channel transistor 90 and a P channel transistor 92. The source of the N
channel transistor 90 is the N~ type source plane region 84.
The gate 94 of the transistor is a frame-like structure like the other frame-like structures. The drain of the transistor 90 is a region 96 of N+ type conductivity inside the gate 94. The source of the P channel transistor g2 is the P~ type source plane region 86. The transistor 92 has a gate 98, and a drain 99 of P+ type conductivity.
A conductor 100 interconnects the gate 94 and the gate 98 of the ~ransistors 90 and 92 respectively and may be connected to an input terminal labelled A. A conductor 102 interconnects the drain 9,6 and the drain 98 of the transistors 90 and 92 respectively and may be connected to an ~ ~ -output terminal labelled ~. The operation of the in~erter 75 is the same as the operation of known complementary metal-oxide-silicon (CMOS) inverters. ;
The transmission gate 76 comprises two transistors 104 and 106. An important feature of the present invention is that means are ccnveniently available in this technology to isolate the transistors 104 and 106 from the other transistors either in the N~ type source plane 84 or the P~
type source plane 86. This may be accomplished by surrounding -13~
. -. . . : , , . .
, , , RCA 66,383 ~0574~
I the transistor 104 by an isolating gate 108 and then pro-viding a conductor 109 which couples that gate 108 with the region 84 in order to maintain the region under the gate 108 in a permanently off condition. Consequently, there -is another region 110 of N+ type conductivity which results when the gate 108 is used and the region 110 constitutes the source region for the transistor 104. The gate of the transistor 104 is a gate 112 and the drain thereof is an -N+ type region 114 therewithin.
IO An isolating gate ~5 similar to the isolating ~ ;
gate 108 surrounds the transistor 106 and defines another l~'\
A P-~ type region ~, which constitutes the source of the transistor 106. The gate of the transistor 106 is a gate 118 and the drain of the transistor 106 is the P+ region 120 therewithin. A conductor 116 couples the guard gate 115 with the P+ type source plane 86 to maintain the area under the gate 115 in a permanently off condition.
A conductor 122 is coupled to the gate 112 of the ~
transistor 104 and may be connected to a terminal of the ; ;
device for providing on the gate 112 a control signal designated B. A conductor 124 is coupled to the gate 118 ~0~ , of the transistor 116 and is adapted to be connected to a terminal of the device for the application of a control ;
signal B having a polarity opposite to that of the control ~`
signal applied to the conductor 122. An input conductor 126 is coupled to the respective source regions 110 and 117. An ~ -output conductor 128 is connected to the respective drain regions 114 and 120. This cons~ruction operates as a complementary transmission gate in known manner similar to the operation of transmission gates in known CMOS structures.
The NAND gate 78 illustrates how transistors can i ;
.: ' .
RCA 66,383 l~)S7~3 1 be connected in series and in parallel in the present technology. The NAND gate 78 comprises two N channel transistors 130 and 132 having their source to drain conduction channels connected in series, as will appear hereinafter, and two P channel transistors 134 and 136, having their source to drain conduction channels connected in parallel. The source of the transistor 130 is the N+
type source plane 84. The gate of the transistor 130 is a structure 138, like the other frame-like structures, which surrounds a region 140 of N+ type conductivity. This latter region 140 is a common drain for the transistor 130 ~ ~ `
and source for the transistor 132. The transistor 132 has a gate 142 and a drain 144 constituted by an N+ type `
region within the gate 142. The transistor 134 has a source constituted by the P+ type source plane 86, a gate 146, and a P~ type drain region 148. Similarly, the transistor 136 has a source constituted by the P+ type source plane 86, a gate 150, and a P+ type drain region 152.
~ A conductor 154 connects the gate 138 of the transistor 130 with the gate 150 of the transistor 136 and may be connected to a terminal of the device designated by the letter C. A conductor 156 interconnects the drain 144 of the transistor 132, the drain 148 of the transistor 134 and the drain 152 of the transistor 136 and constitutes ~25 an output conductor for this NAND gate, labelled C-D. A
conductor 158 is connected to the gate 142 of the transistor 132 and to the gate 146 of the transistor 134 and may be connected to a terminal of the device labelled D.
In the operation of the NAND gate 78 7 if the potentials at terminals C and D are both high, that is at . .
..
, ~ . ; . . ~ :' ' RCA 66,383 ~;
1~5'~
1 VDD, the transistor 130 will be on, the transistor 132 will be on, and both the transistors 134 and 136 will be off.
In this case, the signal appearing on the output terminal C-D will be substantially equal to Vss. If both the terminals C and D are low, i.e. at Vss, the transistors 130 and 132 will be off~ while the transistors 134 and 136 will be on, in which case the output appearing at the terminal C D will be substantially equal to VDD. When C is high and -D is low, the transistor 130 will be on, the transistor 132 will be off. Under these conditions, the output at C-D will also be at the potential of VDD. If D is high and C is low ~he transistor 130 will be off and the transistor 132 will be on, the transistor 134 will be off and the transistor ~0 will be on, in which case the output at C D will also be at VDD. There is hence only one logic state in which the output at C D will be at Vss, that is, when both C and D
are at VDD, so that the structure performs the logic NAND
- function.
Other logic functions can be reali~ed in this ~0 technology and are not described here as their construction will be apparent to those of ordinary skill when provided with this disclosure. More transistors may be connected in series in the manner of the connection of transistors 130 and 132 by surrounding the gates of these transistors 2S with an additional gate, not shown, but there is a limit to this technique inasmuch as each transistor in the series is much wider than the transistor next within it ;~
and thus the transconductances of the se~eral transistors will be much different. In most circuits too wide a variation in the transconductances of the several '''` ~': "
RC~ 66,383 1 transistors therein is not desirable.
The structure and the method disclosed herein has several advantages over known CMOS technology. The device does not rely on guardbands for isolation of devices and therefore does not require the guardband spacings of prior devices, making it adaptable to circuit densities much higher than have been obtained in known CMOS devices heretofore. The construction of the transistors in the closed-geometry form has the benefit of providing improved transconductance-to-drain-capacitance ratios for the transistors, which makes them faster than known I~ devices.
Owing to the ground plane feature disclosed in FIGURE ll, source contact is not required for each transistor in a given integrated circuit device.
In the present novel process as few as four `
photomasks may be used to make any given device. This leads to lower cost and simpler fabrication thus raising yields and making fabrication of the devices more economical. ~
Yields are also improved by the fact that in the process ; ;
three diffusions are put in from one photomask alignment, ; -:;
that is, the alignment required to form the photoresist layer 70 ~FIGURE 8). This alignment is not a critical -alignment because the boundaries 72 of the photoresist ~
layer 70 may vary in location widely from device to device ~- , ;
without sacrificing performance or yield. The four mask ;
process does have the disadvantage pointed out above of making top substrate contact relatively difficult. However, the five mask technique does not possess this problem.
. .
. .
, : , . . . . . .
,., ': , ' , : "' .
Claims (15)
- Claim 1 continued a region of the same type conductivity as said body within said well region adjacent to a part of said surface which surrounds said second frame-like structure;
a region of said opposite type conductivity adjacent to a part of said surface which is surrounded by said third frame-like structure; and a region of said opposite type conductivity adjacent to a part of said surface which surrounds said third frame-like structure. - 2. An integrated circuit device as defined in Claim 1 wherein said means making ohmic contact to said well region includes a region of said opposite type conduc-tivity of higher doping density than said well region, adjacent to a part of said first portion of said surface which lies between said first frame-like structure and said second frame-like structure.
- 3. An integrated circuit device as defined in Claim 2 wherein said region of higher doping density, opposite conductivity type material immediately surrounds that region of the same type conductivity as said body within said well region which surrounds said second frame-like structure.
- 4. An integrated circuit device as defined in Claim 3 wherein each of said frame-like structures has an inner peripheral boundary and an outer peripheral boundary, said region of higher doping density, opposite conductivity type material having a surface intercept boundary substantially contiguous with the inner peripheral boundary of said first frame-like structure.
- 5. An integrated circuit device as defined in Claim 4 wherein each of said regions of the same and the opposite type conductivity has a surface intercept boundary substantially contiguous with at least the inner or the outer peripheral boundary of a frame-like structure.
- 6. An integrated circuit device as defined in Claim 1 wherein said region of said opposite type conductivity which surrounds solid third frame-like structure also surrounds said first frame-like structure.
- 7. An integrated circuit device as defined in Claim 6 further comprising means electrically coupling the layer of conductive material in said first frame-like structure with said region of opposite type conductivity which surrounds said first and said third frame-like structures.
- 8. An integrated circuit device as defined in Claim 1 further comprising a fourth frame-like structure like said first, second, and third frame-like structures disposed on said first portion of said surface.
- 9. An integrated circuit device as defined in Claim 7 wherein said fourth frame-like structure surrounds said second frame-like structure.
- 10. An integrated circuit device as defined in Claim 8 further comprising a fifth frame-like structure like the other frame-like structures disposed on said second portion of said surface.
- 11. An integrated circuit device as defined in Claim 10 wherein said fifth frame-like structure surrounds said third frame-like structure.
12. A method of making a semiconductor integrated circuit device from a body of semiconductive material of predominantly one type conductivity having a surface, comprising the steps of:
forming a continuous first film of insulating material on said surface;
forming a continuous second film of a conductive material on said film of insulating material;
removing portions of said second film to define a pattern therein, said pattern including at least a first frame-like configuration, a second frame-like configuration wholly with said first frame-like configuration, and a third frame-like configuration wholly outside said first frame-like configuration;
forming a masking coating of a material which is impervious to conductivity modifiers on said body, said coating having a pattern therein which exposes only said second frame-like configuration, the area of said first film therewithin, and a portion of the area of said first film inside said first frame-like configuration and outside and surrounding said second frame-like configuration;
introducing opposite type conductivity modifiers into said body to form a continuous region of opposite type conductivity beneath at least the portions of said first film which are exposed by said masking coating and beneath said second frame-like configuration;
removing the exposed portions of said first film;
removing said masking coating;
introducing conductivity modifiers of said one type into said body to form regions of said one type - Claim 12 continued conductivity adjacent to portions of said surface which lie inside and outside said second frame-like configuration;
removing all the remaining portions of said first film except those lying beneath said first, second and third frame-like configurations; and introducing conductivity modifiers of said opposite type into those portions of said body adjacent to the surface portions thereof which are not covered by said first, second and third frame-like configurations. - 13. A method as defined in Claim 12 wherein said continuous region of opposite type conduc-tivity is formed after the formation of said masking coating by ion implanting conductivity modifiers of said opposite type into said body at an energy insufficient to penetrate said masking coating but sufficient to penetrate said first film and the combination of said second film and said first film.
- 14. A method as defined in Claim 12 wherein said step of introducing conductivity modifiers of said one type into said body to form said regions of one type conductivity comprises diffusing said modifiers into said body through said surface portions inside and outside said frame-like configuration.
- 15. A method as defined in Claim 14 wherein said one-type conductivity is N type, said conductivity modifiers are phosphorus atoms, the concentration of phosphorus in said regions of said one type conductivity being greater than about 1021 atoms/cm3, and said step of introducing conductivity modifiers of said opposite type into those portions of said body adjacent to the surface portions thereof which are not covered by said first, second, and third frame-like configuration comprises diffusing boron into said body to a concentration insufficient to reconvert said regions of one type conduc-tivity to P type.
1. An integrated circuit device comprising a body of semiconductive material, predominantly of one type conductivity, having a surface, means including said body defining at least a P channel insulated gate field effect transistor and an N channel insulated gate field effect transistor, and means for isolating said P channel IGFET
from said N channel IGFET, said device comprising:
first, second, and third frame-like structures, each including a layer of insulating material on said surface and a layer of conductive material on said layer of insulating material, said first frame-like structure having a closed geometry surrounding a first portion of said surface and being surrounded by a second portion of said surface, said second frame-like structure also having a closed geometry and being disposed on said first portion of said surface, and said third frame-like structure having a closed geometry and being disposed on said second-portion of said surface;
a well region of conductivity type opposite to that of said body in said body adjacent to said first portion of said surface;
means including a part of said first portion of said surface for making ohmic contact to said well region;
a region of the same type conductivity as said body within said well region adjacent to a part of said surface which is surrounded by said second frame-like structure;
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US58587475A | 1975-06-11 | 1975-06-11 |
Publications (1)
Publication Number | Publication Date |
---|---|
CA1057413A true CA1057413A (en) | 1979-06-26 |
Family
ID=24343323
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA253,457A Expired CA1057413A (en) | 1975-06-11 | 1976-05-27 | Integrated circuit device including both n-channel and p-channel insulated gate field effect transistors |
Country Status (15)
Country | Link |
---|---|
JP (1) | JPS5234677A (en) |
AU (1) | AU497683B2 (en) |
BE (1) | BE842774A (en) |
BR (1) | BR7603615A (en) |
CA (1) | CA1057413A (en) |
CH (1) | CH620049A5 (en) |
DE (1) | DE2625576A1 (en) |
FR (1) | FR2314583A1 (en) |
GB (1) | GB1526503A (en) |
HU (1) | HU175524B (en) |
IN (1) | IN144541B (en) |
IT (1) | IT1079501B (en) |
NL (1) | NL7606272A (en) |
SE (1) | SE416599B (en) |
YU (1) | YU139376A (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4081896A (en) * | 1977-04-11 | 1978-04-04 | Rca Corporation | Method of making a substrate contact for an integrated circuit |
CA1188821A (en) * | 1982-09-03 | 1985-06-11 | Patrick W. Clarke | Power mosfet integrated circuit |
US4860080A (en) * | 1987-03-31 | 1989-08-22 | General Electric Company | Isolation for transistor devices having a pilot structure |
JPH02168666A (en) * | 1988-09-29 | 1990-06-28 | Mitsubishi Electric Corp | Complementary semiconductor device and manufacture thereof |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL6904543A (en) * | 1969-03-25 | 1970-09-29 | ||
US3660735A (en) * | 1969-09-10 | 1972-05-02 | Sprague Electric Co | Complementary metal insulator silicon transistor pairs |
US3608189A (en) * | 1970-01-07 | 1971-09-28 | Gen Electric | Method of making complementary field-effect transistors by single step diffusion |
US3868721A (en) * | 1970-11-02 | 1975-02-25 | Motorola Inc | Diffusion guarded metal-oxide-silicon field effect transistors |
FR2129827B1 (en) * | 1971-03-15 | 1976-09-03 | Gen Electric | |
US3712995A (en) * | 1972-03-27 | 1973-01-23 | Rca Corp | Input transient protection for complementary insulated gate field effect transistor integrated circuit device |
JPS5535869B2 (en) * | 1972-05-15 | 1980-09-17 | ||
JPS4921080A (en) * | 1972-06-15 | 1974-02-25 |
-
1976
- 1976-04-19 IN IN664/CAL/1976A patent/IN144541B/en unknown
- 1976-05-14 IT IT23310/76A patent/IT1079501B/en active
- 1976-05-27 CA CA253,457A patent/CA1057413A/en not_active Expired
- 1976-06-03 GB GB22962/76A patent/GB1526503A/en not_active Expired
- 1976-06-04 SE SE7606368A patent/SE416599B/en unknown
- 1976-06-05 DE DE19762625576 patent/DE2625576A1/en not_active Withdrawn
- 1976-06-07 AU AU14675/76A patent/AU497683B2/en not_active Expired
- 1976-06-07 YU YU01393/76A patent/YU139376A/en unknown
- 1976-06-07 BR BR7603615A patent/BR7603615A/en unknown
- 1976-06-09 CH CH730976A patent/CH620049A5/en not_active IP Right Cessation
- 1976-06-09 BE BE7000833A patent/BE842774A/en unknown
- 1976-06-10 JP JP51068632A patent/JPS5234677A/en active Granted
- 1976-06-10 FR FR7617582A patent/FR2314583A1/en active Granted
- 1976-06-10 HU HU76RA647A patent/HU175524B/en unknown
- 1976-06-10 NL NL7606272A patent/NL7606272A/en not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
AU1467576A (en) | 1977-12-15 |
FR2314583A1 (en) | 1977-01-07 |
IN144541B (en) | 1978-05-13 |
FR2314583B1 (en) | 1982-09-17 |
JPS5234677A (en) | 1977-03-16 |
IT1079501B (en) | 1985-05-13 |
BE842774A (en) | 1976-10-01 |
CH620049A5 (en) | 1980-10-31 |
AU497683B2 (en) | 1978-12-21 |
YU139376A (en) | 1983-04-27 |
HU175524B (en) | 1980-08-28 |
BR7603615A (en) | 1977-02-01 |
DE2625576A1 (en) | 1976-12-30 |
SE7606368L (en) | 1976-12-12 |
NL7606272A (en) | 1976-12-14 |
JPS574105B2 (en) | 1982-01-25 |
SE416599B (en) | 1981-01-19 |
GB1526503A (en) | 1978-09-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4435895A (en) | Process for forming complementary integrated circuit devices | |
USRE31079E (en) | Method for manufacturing complementary insulated gate field effect transistors | |
US5972741A (en) | Method of manufacturing semiconductor device | |
US4282648A (en) | CMOS process | |
US4240093A (en) | Integrated circuit device including both N-channel and P-channel insulated gate field effect transistors | |
US4385947A (en) | Method for fabricating CMOS in P substrate with single guard ring using local oxidation | |
US4135955A (en) | Process for fabricating high voltage cmos with self-aligned guard rings utilizing selective diffusion and local oxidation | |
US5970338A (en) | Method of producing an EEPROM semiconductor structure | |
US4455737A (en) | Process for and structure of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines | |
US3996655A (en) | Processes of forming insulated gate field effect transistors with channel lengths of one micron in integrated circuits with component isolated and product | |
US4506437A (en) | Process for and structure of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines | |
JPH0691201B2 (en) | Method for manufacturing CMOS semiconductor device | |
US4277881A (en) | Process for fabrication of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines | |
US4406049A (en) | Very high density cells comprising a ROM and method of manufacturing same | |
EP0545082B1 (en) | Process for manufacturing MOS-type integrated circuits comprising LOCOS isolation regions | |
US3747200A (en) | Integrated circuit fabrication method | |
US6656803B2 (en) | Radiation hardened semiconductor memory | |
US4229756A (en) | Ultra high speed complementary MOS device | |
EP0135243B1 (en) | A method of producing a semiconductor structure on a substrate and a semiconductor device manufactured thereby | |
US4477962A (en) | Process for and structure of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines | |
JPH10214907A (en) | Semiconductor device and its manufacture | |
US5031019A (en) | Method for manufacturing a semiconductor device having isolated islands and its resulting structure | |
US5005066A (en) | Self-aligned NPN bipolar transistor built in a double polysilicon CMOS technology | |
US4550490A (en) | Monolithic integrated circuit | |
US4159561A (en) | Method of making a substrate contact for an integrated circuit |