CH581885A5 - - Google Patents

Info

Publication number
CH581885A5
CH581885A5 CH657875A CH657875A CH581885A5 CH 581885 A5 CH581885 A5 CH 581885A5 CH 657875 A CH657875 A CH 657875A CH 657875 A CH657875 A CH 657875A CH 581885 A5 CH581885 A5 CH 581885A5
Authority
CH
Switzerland
Application number
CH657875A
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of CH581885A5 publication Critical patent/CH581885A5/xx

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
    • H10D84/813—Combinations of field-effect devices and capacitor only

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
CH657875A 1974-06-28 1975-05-22 CH581885A5 (is")

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2431079A DE2431079C3 (de) 1974-06-28 1974-06-28 Dynamischer Halbleiterspeicher mit Zwei-Transistor-Speicherelementen

Publications (1)

Publication Number Publication Date
CH581885A5 true CH581885A5 (is") 1976-11-15

Family

ID=5919184

Family Applications (1)

Application Number Title Priority Date Filing Date
CH657875A CH581885A5 (is") 1974-06-28 1975-05-22

Country Status (6)

Country Link
JP (1) JPS5428252B2 (is")
CH (1) CH581885A5 (is")
DE (1) DE2431079C3 (is")
FR (1) FR2276659A1 (is")
GB (1) GB1502334A (is")
IT (1) IT1038100B (is")

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5853512B2 (ja) * 1976-02-13 1983-11-29 株式会社東芝 半導体記憶装置の製造方法
JPS5922316B2 (ja) * 1976-02-24 1984-05-25 株式会社東芝 ダイナミツクメモリ装置
US4040016A (en) * 1976-03-31 1977-08-02 International Business Machines Corporation Twin nodes capacitance memory
US4103342A (en) * 1976-06-17 1978-07-25 International Business Machines Corporation Two-device memory cell with single floating capacitor
CA1164710A (en) * 1978-05-09 1984-04-03 Edward J. Reardon, Jr. Phototropic photosensitive compositions containing fluoran colorformer
DE2837877C2 (de) * 1978-08-30 1987-04-23 Siemens AG, 1000 Berlin und 8000 München Verfahren zur Herstellung eines MOS-integrierten Halbleiterspeichers
DE2855118C2 (de) * 1978-12-20 1981-03-26 IBM Deutschland GmbH, 70569 Stuttgart Dynamischer FET-Speicher
EP0078338B1 (de) * 1981-10-30 1986-02-05 Ibm Deutschland Gmbh FET-Speicher
JP5034133B2 (ja) 2000-02-29 2012-09-26 富士通セミコンダクター株式会社 半導体記憶装置
JP4707244B2 (ja) * 2000-03-30 2011-06-22 ルネサスエレクトロニクス株式会社 半導体記憶装置および半導体装置
TWI359422B (en) 2008-04-15 2012-03-01 Faraday Tech Corp 2t sram and associated cell structure

Also Published As

Publication number Publication date
FR2276659B1 (is") 1980-01-04
JPS5428252B2 (is") 1979-09-14
DE2431079C3 (de) 1979-12-13
IT1038100B (it) 1979-11-20
FR2276659A1 (fr) 1976-01-23
DE2431079B2 (de) 1979-04-26
GB1502334A (en) 1978-03-01
DE2431079A1 (de) 1976-02-12
JPS513824A (is") 1976-01-13

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Legal Events

Date Code Title Description
PL Patent ceased
PL Patent ceased