CH490737A - Method for manufacturing a semiconductor device - Google Patents
Method for manufacturing a semiconductor deviceInfo
- Publication number
- CH490737A CH490737A CH622669A CH622669A CH490737A CH 490737 A CH490737 A CH 490737A CH 622669 A CH622669 A CH 622669A CH 622669 A CH622669 A CH 622669A CH 490737 A CH490737 A CH 490737A
- Authority
- CH
- Switzerland
- Prior art keywords
- manufacturing
- semiconductor device
- semiconductor
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19681769271 DE1769271C3 (en) | 1968-04-27 | 1968-04-27 | Method of manufacturing a solid-state circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
CH490737A true CH490737A (en) | 1970-05-15 |
Family
ID=5700073
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CH622669A CH490737A (en) | 1968-04-27 | 1969-04-24 | Method for manufacturing a semiconductor device |
Country Status (4)
Country | Link |
---|---|
CH (1) | CH490737A (en) |
DE (1) | DE1769271C3 (en) |
FR (1) | FR2007542A1 (en) |
GB (1) | GB1231543A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2383521A1 (en) * | 1977-03-12 | 1978-10-06 | Itt | Monolithic semiconductor circuit with bipolar analogs - has additional epitaxially grown layer of higher impurity concentration penetrated during mfg. processes |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2608267A1 (en) * | 1976-02-28 | 1977-09-08 | Itt Ind Gmbh Deutsche | METHOD OF MANUFACTURING A MONOLITHIC INTEGRATED CIRCUIT |
US4132573A (en) * | 1977-02-08 | 1979-01-02 | Murata Manufacturing Co., Ltd. | Method of manufacturing a monolithic integrated circuit utilizing epitaxial deposition and simultaneous outdiffusion |
-
1968
- 1968-04-27 DE DE19681769271 patent/DE1769271C3/en not_active Expired
-
1969
- 1969-04-24 GB GB1231543D patent/GB1231543A/en not_active Expired
- 1969-04-24 CH CH622669A patent/CH490737A/en not_active IP Right Cessation
- 1969-04-25 FR FR6913186A patent/FR2007542A1/fr not_active Withdrawn
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2383521A1 (en) * | 1977-03-12 | 1978-10-06 | Itt | Monolithic semiconductor circuit with bipolar analogs - has additional epitaxially grown layer of higher impurity concentration penetrated during mfg. processes |
Also Published As
Publication number | Publication date |
---|---|
DE1769271C3 (en) | 1975-04-30 |
DE1769271B2 (en) | 1973-11-22 |
FR2007542A1 (en) | 1970-01-09 |
DE1769271A1 (en) | 1970-12-17 |
GB1231543A (en) | 1971-05-12 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PL | Patent ceased |