CH438494A - Verfahren zur Montage von Halbleiterplättchen - Google Patents

Verfahren zur Montage von Halbleiterplättchen

Info

Publication number
CH438494A
CH438494A CH1273265A CH1273265A CH438494A CH 438494 A CH438494 A CH 438494A CH 1273265 A CH1273265 A CH 1273265A CH 1273265 A CH1273265 A CH 1273265A CH 438494 A CH438494 A CH 438494A
Authority
CH
Switzerland
Prior art keywords
semiconductor wafers
assembling semiconductor
assembling
wafers
semiconductor
Prior art date
Application number
CH1273265A
Other languages
English (en)
Inventor
Leonard King Geoffrey Arthur
Original Assignee
Itt
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Itt filed Critical Itt
Publication of CH438494A publication Critical patent/CH438494A/de

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09736—Varying thickness of a single conductor; Conductors in the same plane having different thicknesses
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10166—Transistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0369—Etching selective parts of a metal substrate through part of its thickness, e.g. using etch resist
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
CH1273265A 1964-09-15 1965-09-14 Verfahren zur Montage von Halbleiterplättchen CH438494A (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB37615/64A GB1062928A (en) 1964-09-15 1964-09-15 Multi-wafer integrated circuits

Publications (1)

Publication Number Publication Date
CH438494A true CH438494A (de) 1967-06-30

Family

ID=10397756

Family Applications (1)

Application Number Title Priority Date Filing Date
CH1273265A CH438494A (de) 1964-09-15 1965-09-14 Verfahren zur Montage von Halbleiterplättchen

Country Status (5)

Country Link
BE (1) BE669627A (de)
CH (1) CH438494A (de)
DE (1) DE1240961B (de)
GB (1) GB1062928A (de)
NL (1) NL6511689A (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1591580B1 (de) * 1967-10-11 1971-02-04 Siemens Ag Verfahren zum gleichzeitigen Anbringen mehrerer elektrischer Anschlusselemente an Kontaktpunkten von Duennschichtbauelementen der Nachrichtentechnik
US3698073A (en) * 1970-10-13 1972-10-17 Motorola Inc Contact bonding and packaging of integrated circuits
DE3029939A1 (de) * 1980-08-07 1982-03-25 GAO Gesellschaft für Automation und Organisation mbH, 8000 München Ausweiskarte mit ic-baustein und verfahren zu ihrer herstellung
JP3365048B2 (ja) * 1994-05-06 2003-01-08 ソニー株式会社 チップ部品の実装基板およびチップ部品の実装方法

Also Published As

Publication number Publication date
GB1062928A (en) 1967-03-22
BE669627A (de) 1966-03-15
NL6511689A (de) 1966-03-16
DE1240961B (de) 1967-05-24

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