CH397878A - Verfahren zur Herstellung von Halbleiteranordnungen - Google Patents
Verfahren zur Herstellung von HalbleiteranordnungenInfo
- Publication number
- CH397878A CH397878A CH28962A CH28962A CH397878A CH 397878 A CH397878 A CH 397878A CH 28962 A CH28962 A CH 28962A CH 28962 A CH28962 A CH 28962A CH 397878 A CH397878 A CH 397878A
- Authority
- CH
- Switzerland
- Prior art keywords
- production
- semiconductor devices
- semiconductor
- devices
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Weting (AREA)
- Thyristors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DEB60834A DE1154871B (de) | 1961-01-13 | 1961-01-13 | Verfahren zum Herstellen von Halbleiterbauelementen mit wenigstens einem pn-UEbergang |
Publications (1)
Publication Number | Publication Date |
---|---|
CH397878A true CH397878A (de) | 1965-08-31 |
Family
ID=6972991
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CH28962A CH397878A (de) | 1961-01-13 | 1962-01-11 | Verfahren zur Herstellung von Halbleiteranordnungen |
Country Status (3)
Country | Link |
---|---|
CH (1) | CH397878A (de) |
DE (1) | DE1154871B (de) |
GB (1) | GB968230A (de) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3268309A (en) * | 1964-03-30 | 1966-08-23 | Gen Electric | Semiconductor contact means |
US3368120A (en) * | 1965-03-22 | 1968-02-06 | Gen Electric | Multilayer contact system for semiconductor devices |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL215949A (de) * | 1956-04-03 | |||
NL241982A (de) * | 1958-08-13 | 1900-01-01 | ||
FR1213751A (fr) * | 1958-10-27 | 1960-04-04 | Telecommunications Sa | Procédé de fabrication de transistrons à jonctions n-p-n obtenues par double diffusion |
FR1228285A (fr) * | 1959-03-11 | 1960-08-29 | Structures à semi-conducteurs pour amplificateur paramétrique à micro-ondes |
-
1961
- 1961-01-13 DE DEB60834A patent/DE1154871B/de active Pending
-
1962
- 1962-01-11 CH CH28962A patent/CH397878A/de unknown
- 1962-01-12 GB GB120862A patent/GB968230A/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
GB968230A (en) | 1964-09-02 |
DE1154871B (de) | 1963-09-26 |
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