CA967288A - Fabrication of monolithic integrated circuits using dielectric isolation - Google Patents

Fabrication of monolithic integrated circuits using dielectric isolation

Info

Publication number
CA967288A
CA967288A CA147,513A CA147513A CA967288A CA 967288 A CA967288 A CA 967288A CA 147513 A CA147513 A CA 147513A CA 967288 A CA967288 A CA 967288A
Authority
CA
Canada
Prior art keywords
fabrication
integrated circuits
monolithic integrated
dielectric isolation
dielectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA147,513A
Other languages
English (en)
Other versions
CA147513S (en
Inventor
Edward J. Boleky (Iii)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
RCA Corp
Original Assignee
RCA Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by RCA Corp filed Critical RCA Corp
Application granted granted Critical
Publication of CA967288A publication Critical patent/CA967288A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/764—Air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8221—Three dimensional integrated circuits stacked in different levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/86—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body the insulating body being sapphire, e.g. silicon on sapphire structure, i.e. SOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76289—Lateral isolation by air gap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/008—Bi-level fabrication
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/122—Polycrystalline
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/15—Silicon on sapphire SOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)
  • Thin Film Transistor (AREA)
CA147,513A 1971-10-21 1972-07-19 Fabrication of monolithic integrated circuits using dielectric isolation Expired CA967288A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US19145571A 1971-10-21 1971-10-21

Publications (1)

Publication Number Publication Date
CA967288A true CA967288A (en) 1975-05-06

Family

ID=22705564

Family Applications (1)

Application Number Title Priority Date Filing Date
CA147,513A Expired CA967288A (en) 1971-10-21 1972-07-19 Fabrication of monolithic integrated circuits using dielectric isolation

Country Status (12)

Country Link
US (1) US3791024A (ja)
JP (1) JPS5112992B2 (ja)
AU (1) AU462435B2 (ja)
BE (1) BE786089A (ja)
CA (1) CA967288A (ja)
DE (1) DE2235185A1 (ja)
ES (2) ES404273A1 (ja)
FR (1) FR2156543B1 (ja)
GB (1) GB1339095A (ja)
IT (1) IT956533B (ja)
NL (1) NL7209192A (ja)
SE (1) SE376327B (ja)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4074304A (en) * 1974-10-04 1978-02-14 Nippon Electric Company, Ltd. Semiconductor device having a miniature junction area and process for fabricating same
US4094057A (en) * 1976-03-29 1978-06-13 International Business Machines Corporation Field effect transistor lost film fabrication process
JPS5721856B2 (en) * 1977-11-28 1982-05-10 Nippon Telegraph & Telephone Semiconductor and its manufacture
US4199384A (en) * 1979-01-29 1980-04-22 Rca Corporation Method of making a planar semiconductor on insulating substrate device utilizing the deposition of a dual dielectric layer between device islands
JPH0628313B2 (ja) * 1982-01-19 1994-04-13 キヤノン株式会社 半導体素子
US4481707A (en) * 1983-02-24 1984-11-13 The United States Of America As Represented By The Secretary Of The Air Force Method for the fabrication of dielectric isolated junction field effect transistor and PNP transistor
JPS6072243A (ja) * 1983-09-28 1985-04-24 Matsushita Electric Ind Co Ltd 半導体集積回路装置
US4879585A (en) * 1984-03-31 1989-11-07 Kabushiki Kaisha Toshiba Semiconductor device
US4897698A (en) * 1984-10-31 1990-01-30 Texas Instruments Incorporated Horizontal structure thin film transistor
JPH01162376A (ja) * 1987-12-18 1989-06-26 Fujitsu Ltd 半導体装置の製造方法
US5525536A (en) * 1991-12-26 1996-06-11 Rohm Co., Ltd. Method for producing SOI substrate and semiconductor device using the same
US5952695A (en) * 1997-03-05 1999-09-14 International Business Machines Corporation Silicon-on-insulator and CMOS-on-SOI double film structures
US5889293A (en) * 1997-04-04 1999-03-30 International Business Machines Corporation Electrical contact to buried SOI structures
US5834350A (en) 1997-06-11 1998-11-10 Advanced Micro Devices, Inc. Elevated transistor fabrication technique
US6353246B1 (en) * 1998-11-23 2002-03-05 International Business Machines Corporation Semiconductor device including dislocation in merged SOI/DRAM chips
JP4540146B2 (ja) 1998-12-24 2010-09-08 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US6259135B1 (en) 1999-09-24 2001-07-10 International Business Machines Corporation MOS transistors structure for reducing the size of pitch limited circuits
AU2011250605B2 (en) 2010-05-05 2016-06-16 Allsteel Inc. Moveable and demountable wall panel system for butt-glazed wall panels

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3290753A (en) * 1963-08-19 1966-12-13 Bell Telephone Labor Inc Method of making semiconductor integrated circuit elements
US3359467A (en) * 1965-02-04 1967-12-19 Texas Instruments Inc Resistors for integrated circuits
US3442011A (en) * 1965-06-30 1969-05-06 Texas Instruments Inc Method for isolating individual devices in an integrated circuit monolithic bar
US3519901A (en) * 1968-01-29 1970-07-07 Texas Instruments Inc Bi-layer insulation structure including polycrystalline semiconductor material for integrated circuit isolation

Also Published As

Publication number Publication date
JPS5112992B2 (ja) 1976-04-23
IT956533B (it) 1973-10-10
ES410640A1 (es) 1975-12-01
BE786089A (fr) 1972-11-03
DE2235185A1 (de) 1973-04-26
JPS4850679A (ja) 1973-07-17
AU4573072A (en) 1974-03-07
ES404273A1 (es) 1975-06-01
NL7209192A (ja) 1973-04-25
GB1339095A (en) 1973-11-28
FR2156543A1 (ja) 1973-06-01
FR2156543B1 (ja) 1977-08-26
SE376327B (ja) 1975-05-12
US3791024A (en) 1974-02-12
AU462435B2 (en) 1975-06-26

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