BE786089A - Circuits integres monolithiques et leur procede de fabrication - Google Patents
Circuits integres monolithiques et leur procede de fabricationInfo
- Publication number
- BE786089A BE786089A BE786089A BE786089A BE786089A BE 786089 A BE786089 A BE 786089A BE 786089 A BE786089 A BE 786089A BE 786089 A BE786089 A BE 786089A BE 786089 A BE786089 A BE 786089A
- Authority
- BE
- Belgium
- Prior art keywords
- manufacturing process
- integrated circuits
- monolithic integrated
- monolithic
- circuits
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/764—Air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8221—Three dimensional integrated circuits stacked in different levels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
- H01L21/86—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body the insulating body being sapphire, e.g. silicon on sapphire structure, i.e. SOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76289—Lateral isolation by air gap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/008—Bi-level fabrication
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/085—Isolated-integrated
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/122—Polycrystalline
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/15—Silicon on sapphire SOS
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
- Thin Film Transistor (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US19145571A | 1971-10-21 | 1971-10-21 |
Publications (1)
Publication Number | Publication Date |
---|---|
BE786089A true BE786089A (fr) | 1972-11-03 |
Family
ID=22705564
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BE786089A BE786089A (fr) | 1971-10-21 | 1972-07-10 | Circuits integres monolithiques et leur procede de fabrication |
Country Status (12)
Country | Link |
---|---|
US (1) | US3791024A (fr) |
JP (1) | JPS5112992B2 (fr) |
AU (1) | AU462435B2 (fr) |
BE (1) | BE786089A (fr) |
CA (1) | CA967288A (fr) |
DE (1) | DE2235185A1 (fr) |
ES (2) | ES404273A1 (fr) |
FR (1) | FR2156543B1 (fr) |
GB (1) | GB1339095A (fr) |
IT (1) | IT956533B (fr) |
NL (1) | NL7209192A (fr) |
SE (1) | SE376327B (fr) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4074304A (en) * | 1974-10-04 | 1978-02-14 | Nippon Electric Company, Ltd. | Semiconductor device having a miniature junction area and process for fabricating same |
US4094057A (en) * | 1976-03-29 | 1978-06-13 | International Business Machines Corporation | Field effect transistor lost film fabrication process |
JPS5721856B2 (en) * | 1977-11-28 | 1982-05-10 | Nippon Telegraph & Telephone | Semiconductor and its manufacture |
US4199384A (en) * | 1979-01-29 | 1980-04-22 | Rca Corporation | Method of making a planar semiconductor on insulating substrate device utilizing the deposition of a dual dielectric layer between device islands |
JPH0628313B2 (ja) * | 1982-01-19 | 1994-04-13 | キヤノン株式会社 | 半導体素子 |
US4481707A (en) * | 1983-02-24 | 1984-11-13 | The United States Of America As Represented By The Secretary Of The Air Force | Method for the fabrication of dielectric isolated junction field effect transistor and PNP transistor |
JPS6072243A (ja) * | 1983-09-28 | 1985-04-24 | Matsushita Electric Ind Co Ltd | 半導体集積回路装置 |
US4879585A (en) * | 1984-03-31 | 1989-11-07 | Kabushiki Kaisha Toshiba | Semiconductor device |
US4897698A (en) * | 1984-10-31 | 1990-01-30 | Texas Instruments Incorporated | Horizontal structure thin film transistor |
JPH01162376A (ja) * | 1987-12-18 | 1989-06-26 | Fujitsu Ltd | 半導体装置の製造方法 |
US5525536A (en) * | 1991-12-26 | 1996-06-11 | Rohm Co., Ltd. | Method for producing SOI substrate and semiconductor device using the same |
US5952695A (en) * | 1997-03-05 | 1999-09-14 | International Business Machines Corporation | Silicon-on-insulator and CMOS-on-SOI double film structures |
US5889293A (en) * | 1997-04-04 | 1999-03-30 | International Business Machines Corporation | Electrical contact to buried SOI structures |
US5834350A (en) * | 1997-06-11 | 1998-11-10 | Advanced Micro Devices, Inc. | Elevated transistor fabrication technique |
US6353246B1 (en) * | 1998-11-23 | 2002-03-05 | International Business Machines Corporation | Semiconductor device including dislocation in merged SOI/DRAM chips |
JP4540146B2 (ja) | 1998-12-24 | 2010-09-08 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US6259135B1 (en) | 1999-09-24 | 2001-07-10 | International Business Machines Corporation | MOS transistors structure for reducing the size of pitch limited circuits |
BR112012028026A2 (pt) | 2010-05-05 | 2017-03-28 | Eberhard Von Huene & Ass Inc | sietema de painel de parede movível e desmontável |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3290753A (en) * | 1963-08-19 | 1966-12-13 | Bell Telephone Labor Inc | Method of making semiconductor integrated circuit elements |
US3359467A (en) * | 1965-02-04 | 1967-12-19 | Texas Instruments Inc | Resistors for integrated circuits |
US3442011A (en) * | 1965-06-30 | 1969-05-06 | Texas Instruments Inc | Method for isolating individual devices in an integrated circuit monolithic bar |
US3519901A (en) * | 1968-01-29 | 1970-07-07 | Texas Instruments Inc | Bi-layer insulation structure including polycrystalline semiconductor material for integrated circuit isolation |
-
1971
- 1971-10-21 US US00191455A patent/US3791024A/en not_active Expired - Lifetime
-
1972
- 1972-06-13 IT IT25629/72A patent/IT956533B/it active
- 1972-06-26 ES ES404273A patent/ES404273A1/es not_active Expired
- 1972-06-30 NL NL7209192A patent/NL7209192A/xx not_active Application Discontinuation
- 1972-07-06 FR FR7224473A patent/FR2156543B1/fr not_active Expired
- 1972-07-10 BE BE786089A patent/BE786089A/fr unknown
- 1972-07-18 SE SE7209433A patent/SE376327B/xx unknown
- 1972-07-18 DE DE2235185A patent/DE2235185A1/de active Pending
- 1972-07-19 CA CA147,513A patent/CA967288A/en not_active Expired
- 1972-07-20 JP JP47073008A patent/JPS5112992B2/ja not_active Expired
- 1972-07-21 GB GB3429272A patent/GB1339095A/en not_active Expired
- 1972-08-18 AU AU45730/72A patent/AU462435B2/en not_active Expired
-
1973
- 1973-01-15 ES ES410640A patent/ES410640A1/es not_active Expired
Also Published As
Publication number | Publication date |
---|---|
IT956533B (it) | 1973-10-10 |
CA967288A (en) | 1975-05-06 |
ES404273A1 (es) | 1975-06-01 |
JPS4850679A (fr) | 1973-07-17 |
JPS5112992B2 (fr) | 1976-04-23 |
DE2235185A1 (de) | 1973-04-26 |
GB1339095A (en) | 1973-11-28 |
AU4573072A (en) | 1974-03-07 |
FR2156543B1 (fr) | 1977-08-26 |
FR2156543A1 (fr) | 1973-06-01 |
SE376327B (fr) | 1975-05-12 |
AU462435B2 (en) | 1975-06-26 |
NL7209192A (fr) | 1973-04-25 |
ES410640A1 (es) | 1975-12-01 |
US3791024A (en) | 1974-02-12 |
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