CA2918503A1 - Method to minimize the number of irq lines from peripherals to one wire - Google Patents

Method to minimize the number of irq lines from peripherals to one wire Download PDF

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Publication number
CA2918503A1
CA2918503A1 CA2918503A CA2918503A CA2918503A1 CA 2918503 A1 CA2918503 A1 CA 2918503A1 CA 2918503 A CA2918503 A CA 2918503A CA 2918503 A CA2918503 A CA 2918503A CA 2918503 A1 CA2918503 A1 CA 2918503A1
Authority
CA
Canada
Prior art keywords
irq
bus
signal
slave
group
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA2918503A
Other languages
English (en)
French (fr)
Inventor
Shoichiro Sengoku
Richard Dominic Wietfeldt
George Alan Wiley
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CA2918503A1 publication Critical patent/CA2918503A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/4226—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with asynchronous protocol
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/22—Handling requests for interconnection or transfer for access to input/output bus using successive scanning, e.g. polling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2211/00—Indexing scheme relating to details of data-processing equipment not covered by groups G06F3/00 - G06F13/00
    • G06F2211/001—In-Line Device
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2211/00—Indexing scheme relating to details of data-processing equipment not covered by groups G06F3/00 - G06F13/00
    • G06F2211/002—Bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Bus Control (AREA)
CA2918503A 2013-08-24 2014-08-19 Method to minimize the number of irq lines from peripherals to one wire Abandoned CA2918503A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201361869673P 2013-08-24 2013-08-24
US61/869,673 2013-08-24
US14/462,363 2014-08-18
US14/462,363 US9921981B2 (en) 2013-08-24 2014-08-18 Method to minimize the number of IRQ lines from peripherals to one wire
PCT/US2014/051758 WO2015031115A1 (en) 2013-08-24 2014-08-19 Method to minimize the number of irq lines from peripherals to one wire

Publications (1)

Publication Number Publication Date
CA2918503A1 true CA2918503A1 (en) 2015-03-05

Family

ID=52481419

Family Applications (1)

Application Number Title Priority Date Filing Date
CA2918503A Abandoned CA2918503A1 (en) 2013-08-24 2014-08-19 Method to minimize the number of irq lines from peripherals to one wire

Country Status (9)

Country Link
US (1) US9921981B2 (enExample)
EP (1) EP3036647B1 (enExample)
JP (1) JP2016532967A (enExample)
KR (1) KR20160047484A (enExample)
CN (1) CN105474193A (enExample)
CA (1) CA2918503A1 (enExample)
ES (1) ES2647147T3 (enExample)
HU (1) HUE033685T2 (enExample)
WO (1) WO2015031115A1 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9519603B2 (en) * 2013-09-09 2016-12-13 Qualcomm Incorporated Method and apparatus to enable multiple masters to operate in a single master bus architecture
DE102014014379B3 (de) * 2014-10-02 2015-08-20 Micronas Gmbh Verfahren für eine deterministische Auswahl eines Sensors aus einer Vielzahl von Sensoren
US20180107987A1 (en) * 2016-10-14 2018-04-19 Microsoft Technology Licensing, Llc Meeting service with meeting time and location optimization
KR20180124340A (ko) * 2017-05-11 2018-11-21 엘에스산전 주식회사 프로그래머블 논리 제어 장치
JP6939240B2 (ja) 2017-08-17 2021-09-22 富士フイルムビジネスイノベーション株式会社 情報処理装置
US11030133B2 (en) * 2018-08-30 2021-06-08 Qualcomm Incorporated Aggregated in-band interrupt based on responses from slave devices on a serial data bus line
JP2024118727A (ja) 2023-02-21 2024-09-02 シャープセミコンダクターイノベーション株式会社 電子機器

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JPS6046748B2 (ja) * 1977-02-21 1985-10-17 株式会社日立製作所 コンピユ−タの割込処理方式
US4332011A (en) * 1980-03-17 1982-05-25 Cambridge Telecommunications, Inc. Data processing arrangement including multiple groups of I/O devices with priority between groups and within each group
JPS58198994A (ja) * 1982-05-15 1983-11-19 Matsushita Electric Works Ltd 時分割多重遠隔制御システムの割込処理方式
JPH07117935B2 (ja) * 1985-01-31 1995-12-18 株式会社東芝 割込み検出方式
JPH0817394B2 (ja) * 1989-09-14 1996-02-21 松下電工株式会社 時分割多重伝送システムの割込処理方式
US5555420A (en) 1990-12-21 1996-09-10 Intel Corporation Multiprocessor programmable interrupt controller system with separate interrupt bus and bus retry management
US5321818A (en) 1992-05-12 1994-06-14 Hughes Aircraft Company System for arbitrating for access on VME bus structures
US5530875A (en) * 1993-04-29 1996-06-25 Fujitsu Limited Grouping of interrupt sources for efficiency on the fly
JPH07302203A (ja) * 1994-05-10 1995-11-14 Matsushita Electric Ind Co Ltd 割込制御装置
US5943500A (en) * 1996-07-19 1999-08-24 Compaq Computer Corporation Long latency interrupt handling and input/output write posting
US5940402A (en) 1997-06-06 1999-08-17 Timeplex, Inc. Method and apparatus for TDM interrupt transmissions between multiple devices and a processor
JPH11232210A (ja) * 1998-02-16 1999-08-27 Fuji Xerox Co Ltd 情報処理装置
US6065073A (en) * 1998-08-17 2000-05-16 Jato Technologies, Inc. Auto-polling unit for interrupt generation in a network interface device
US6263395B1 (en) * 1999-01-06 2001-07-17 Compaq Computer Corp. System and method for serial interrupt scanning
JP2000231539A (ja) * 1999-02-12 2000-08-22 Ricoh Co Ltd データ転送システムおよびデータ転送方法
JP2002055830A (ja) 2000-05-29 2002-02-20 Seiko Epson Corp 割込信号生成装置及び割込信号の生成方法
US6704823B1 (en) * 2000-07-20 2004-03-09 International Business Machines Corporation Method and apparatus for dynamic allocation of interrupt lines through interrupt sharing
US20020116563A1 (en) * 2000-12-12 2002-08-22 Lever Paul D. Apparatus and method to reduce interrupt latency in shared interrupt systems
US7089338B1 (en) * 2002-07-17 2006-08-08 Cypress Semiconductor Corp. Method and apparatus for interrupt signaling in a communication network
GB0219570D0 (en) * 2002-08-22 2002-10-02 Ibm Disk drive arrangement, enclosure, adapter and method
US7200700B2 (en) 2005-05-19 2007-04-03 Inventec Corporation Shared-IRQ user defined interrupt signal handling method and system
US7752365B2 (en) 2008-04-01 2010-07-06 Kyocera Corporation Bi-directional single conductor interrupt line for communication bus
DE102008059204B9 (de) 2008-11-27 2011-05-05 Infineon Technologies Ag Verfahren zum Suchen eines Slave-Knotens in einem Kommunikationsnetz, Master-Knoten und Slave-Knoten für ein Kommunikationsnetz
US8489786B2 (en) * 2009-11-09 2013-07-16 Stmicroelectronics International N.V. Acknowledgement management technique for supported command set of SMBUS/PMBUS slave applications
US8775707B2 (en) 2010-12-02 2014-07-08 Blackberry Limited Single wire bus system
US8725916B2 (en) * 2012-01-07 2014-05-13 Microsoft Corporation Host side implementation for HID I2C data bus
US10353837B2 (en) * 2013-09-09 2019-07-16 Qualcomm Incorporated Method and apparatus to enable multiple masters to operate in a single master bus architecture
US9690725B2 (en) * 2014-01-14 2017-06-27 Qualcomm Incorporated Camera control interface extension with in-band interrupt
US20150095537A1 (en) * 2013-10-02 2015-04-02 Qualcomm Incorporated Camera control interface sleep and wake up signaling
US9519603B2 (en) * 2013-09-09 2016-12-13 Qualcomm Incorporated Method and apparatus to enable multiple masters to operate in a single master bus architecture
US9892077B2 (en) * 2013-10-07 2018-02-13 Qualcomm Incorporated Camera control interface slave device to slave device communication
EP3055779B1 (en) * 2013-10-08 2017-08-02 Qualcomm Incorporated Coexistence of i2c slave devices and camera control interface extension devices on a shared control data bus
US9684624B2 (en) * 2014-01-14 2017-06-20 Qualcomm Incorporated Receive clock calibration for a serial bus
US9904637B2 (en) * 2014-11-26 2018-02-27 Qualcomm Incorporated In-band interrupt time stamp

Also Published As

Publication number Publication date
WO2015031115A1 (en) 2015-03-05
JP2016532967A (ja) 2016-10-20
KR20160047484A (ko) 2016-05-02
EP3036647B1 (en) 2017-09-20
HUE033685T2 (en) 2017-12-28
EP3036647A1 (en) 2016-06-29
US20150058507A1 (en) 2015-02-26
CN105474193A (zh) 2016-04-06
ES2647147T3 (es) 2017-12-19
US9921981B2 (en) 2018-03-20

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Legal Events

Date Code Title Description
FZDE Dead

Effective date: 20190820