CA2774482C - Circuit d'echantillonnage de donnees et procede de recuperation d'horloge et de donnees - Google Patents
Circuit d'echantillonnage de donnees et procede de recuperation d'horloge et de donnees Download PDFInfo
- Publication number
- CA2774482C CA2774482C CA2774482A CA2774482A CA2774482C CA 2774482 C CA2774482 C CA 2774482C CA 2774482 A CA2774482 A CA 2774482A CA 2774482 A CA2774482 A CA 2774482A CA 2774482 C CA2774482 C CA 2774482C
- Authority
- CA
- Canada
- Prior art keywords
- signal
- circuit
- delay
- data
- preselected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 34
- 238000005070 sampling Methods 0.000 title claims description 34
- 238000011084 recovery Methods 0.000 title abstract description 17
- 238000004891 communication Methods 0.000 claims abstract description 22
- 230000003111 delayed effect Effects 0.000 claims description 40
- 238000001514 detection method Methods 0.000 claims description 23
- 230000001360 synchronised effect Effects 0.000 claims description 11
- 230000004044 response Effects 0.000 claims description 8
- 230000001960 triggered effect Effects 0.000 claims description 6
- 230000000295 complement effect Effects 0.000 claims description 3
- 230000005540 biological transmission Effects 0.000 abstract description 15
- 238000000605 extraction Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 27
- 230000007704 transition Effects 0.000 description 20
- 230000000630 rising effect Effects 0.000 description 14
- 238000012545 processing Methods 0.000 description 9
- 230000001934 delay Effects 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 4
- 239000000835 fiber Substances 0.000 description 3
- 230000000977 initiatory effect Effects 0.000 description 3
- 239000013307 optical fiber Substances 0.000 description 3
- 230000003044 adaptive effect Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000001976 improved effect Effects 0.000 description 2
- 230000006855 networking Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000001902 propagating effect Effects 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- XOJVVFBFDXDTEG-UHFFFAOYSA-N Norphytane Natural products CC(C)CCCC(C)CCCC(C)CCCC(C)C XOJVVFBFDXDTEG-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000013075 data extraction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229920000729 poly(L-lysine) polymer Polymers 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 230000003595 spectral effect Effects 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
- H04L7/0338—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Linvention concerne un circuit et un procédé de récupération d'horloge et de données qui sont utilisés dans un système de communications de données numériques. Le circuit et le procédé sont employés de manière efficace pour une transmission haut débit, en mode rafale, et permettent une récupération rapide des signaux d'horloge et de données sans nécessiter un en-tête étendu, et indépendamment de la présence d'une instabilité de temporisation substantielle. Le procédé choisit de manière adaptative parmi trois temps de retard pour l'extraction de données par lidentification d'un motif d'entrée à récurrence fréquente dans les données entrantes. Le temps de retard est sélectionné d'une manière qui assure que le même motif est présent dans les données de sortie reconstruites, re-synchronisées.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/US2008/011416 WO2010039108A1 (fr) | 2008-10-02 | 2008-10-02 | Circuit d'échantillonnage de données et procédé de récupération d'horloge et de données |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2774482A1 CA2774482A1 (fr) | 2010-04-08 |
| CA2774482C true CA2774482C (fr) | 2015-12-01 |
Family
ID=42073727
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA2774482A Active CA2774482C (fr) | 2008-10-02 | 2008-10-02 | Circuit d'echantillonnage de donnees et procede de recuperation d'horloge et de donnees |
Country Status (3)
| Country | Link |
|---|---|
| EP (1) | EP2335374A4 (fr) |
| CA (1) | CA2774482C (fr) |
| WO (1) | WO2010039108A1 (fr) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8724764B2 (en) * | 2012-05-30 | 2014-05-13 | Xilinx, Inc. | Distortion tolerant clock and data recovery |
| US9274545B2 (en) | 2013-10-24 | 2016-03-01 | Globalfoundries Inc. | Apparatus and method to recover a data signal |
| CN113886315B (zh) * | 2021-09-23 | 2024-05-03 | 珠海一微半导体股份有限公司 | 一种时钟数据恢复系统、芯片及时钟数据恢复方法 |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4486739A (en) | 1982-06-30 | 1984-12-04 | International Business Machines Corporation | Byte oriented DC balanced (0,4) 8B/10B partitioned block transmission code |
| EP1061691A3 (fr) * | 1999-06-15 | 2005-05-25 | Matsushita Electric Industrial Co., Ltd. | Circuit PLL digital pour données en mode rafale et circuit de réception optique utilisant ce dernier |
| US7642566B2 (en) * | 2006-06-12 | 2010-01-05 | Dsm Solutions, Inc. | Scalable process and structure of JFET for small and decreasing line widths |
| US20020085656A1 (en) * | 2000-08-30 | 2002-07-04 | Lee Sang-Hyun | Data recovery using data eye tracking |
| WO2006011830A2 (fr) * | 2004-07-20 | 2006-02-02 | Igor Anatolievich Abrosimov | Circuit resynchroniseur de recuperation de donnees a recuperation rapide a partir d'un mode faible puissance |
| US7873132B2 (en) * | 2005-09-21 | 2011-01-18 | Hewlett-Packard Development Company, L.P. | Clock recovery |
| US7983368B2 (en) * | 2006-12-11 | 2011-07-19 | International Business Machines Corporation | Systems and arrangements for clock and data recovery in communications |
| TW200835178A (en) * | 2007-02-02 | 2008-08-16 | Smedia Technology Corp | Multi-sampling data recovery circuit and method applicable to receiver |
-
2008
- 2008-10-02 EP EP08877195A patent/EP2335374A4/fr not_active Withdrawn
- 2008-10-02 CA CA2774482A patent/CA2774482C/fr active Active
- 2008-10-02 WO PCT/US2008/011416 patent/WO2010039108A1/fr active Application Filing
Also Published As
| Publication number | Publication date |
|---|---|
| EP2335374A4 (fr) | 2012-03-28 |
| CA2774482A1 (fr) | 2010-04-08 |
| EP2335374A1 (fr) | 2011-06-22 |
| WO2010039108A1 (fr) | 2010-04-08 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request |