WO2006011830A2 - Circuit resynchroniseur de recuperation de donnees a recuperation rapide a partir d'un mode faible puissance - Google Patents

Circuit resynchroniseur de recuperation de donnees a recuperation rapide a partir d'un mode faible puissance Download PDF

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Publication number
WO2006011830A2
WO2006011830A2 PCT/RU2005/000385 RU2005000385W WO2006011830A2 WO 2006011830 A2 WO2006011830 A2 WO 2006011830A2 RU 2005000385 W RU2005000385 W RU 2005000385W WO 2006011830 A2 WO2006011830 A2 WO 2006011830A2
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WIPO (PCT)
Prior art keywords
data
communications receiver
detector
clock
phase
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PCT/RU2005/000385
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English (en)
Inventor
Igor Anatolievich Abrosimov
Alexander Roger Deas
David Coyne
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Igor Anatolievich Abrosimov
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Publication of WO2006011830A2 publication Critical patent/WO2006011830A2/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0004—Initialisation of the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/046—Speed or phase control by synchronisation signals using special codes as synchronising signal using a dotting sequence

Definitions

  • the present invention relates to sampling and re-timing of data in a high speed communications interface between integrated circuits. Specifically, the sampling and re-timing of data where the receive circuit has a power down state and fast recovery from said low power state.
  • a communications receiver typically consists of a plurality of channels.
  • AMB Advanced Memory Buffer
  • the data may be encoded in a suitable fashion to allow the clock to be extracted from the data providing accurate sampling of the data in the receiver.
  • An example of such a channel is XAUI where data is 8b10b encoded and transmitted at 3.125Gbps.
  • the receiver in a XAUI communications system must decode the data correctly without the knowledge of the exact frequency of the transmitted data.
  • One problem with this technique is the over-head associated with the coding.
  • the 8b10b code results in the loss of 20% of the potential data throughput for the channel.
  • a clock is also transmitted through the communications medium where the clock is at the same frequency as the data, a multiple frequency of the data, or a sub-multiple of the frequency of the data.
  • the data is transmitted at a data rate of 2.5Gbps and a reference clock is transmitted across the channel at 100MHz i.e. 1/25 th of the data rate.
  • the data received by each channel in a multi-channel mesochronous communications system may be skewed with
  • PCI-Express applies 8b10b coding it would be possible to employ clock and data recovery on a per-channel basis.
  • another aspect of PCI- Express is the optional requirement for the low power state, LOs, and fast recovery from this state. It is usual that clock and data recovery circuits contain filtering with long time constants, for example, the loop filter in a phase lock loop. The long time constants incurred in the circuit recovering from the power-down mode necessitate that another technique be used to recover the data.
  • the generally preferred method of data recovery is to have one PLL running locked to the external reference clock and distribute the output clock from this PLL to all receive channels.
  • each receive channel the distributed, synchronous clock is aligned to the data in order to sample the data at the optimum point to produce the lowest bit error rate (BER).
  • Delay lines or phase interpolators are common methods of aligning the clock to the data, which may be designed to recover quickly from a power-down condition without the long time constant of a PLL based data recovery circuit.
  • AMB Advanced Memory Buffer
  • AMB transmitter inserts a burst of data transitions into the serial data streams in order to allow the data to be recovered and any random jitter tracked.
  • AMB a burst of eight alternating ones and zeros are inserted in a SYNC frame with SYNC frames occurring regularly. Using this method it is guaranteed that there will be at least six transitions every 504 bits transmitted.
  • a clock and data recovery circuit is required to detect these transitions and update the clock alignment to the data for correct data recovery.
  • Over-sampling techniques where the received data is sampled many times per bit are potentially suitable for the inclusion of a low power mode as the majority of the processing is performed in the digital domain and power may be reduced by halting or slowing down clocks and using other well-known techniques.
  • an over- sampling receiver such as that described in EP 1 ,386,441 by the applicants of the present invention, a synchronous clock could be distributed across many receive channels and in each receive channel could be aligned to the data transitions of each particular receive channel. On powering down the receive channel the phase of the clock in each channel could be saved. On resumption of normal operation the selected clock phase could be restored and recovery to normal operation swift.
  • the drawback with the over-sampling method is that power consumption is generally significantly higher than conventional clock and data recovery techniques and this is compounded in a system with a multitude of receive channels.
  • the length of time that a receiver may stay in a power-down state is dependant on the random jitter of the received signal.
  • the receiver must be able to track low frequency random jitter and is therefore only placed into the power-down state for a limited period.
  • it is usual for reduction of power and extension of battery life, to place the receiver into a low power state for a fixed period of time.
  • the receiver On expiration of the power-down period the receiver is turned back on and checks for any radio activity to which it must respond. If there is no radio activity to which the receiver must respond it is placed in the low power mode, again, for a fixed period of time.
  • the timing of the low power state in a Bluetooth receiver is critical to the overall operation and must be accurately controlled.
  • an AMB communications channel controls the period that the components in the channel are placed in the power-down state in order that random jitter does not accumulate and require that a lengthy training sequence be invoked to re-lock the data to the clock.
  • a system such as AMB there may be as many as 24 transmitters and 24 receivers on a single integrated circuit. Power consumption must be maintained at a low level for each receiver and transmitter in the integrated circuit in order to achieve overall low power operation. It may be necessary from time to time to reduce the temperature of the integrated circuit in an AMB system by placing it in a low power mode. The overall throughput of a system may be degraded if the average power consumption of the integrated circuit is too high necessitating the controller to repeatedly place the integrated circuit in the low power mode and losing data throughput.
  • FIG. 1 An example of a communications receiver with multiple receive channels is shown in figure 1. Data is received at the inputs to the communications receiver across a plurality of receive channels on signals RXD ⁇ 0>, RXD ⁇ 1 > etc in bus 10.
  • Clock REFCLK 20 is also an input to the communications receiver, which may be at the same frequency as the received data or, as is more generally the case, a sub- multiple of the received data rate.
  • REFCLK 20 is multiplied up to the received data rate by phase locked loop 50, generating clock 60 distributed to all receivers 40. Within each receiver, clock 60 is aligned to the data and the data is re-sampled, generating the re-timed output data RTD ⁇ 0>, RTD ⁇ 1 > etc in bus 30.
  • FIG. 2 shows a possible implementation of a PLL as used in many communications systems for clock recovery from the data comprising a phase and frequency detector (PFD) 110, a clock recovery unit (CRU) 120, a dual 2 to 1 data selector (SEL) 130, a charge pump (CP) 140, a loop filter (LF) 150, a voltage controlled oscillator (VCO) 160 and a feedback divider (FB) 170.
  • PFD phase and frequency detector
  • CRU clock recovery unit
  • SEL dual 2 to 1 data selector
  • CP charge pump
  • LF loop filter
  • VCO voltage controlled oscillator
  • FB feedback divider
  • the PLL may be therefore necessary to assist the PLL to lock to the data signal by first locking to a frequency that is close to the frequency of the data signal.
  • the REFCLK signal, 20 may be at a slightly different frequency to the frequency of the received data.
  • the PLL would be initially configured with PFD 110 driving CP 140 to lock the PLL at a frequency close to the frequency of the data and within the capture range of the CRU 120. Once lock was achieved the DATALOCK 70 signal would be changed to select the CRU 120 to drive the CP 130 and force the VCO to lock to the frequency of the signal DATA 60.
  • a conventional data recovery circuit typically used in CRU 120 is described in
  • time constants for the loop filter are of the order of many microseconds. Simply powering down the receiver and the PLL is not an option in a system where recovery is required orders of magnitude faster than that imposed by the PLL loop filter.
  • a particular form of the invention is suitable for memory to processor interfaces, high speed network interfaces and ASIC to ASIC interfaces.
  • the present invention relates to a device and method for a clock and data recovery circuit suitable for use in a communications receiver with multiple channels.
  • the clock and data recovery unit extracts information from the received data to generate control signals to align a synchronous reference clock to the data.
  • the clock and data recovery unit comprises a phase controller and phase selector.
  • the phase controller comprises: a pattern detector, which detects ISI-free patterns outputting a signal to indicate the presence of such a pattern in the received data, a transition detector, which detects the presence of transitions in the received data relative to the edge of the re-sampling clock, outputting signals to indicate the presence of said transitions and position relative to the edge of the re-sampling clock, a tracking pipeline, which adjusts the output signals from the transition detector and aligns them in time to the output signal from the pattern detector to allow processing of correct signals from each block, and a calibrate detector, which processes signals from the transition detector during the calibration phase to generate control signals that allow positioning of the edge of the re-sampling clock relative to the data transitions.
  • a pattern detector which detects ISI-free patterns outputting a signal to indicate the presence of such a pattern in the received data
  • a transition detector which detects the presence of transitions in the received data relative to the edge of the re-sampling clock, outputting signals to indicate the presence of said transitions and
  • the calibrate detector comprises a plurality of rectifying integrators and comparators for integrating the pulses from the transition detector and logic circuits for making decisions based on the absolute and relative outputs of the integrators.
  • the phase selector comprises a delay line for generating delayed versions of a reference clock; a first and second data selector for selecting outputs from the delay line; a third data selector selecting between the outputs of the first and second data selectors and a controller for control of the circuit based on the inputs from the phase controller and external control.
  • the delay line is made up of a plurality of delay elements, preferably each delay element contributing an equal period of delay, the delay line having connected to its input a reference clock, the delay line further having a total delay equal to the period of the received data,
  • the first and second data selectors have a plurality of inputs equal to the number of stages in the delay line, preferably the number of stages being sixteen, the data selectors have control inputs to select one tap from the delay line, preferably the control inputs being binary encoded in a four bit word.
  • the third data selector has two data inputs and two select inputs, the data inputs connected to the outputs of the first and second data selectors, the select inputs connected to the controller, the select inputs controlling the selection of the data inputs generating an output of the third data selector that is glitch-free.
  • the controller generates control signals for selecting the outputs of the first, second and third data selectors based on the inputs from the transition detector dependant on the control inputs from an external source for selecting the calibration or tracking mode, further the controller powers down unused circuits dependant on the mode of operation and anticipated arrival of periodic data transitions within the received data for tracking of random jitter.
  • Fig. 1 shows a block diagram of a typical communications receiver with multiple receiver channels.
  • Fig. 2 shows the block diagram of a PLL for clock and data recovery with a dual phase detector architecture.
  • Fig. 3 shows a block diagram of a serial communications input-output cell using the clock and data recovery circuit of the present invention.
  • Fig. 4 shows a block diagram of the clock and data recovery circuit in the present invention.
  • Fig. 5 shows a block diagram of the phase controller circuit in the present invention.
  • Fig. 6 shows the circuit diagram of the pattern detector employed in the phase controller of the present invention.
  • Fig. 7 and Fig. 8 show the circuit diagram of the transition detector employed in the phase controller of the present invention.
  • Fig. 9 shows the circuit diagram of the tracking pipeline employed in the phase controller of the present invention.
  • Fig. 10 shows timing diagrams associated with the various states of the transition detector.
  • Fig. 11 shows the circuit diagram of the calibrate detector employed in the phase controller.
  • Fig. 12 shows a diagram overlaying the output voltages from the integrators in the calibrate detector on top of the transition probability distribution and the logic levels for each of the different states.
  • Fig. 13 shows a diagram of a rectifying integrator with reset as employed in the integrators of the calibrate detector.
  • Fig. 14 shows a timing diagram associated with the calibrate detector.
  • Fig. 15 shows a block diagram of the phase selector.
  • Fig. 16 shows the circuit diagram of part of the delay line.
  • Fig. 17 shows the circuit diagram of one element of the delay line.
  • Fig. 18 shows the circuit diagram of the re-sampling clock data selector employed in the phase selector.
  • Fig. 19 and Fig. 20 show timing diagrams associated with the timing of the re ⁇ sampling clock data selector.
  • Fig. 21 shows a block diagram of the controller in the phase selector.
  • Fig. 22 and Fig 23 show a flowchart detailing the operation of the controller in the phase selector.
  • FIG. 3 shows a block diagram of a communications receiver with the clock and data recovery circuit (CDR) of the present invention.
  • the receiver comprises PLL 200 locked to REFCLK 20 and generating re-timing clock RTCLK 201 , one instance of the PLL being used to supply clock RTCLK 201 across a several channels.
  • the receiver further comprises, in each channel, RX buffer 100 for receiving data RXDIN 10, CDR 300 for locking RTCLK 201 to RXIN 101 and producing re-sampling clock RSCLK, RX elastic buffer deskew and deserialiser 400, TX serialiser 500, output clock and data selector 600, TX synchroniser and de- emphasis 700 and TX output buffer 800.
  • CDR 300 aligns RTCLK 201 to RXIN 101 and produces re-sampling clock RSCLK 301.
  • the re-sampling clock allows fast pass-through of data from RXIN to TXOUT.
  • An alternate mode of operation allows the pass-through of data to be re ⁇ timed and the TXOUT data aligned to RTCLK.
  • Clock and data selectors 600 select the clock and data for the transmit output TXOUT from several sources dependant on the control lines in bus CTRL.
  • the bus CTRL also controls other aspects of the operation of the input-output cell.
  • FIG. 4 shows a block diagram of CDR 300 comprising phase controller 320 and phase selector 370.
  • CDR 300 generates re-sampling clock RSCLK 301 from RTCLK 201 wherein re-sampling clock RSCLK 301 is locked to the received data RXIN 101.
  • Phase controller 320 generates control signals FTRAN ⁇ 1 :0> 321 , VALID 322 and STRAN ⁇ 1 :0> 323 that are processed by phase selector 370 under control of signals CALIBRATE and TRACK in bus 910.
  • phase selector 370 interacts with phase controller 320 through the signal RESJNT 325.
  • a delayed version of the received data RXIN 101 is generated.
  • DRXIN 324 is aligned to the re-sampling clock RSCLK 301 where the falling edge of RSCLK occurs in the centre of the data eye of DRXIN 324.
  • Bus PHASE 920 generated by the phase selector 370 is bi-directional and in the direction out of CDR 300 is used for monitoring purposes elsewhere in the receiver.
  • bus PHASE 920 is used in the direction into CDR 300 it allows the phase to be set to any value.
  • a typical use of bus PHASE 920 would be to monitor the re-sampling clock phase selection pointer and store the same prior to a temporary power down of a receiver channel. On power up of the receive channel the phase selection pointer could be reinstated and the receive channel continue to operate without having to go through a lengthy calibration sequence.
  • Another use of bus 920 would be the diagnostic monitoring of the random jitter on the received data.
  • CDR 300 has two operating modes, calibration and tracking.
  • calibration mode a data pattern is received that has a high transition density allowing the alignment of re-sampling clock RSCLK 301 to the data eye of received data RXIN 101.
  • CDR 300 determines the centre of the data eye by detecting transitions and positioning the rising edge of re-sampling clock RSCLK 301 at the point where transitions in the data eye have the highest density.
  • the time constant associated with the averaging process must be long enough to ensure a statistically correct result whilst being sufficiently short to negate the effects of spread spectrum clocking that may be applied to the reference clock 140 and received data 101 as typically used in Personal Computer design to reduce EMI.
  • the tracking mode may be entered to track random jitter.
  • the CDR updates the phase of the re-sampling clock by monitoring the presence of transitions in the data.
  • the update of the re-sampling clock phase needs to occur even in the case where the presence of a high transition density may not be guaranteed.
  • coding is often applied to the data to ensure a high transition density to maintain lock within the CDR but coding has an overhead that reduces the effective data transfer rate and often increases latency during the coding and decoding of the data.
  • An example of such a coding technique may be found in the IEEE XAUI standard where an 8b10b code is applied to the data, resulting in a 20% lower data transmission throughput.
  • Using the same method as employed in the calibration mode of CDR 300 may not produce a statistically correct output with a low density of data transitions or indeed with no data transitions except for a burst every SYNC frame in the case of AMB. Further, the integration period may be long and random jitter may render the use of the calibration mode inoperable. A method is required that maintains lock of the re-sampling clock to the received data in the case where the number of transitions is very low. In the Advanced Memory Bus (AMB) standard transitions are inserted into the data stream with the introduction of SYNC frames. A SYNC frame contains a burst of transitions with an eight bit pattern of 01010101 or 10101010 that occurs approximately every 512 data bits.
  • AMB Advanced Memory Bus
  • transitions in the centre of the burst will be guaranteed to be ISI-free for a communications channel where the ISI is restricted to a period much less than one unit interval. Transitions at the edges of the burst may not be ISI-free and should not be used to update the phase of the re ⁇ sampling clock. Synchronising to these transitions may not be straight-forward, especially when considering the implementation of high-speed counters to generate a detection window.
  • the present invention resolves this problem by detecting any such patterns directly in the received data.
  • Figure 5 shows the preferred embodiment of phase controller 320 comprising pattern detector 330, transition detector 340, calibrate detector 350 and tracking pipeline 360.
  • Pattern detector 330 detects the patterns selected to be ISI-free, with RXIN
  • Pattern detector 330 is used in the tracking mode of operation as it requires re-sampling clock RSCLK 301 to be aligned closely to the received data RXIN 101.
  • Transition detector 330 determines when a transition occurs in the received data by sampling the received data either side of the rising edge of the re-sampling clock 301.
  • Bus 349 contains information indicating the presence or absence of a transition in the received data RXIN 101 in the proximity of the rising edge of re- sampling clock RSCLK 301. Further, bus 349 may indicate whether the transition is early or late with respect to the rising edge of the re-sampling clock. In the tracking mode this information is passed through tracking pipeline 360, generating output bus FTRAN ⁇ 1 :0> 322 used by phase selector 370 to control the phase of the re ⁇ sampling clock. In calibration mode transition detector 340 produces bus 341 which is a super-set of bus 349.
  • the data in bus 341 is input to calibration detector 350 where the data is averaged producing bus STRAN ⁇ 1 :0> 323, again used by phase selector 370 to control the phase of the re-sampling clock and generate the initial lock to the received data.
  • Figure 6 shows the preferred embodiment of pattern detector 320.
  • Pattern detector 320 outputs a logic high on signal VALID 322 when a pattern of six alternating data bits occurs, that is, when a pattern 010101 or 101010 is received.
  • Flip-flops 331 and exclusive OR gate 332 are connected to form a difference detector, the output of exclusive OR gate 332 going high when two sampled, adjacent bits are detected.
  • Flip-flops 333 with AND gate 334 form a sequence detector and generate a logic high at the output of AND gate 334 whenever a sequence of six alternating bits are detected in the received data RXIN 101.
  • Flip- flops 335 and 336 align the output signal VALID 322 of the pattern detector to the rising edge of the re-sampled clock RSCLK 301. It is obvious to someone skilled in the art that other implementations of pattern detector 320 may produce the same function.
  • the VALID signal will go high for a minimum of three clock periods, allowing the processing of the information from the three centre transitions in the sequence. It is also possible that the pattern detector could be reduced in length, subsequently allowing the reduction in the length of tracking pipeline 360. In the case where the pattern detector was reduced in length the update rate of the phase of the re-sampling clock could be higher, however, it is noted that a shorter pattern detector may make the CDR more susceptible to ISI.
  • Figures 7 and 8 show the preferred embodiment of transition detector 340 comprising two delay lines formed by delay elements 342 and 343, flip-flop samplers 344, exclusive OR gates 345 and logic gates 346 and 347.
  • the longer of the two delay lines consisting of delay elements 343 delays signal RXIN 101 incrementally and monotonically producing several delayed output signals that are sampled in flip-flop samplers 344 by the re-sampling clock RSCLK
  • the sequence 0011 is generated at the output of the samplers for a low to high transition in the received data.
  • the output of the samplers will produce a sequence at the output of samplers 344 of 1000, 1100, or 1110 dependant on the exact alignment of the data transition to the re-sampling clock. It is intended that when the received data RXIN 101 is correctly aligned to the re-sampling clock RSCLK 301 , the sequence 1100 is generated at the output of flip- flop samplers 344 for a high to low data transition in the received data.
  • the output of the flip-flop samplers 344 are combined in exclusive OR gates 345 to detect where the transition occurs relative to the delay line formed by delay elements 343.
  • a transition of either polarity in the received data RXIN should produce an output on bus DX ⁇ 2:0> 341 , the data bus contents being 010.
  • Bus DX ⁇ 2:0> is connected to the input of the calibrate detector 360 in addition to being coded into the two bit bus DDX ⁇ 1 :0> 349 by gates 346 and 347.
  • Bus DDX ⁇ 1 :0> 349 is coded to produce an early and late pulse on bits 0 and 1 of the bus respectively.
  • the tracking detector can be expanded to operate over a larger delay line. By means of an example, increasing the delay line to six bits it would be possible to track up to two delays in the period between SYNC frames. Such a scheme would increase power consumption and complexity.
  • the re-sampling clock samples the data in the delay line formed by delay elements 343 on the rising edge of the re-sampling clock, defining the edge of the data bit cell
  • RSCLK is aligned not to RXIN 101 but to a delayed version of RXIN.
  • the receive data is delayed in the delay line formed by delay elements 342 producing signal DRXIN 324, producing a data signal that is aligned to the re ⁇ sampling clock RSCLK 301.
  • the delayed receive data signal DRXIN 324 is sampled by the falling edge of RSCLK in synchroniser 700.
  • the elements 342 and 343 in both delay lines are matched. Additional delay matching may be required depending on the loads presented to the delay line.
  • Figure 9 shows the preferred embodiment of tracking pipeline 360.
  • Bus DDX ⁇ 1 :0> 341 is delayed four periods of the re-sampling clock RSCLK in flip-fops 361 , aligning signal VALID 322 from pattern detector 320 with output bus FTRAN ⁇ 1 :0>.
  • Figure 10 shows three timing diagrams for the alignment of received data RXIN 101 to re-sampling clock RSCLK 301. The timing diagrams show the received data early with respect to the re-sampling clock, aligned to the re-sampling clock and late with respect to the re-sampling clock.
  • the values on bus DX ⁇ 2:0> 341 and bus FTRAN ⁇ 1 :0> 321 are also shown for the three cases.
  • calibration detector 350 is used to centre the re-sampling clock to the data.
  • Figure 11 shows the preferred embodiment of calibration detector 350 comprising rectifying integrators 351 , comparators 352, 353 and 356, majority voting circuit 354 and pull-down transistors 355.
  • the bits of bus DX ⁇ 2:0> 341 from the transition detector are inputs to rectifying integrators 351.
  • a logic high value on any bit of bus DX ⁇ 2:0> 324 indicates the presence of a transition in the received data at the corresponding offset with respect to the re-sampling clock RSCLK 301 , the offset being defined by the delay elements 343 of the delay line in transition detector 340.
  • the preferred embodiment of the delay line formed by delay elements 342 and 343 in transition detector 340 is described later in relation to delay line 373.
  • the voltages associated with the logic levels of the bits in bus DX ⁇ 2:0> are integrated by rectifying integrators 351 producing the output voltages labelled A, B and C in figure 11.
  • the outputs of integrators 351 are compared against fixed voltages in comparators 352 and 353 the outputs of these comparators connected to the inputs of majority voting circuit 354.
  • the outputs of comparators 352 and 353 indicate that two or more of the integrated voltages are below the fixed thresholds the output of majority voting circuit 354 goes high turning on pull-down transistors 355 and forcing bus STRAN ⁇ 1 :0> to the logic state ⁇ 00>. This indicates that re-sampling clock RSCLK 301 is not close to the transition edges of data RXIN 101.
  • Controller 371 interprets the logic levels on STRAN ⁇ 1 :0> and increments the phase of the re-sampling clock, till this condition no longer occurs and two of the three outputs of integrators 351 are above the fixed thresholds and the re-sampling clock is in close proximity of the optimum alignment. At this point the output of majority voting circuit 354 goes low and turns off pull-down transistors 355, enabling the outputs of comparators to drive bus STRAN ⁇ 1 :0> 323.
  • the probability distribution of a transition in the received data with respect to the ideal position of the transition will be a function of the characteristics of the random and deterministic jitter on the received data. Integration of the transitions detected in the received data will produce an output voltage whose magnitude is a function of the jitter characteristics. For transitions with no offset relative to the re ⁇ sampling clock RSCLK 301 , integration of the pulses in bus DX ⁇ 2:0> 341 will produce a voltage that coincides with the peak in the probability distribution that voltage being the largest integrated output voltage obtained for a fixed integration period. For an offset of the data with respect to the re-sampling clock, the output voltage will be lower.
  • the three bits in bus ⁇ DX ⁇ 2:0> 341 are integrated and the outputs of the integrators compared against the profile expected from the transition probability distribution.
  • the receive data RXIN 101 is aligned to the re- sampling clock RSCLK 301 the highest probability of a transition is associated with bit DX ⁇ 1 >, while transitions associated with bits DX ⁇ 2> and DX ⁇ 0> have lower probability. Accordingly, when the receive data RXIN 101 is aligned to the rising edge of the re-sampling clock RSCLK 301 , the output voltage at node B is higher than the output voltages of the other two integrators.
  • FIG. 12 shows the integrator output voltages for the three cases of data arriving earlier than the re-sampling clock, data aligned to the re-sampling clock and data arriving later than the re ⁇ sampling clock.
  • the integration period during calibration needs to be sufficiently large so as to generate a statistically significant result in the bus STRAN ⁇ 1 :0>.
  • Offset in the integrators and comparators can manifest themselves as effectively larger or smaller output voltages. These offsets need to be controlled.
  • Techniques for integrator offset cancellation are well know to those skilled in the art and include calibration by applying know data waveforms and monitoring the outputs till they are all equal, as indicated by the comparator outputs toggling.
  • the magnitude of the delay period introduced to the received data from the delay elements 343 in the delay line of transition detector 340 may also affect the operation of calibration detector 350. Where the delay period is very short then the difference in the probability distribution may be small and result in similar output voltages from the three integrators. Decreasing the delay to improve the clock to data alignment may result in improper operation of calibration detector 350. Increasing the delay may result in multiple clock alignment positions where the output states of the calibration detector remain constant for varying clock to data offset. Further the use of patterns containing mainly alternating zeros and ones will combined with a very small delay in delay elements 343 may require adjustment of the fixed threshold voltages in calibrate detector 350.
  • transition detector 340 and calibration detector 350 may allow more information to be processed to align the clock to the data during the calibration phase.
  • the calibration detector could be extended to generate five sampling points on the probability distribution curve and more advanced techniques such as mid-point determination used to select the optimum phase for the re-sampling clock.
  • One possible implementation of the rectifying integrators 351 , 352 and 353 is shown in figure 13 comprising a diode 451 , resistor 452, capacitor 453 and reset switch 454. Diode 451 and capacitor 453 perform peak detection with resistor 452 limiting the integration time-constant.
  • Switch 454 is used to reset the integrator at the beginning of each integration cycle and controlled by phase selector 370 through signal RESJNT 325.
  • Figure 14 shows a timing diagram associated with the calibration detector detailing the integration of the data bits in bus DX ⁇ 2:0> 341. Random jitter on the received data manifests itself in pulses in DX ⁇ 2:0> 341 being integrated and producing different voltages at the outputs of integrators 351 , 352 and 353. Further, the outputs of comparators 357 and 358 generate signals STRAN ⁇ 1 > and STRAN ⁇ 0> respectively. The signals in bus STRAN ⁇ 1 :0> change dynamically and towards the end of the integration period stabilise at fixed logic levels.
  • FIG. 15 shows the preferred embodiment of phase selector 370 comprising controller 371 , data selectors 372 and 374, delay line 373 and 2-to-1 data selector 375.
  • Control signals 910 determine the mode of operation of the phase selector, the calibration mode being set by a logic high value on signal CALIBRATE while the tracking mode being set by a logic high value on signal TRACK, the signals TRACK and CALIBRATE neither being high at the same.
  • Data selectors 372 and 374 in conjunction with delay line 373 and data selector 375 generate the re-sampling clock 301 from the re-timer clock 201 under control of controller 371.
  • Controller 371 generates signals PH_0 376 and PH_1 377 for selecting the tap from delay line 373.
  • the preferred embodiment shown in Figure 15 adopts two data selectors 372 and 374 to select taps from the delay line and a final data selector to select the output of data selector 372 or 374 for RSCLK 301.
  • the control of data selectors 372 and 374 relies on the fact that the phase of the clock is only adjusted in small increments.
  • the outputs of data selectors 372 and 374 are selected in such a manner that the clock pulses are logically OR'd for one period of RSCLK. This ensures a glitch-free output.
  • Data selector 375 has two separate enables EN_0 380 and EN_1 381 generated by controller 371 to select and gate the outputs CLK_0 382 and CLK_1 383 from data selectors 372 and 374 respectively
  • Figure 16 shows the preferred embodiment of delay line 373 using a string of serially connected differential buffers 470. It is obvious to someone skilled in the art that the delay line may take other forms and may consist of a plurality of transmission lines, discrete or active filters, and other elements that generate the property of time delay.
  • delay line 373 consists of 16 equal delay elements and the delay through each of the delay elements is such that the delay through the delay line is equal to one data bit-period.
  • differential buffers may be typically formed from all NMOS transistors to maintain high-speed operation.
  • Figure 17 shows the preferred embodiment of differential buffer 470.
  • NMOS transistors 471 and 472 form a differential pair.
  • the differential input signal is applied across the gates of transistors 471 and 472.
  • the common mode voltage of the input signal provides DC biasing of transistors 471 and 472.
  • NMOS transistors 473 and 474 form an active load.
  • the load presented to the differential pair formed by transistors 471 and 472 is a function of the process parameters; device size and the bias voltage applied to the gates of the active load transistors 473 and 474.
  • NMOS transistor 475 forms a constant current bias for the NMOS transistors forming differential pair 471 and 472 and active load 473 and 474.
  • the voltage applied to the gate of transistor 475 primarily determines the bias current for differential buffer 470.
  • Each differential buffer 470 is connected to a separate signal in bus 378 and bus 379 connecting to data selectors 372 and 374 respectively.
  • the delay in each element of the delay line is dependant on bias current, transistor sizes and load presented to the output of each differential buffer. In the preferred embodiment it is preferred that the delay for each stage of the delay line 373 is constant.
  • a typical control mechanism would include a delay locked loop where the output of the delay line would be compared to the input to the delay line and the delay of the individual elements controlled to match the total delay to the period of the re-sampling clock.
  • a delay locked loop In a multi-channel receiver it is generally not practical to include a delay locked loop in each channel for reasons of area and power consumption. Further, the lock time of the delay locked loop may also cause problems in recovery from low power-down operation.
  • the preferred embodiment in the present invention is to have one, separate, delay locked loop for all receiver channels containing a master delay line that is matched to a slave delay line, delay line 373, in each receiver channel.
  • the master delay locked loop would not normally be powered down when the receiver channels were powered down and would generate a continuous control voltage for the slave delay lines in each receiver channel.
  • the implementation of such a delay locked loop and the generation of control voltage for the slave locked loops is obvious to someone skilled in the art.
  • controller 371 may generate suitable control signals to perform these tasks.
  • Figure 18 shows the preferred embodiment of data selector 375.
  • the selected clocks from data selectors 372 and 374 are differential inputs CK_0_P, CK_0_N and CK_1_P, CK_1_N to data selector 375 and are applied to the gates of NMOS transistors 480, 481 , 482 and 483 respectively.
  • the single-ended enable EN_0 is applied to the gates of NMOS transistors 484 and 485 and acts as the enable for differential inputs CK_0_P and CK0_N.
  • the single-ended enable EN_1 is applied to the gates of NMOS transistors 486 and 487 and acts as the enable for differential inputs CK_1_P and CK_1_N.
  • PMOS transistors 488 and 489 acts as a differential load for the data selector.
  • output edges are defined by alternate edges of the two clock inputs.
  • Figure 19 shows the operation of data selector 375 during the period when the phase is being updated.
  • Figure 20 shows a timing diagram detailing which edges contribute to the output clock, RSCLK 301 , for the two cases of phase advance and phase retardation.
  • EN_0 and EN 1 would be complementary enabling either one input pair or the other to be routed to the output.
  • the signals are unique and allow both pairs of input signals to be routed to the output providing the logical OR'ing of the two pairs of inputs. Since there is only a small delay between the pairs of inputs the output is glitch-free.
  • Controller 371 may be configured to operate under different conditions of data patterns and jitter characteristics.
  • a data pattern rich in transitions is received in the calibration phase and CDR 300 locks the rising edge of the re-sampling clock RSCLK 301 to the edges of the data transitions by detecting the average position in time of the transition edge.
  • CDR 300 switches to the tracking mode where the only guaranteed transitions occur in a burst of alternating zeros and ones.
  • the transitions in the centre of the burst are processed to determine whether to advance or retard the phase of the re-sampling clock to maintain alignment of the re- sampling clock to the edges of the data transitions.
  • FIG 21 shows a block diagram of the preferred implementation of controller 371 comprising finite state machine 1 (FSM1) 490, finite state machine 2 (FSM2) 491 and phase latches 492 and 493.
  • FSM1 490 is the main state machine controlled mainly by CALCLK 920 while FSM2 491 is the state machine which controls the timing of the EN_0 and EN_1 signals.
  • FSM1 is mainly lower speed operation while FSM2 is high speed operation and this configuration allows for optimisation of the design in different clock domains to maintain low power operation.
  • the operation of controller 371 is described in the flowchart diagrams of figures 22 and 23.
  • Figure 22 shows the operation of controller 371 in calibration mode.
  • Signals in bus DX ⁇ 2:0> 341 are integrated as shown in figure 11 to determine where the re-sampling clock is aligned correctly with respect to the data transitions.
  • Figure 23 shows the operation of controller 372 in tracking mode.
  • a burst of eight alternating zeros and ones will produce a VALID signal 322 that is three bits wide.
  • Controller detects the presence of the VALID signal 322 generated by pattern detector 330 and averages the information from bus FTRAN ⁇ 1 :0> 321 , determining, over the three periods that VALID is high, whether to increment the phase value, decrement the phase value or make no change to the phase value.
  • the signal VALID may also detect the presence of data sequences that are not part of the guaranteed, periodic tracking pattern, a check is made to ensure that the VALID pulse is three clock periods wide.
  • VALID signal 322 is less than three periods wide the information is ignored and the process is reset to await the next correct sequence. If a data pattern is received that contains a long sequence of alternating zeros and ones then signal VALID would be high for proportionately longer period.
  • the information from bus FTRAN ⁇ 1 :0> is processed for the first three transitions, the decision to update the phase made and a lock-out period started. During the lock-out period the phase is updated in the sequence previously described where, after a settling period, the EN_0 and EN_1 signals are generated by FSM2 491.
  • controller 371 only acts on data that has been generated by the updated re-sampling clock. With long sequences of alternating ones and zeros it is possible that the re-sampling clock track higher frequency jitter than that from the periodic insertion of the guaranteed burst pattern.
  • a typical power management scheme as utilised in AMB is to send a control word across the serial links such that the control word may be decoded to indicate that the receiver should power down for a period of time where the period is sufficiently short to not allow drift of the re-sampling clock.
  • the architecture of the present invention is particularly suited to operating with this type of power management scheme. Calibration may be a particularly time-consuming process and it is not beneficial to re-calibrate the receiver on return from a power-down mode. In the present invention it is possible to enter the power-down mode from the tracking mode. Prior to entering the power-down mode the value of the phase is stored in registers 492 and 493 of controller 371. During power-down the contents of registers 492 and 493 are protected and not changed.
  • controller 371 On recovery from the power- down mode CDR 300 is powered up in a controlled manner, possibly starting a short period of time before the end of the power-down period, and, controller 371 starts operating in the tracking mode bypassing the calibration mode using the stored values in phase registers 492 and 493.
  • the power-down period is not excessive as to allow random jitter in the system to cause misalignment of the re-sampling clock to the received data.
  • the total period may be made up of multiple periods of shorter power- down duration where CDR 300 is able to receive phase tracking information during short power-up periods.
  • this can be achieved by the host controller sending a power-down command followed by data frames after recovery from the power down period.
  • the data frames received after power down recovery containing a burst of alternating zeros and ones. This may be repeated with further power down commands till the required power down period or average power level has been achieved.
  • a further level of power management may be obtained by turning off calibrate detector 350 while in tracking mode and similarly turning off tracking pipeline 360 while in calibrate mode.
  • lower power operation may be achieved by turning off pattern detector 330, most parts of transition detector 350, calibrate detector 350 and tracking pipeline 360 in the periods between SYNC frames. This level of power reduction may be achieved through the main controller containing a frame counter and after updating the phase powering down circuitry until just before the next SYNC frame is due to occur.
  • single-ended signals are generally depicted for reasons of diagrammatic clarity. However, it is obvious that in very high speed circuits differential signalling is often the preferred method of transporting data from circuit to circuit. The preferred implementation within the present invention primarily uses differential signals.
  • clock and data recovery circuits operate with half-rate clocks, that is, with a re-sampling clock of one half the frequency of the received data. Modification of the present invention to operate with a half-rate clock or quarter-rate quadrature clocks is entirely possible and obvious to someone skilled in the art.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

L'invention concerne l'échantillonnage et la resynchronisation de données dans une interface de communications à grande vitesse entre circuits intégrés. Plus précisément, elle concerne l'échantillonnage et la resynchronisation de données où le circuit de réception présente un état de coupure de puissance et une récupération rapide à partir de cet état. Le récepteur de communications comporte plusieurs voies de réception et une boucle à phase asservie, chaque voie comprenant une horloge et un circuit de récupération de données, et la boucle à phase asservie génère une horloge de sortie distribuée à toutes les voies de réception, de façon que chacune de ces voies aligne l'horloge de sortie à partir de la boucle à phase asservie jusqu'aux données de réception pour la même voie de réception.
PCT/RU2005/000385 2004-07-20 2005-07-20 Circuit resynchroniseur de recuperation de donnees a recuperation rapide a partir d'un mode faible puissance WO2006011830A2 (fr)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2335374A1 (fr) * 2008-10-02 2011-06-22 Zenko Technologies, Inc. Circuit d'échantillonnage de données et procédé de récupération d'horloge et de données

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2335374A1 (fr) * 2008-10-02 2011-06-22 Zenko Technologies, Inc. Circuit d'échantillonnage de données et procédé de récupération d'horloge et de données
EP2335374A4 (fr) * 2008-10-02 2012-03-28 Zenko Technologies Inc Circuit d'échantillonnage de données et procédé de récupération d'horloge et de données

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