CA2630082C - Systeme et methode permettant de generer un signal de remise a zero - Google Patents

Systeme et methode permettant de generer un signal de remise a zero Download PDF

Info

Publication number
CA2630082C
CA2630082C CA2630082A CA2630082A CA2630082C CA 2630082 C CA2630082 C CA 2630082C CA 2630082 A CA2630082 A CA 2630082A CA 2630082 A CA2630082 A CA 2630082A CA 2630082 C CA2630082 C CA 2630082C
Authority
CA
Canada
Prior art keywords
signal
clock signal
offset
input
reset
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CA2630082A
Other languages
English (en)
Other versions
CA2630082A1 (fr
Inventor
Joseph Deschamp
Carl R. Cochrane
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Harris Corp
Original Assignee
Harris Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Harris Corp filed Critical Harris Corp
Priority to CA2630082A priority Critical patent/CA2630082C/fr
Publication of CA2630082A1 publication Critical patent/CA2630082A1/fr
Application granted granted Critical
Publication of CA2630082C publication Critical patent/CA2630082C/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Controls And Circuits For Display Device (AREA)

Abstract

Des systèmes et procédés pour générer un signal de remise à zéro, par exemple pour permettre la synchronisation. Selon un mode de réalisation, un système pour émettre un signal de remise à zéro comprend un générateur de décalage qui fournit un signal de décalage d'horloge ayant un décalage de fréquence par rapport à une fréquence dun signal dhorloge dentrée. Un générateur de remise à zéro génère le signal de remise à zéro en réponse à la détection dun décalage de phase périodique entre le signal de décalage dhorloge et le signal dhorloge dentrée.
CA2630082A 2008-04-28 2008-04-28 Systeme et methode permettant de generer un signal de remise a zero Active CA2630082C (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CA2630082A CA2630082C (fr) 2008-04-28 2008-04-28 Systeme et methode permettant de generer un signal de remise a zero

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CA2630082A CA2630082C (fr) 2008-04-28 2008-04-28 Systeme et methode permettant de generer un signal de remise a zero

Publications (2)

Publication Number Publication Date
CA2630082A1 CA2630082A1 (fr) 2009-10-28
CA2630082C true CA2630082C (fr) 2013-07-02

Family

ID=41255938

Family Applications (1)

Application Number Title Priority Date Filing Date
CA2630082A Active CA2630082C (fr) 2008-04-28 2008-04-28 Systeme et methode permettant de generer un signal de remise a zero

Country Status (1)

Country Link
CA (1) CA2630082C (fr)

Also Published As

Publication number Publication date
CA2630082A1 (fr) 2009-10-28

Similar Documents

Publication Publication Date Title
US7831855B2 (en) System and method for generating a reset signal for synchronization of a signal
TWI720008B (zh) 用於三相介面之多相位時脈資料回復
JP6420330B2 (ja) 3位相またはn位相アイパターンの指定
KR102502236B1 (ko) 클락 데이터 복구 회로, 이를 포함하는 장치 및 클락 데이터 복구 방법
US20060092100A1 (en) Display controlling device and controlling method
CN101510419B (zh) 显示器的自动频率和相位调节装置和方法
EP2120056B1 (fr) Système et procédé de génération d'un signal de réinitialisation
CN104579325B (zh) 数据接收装置与方法
CN109427276B (zh) 显示装置、时序控制电路及其信号重建方法
CA2630082C (fr) Systeme et methode permettant de generer un signal de remise a zero
US20040085309A1 (en) Method and apparatus for coordinating horizontal and vertical synchronization signals
CN110830742B (zh) 一种消除vga信号抖动的方法及装置
JP4017335B2 (ja) 映像信号の有効期間検出回路
CN101583047B (zh) 用于生成复位信号的系统和方法
KR100272273B1 (ko) 동기 신호 검출 회로 및 방법
KR0142468B1 (ko) 액정 표시장치의 실효화면 중앙표시 구동 장치 및 방법
JP2004254007A (ja) ジッタ・キャンセルの方法および装置
KR20170122357A (ko) 표시장치
US6946881B1 (en) Method to detect the polarity of sync signals without external capacitor or clock
KR0158645B1 (ko) 액정표시장치의 데이터 인에이블 모드 우선 순위 검출회로
US5949255A (en) Method and apparatus for generating active pulse of desired polarity
TW571516B (en) Phase-locked loop and its control method
CN102468830B (zh) 一种利用多相位信号提高频率比较器精度的方法和电路
JP2003224528A (ja) 光波形評価方法
JP4584725B2 (ja) 映像処理装置

Legal Events

Date Code Title Description
EEER Examination request