CA2155379A1 - Circuit which includes cells with high fanout requirements which has a reduced rc delay - Google Patents

Circuit which includes cells with high fanout requirements which has a reduced rc delay

Info

Publication number
CA2155379A1
CA2155379A1 CA002155379A CA2155379A CA2155379A1 CA 2155379 A1 CA2155379 A1 CA 2155379A1 CA 002155379 A CA002155379 A CA 002155379A CA 2155379 A CA2155379 A CA 2155379A CA 2155379 A1 CA2155379 A1 CA 2155379A1
Authority
CA
Canada
Prior art keywords
cells
cell
copy
coupled
lookahead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA002155379A
Other languages
English (en)
French (fr)
Inventor
Steven Craig Bartling
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CA2155379A1 publication Critical patent/CA2155379A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/506—Indexing scheme relating to groups G06F7/506 - G06F7/508
    • G06F2207/5063—2-input gates, i.e. only using 2-input logical gates, e.g. binary carry look-ahead, e.g. Kogge-Stone or Ladner-Fischer adder

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Apparatus Associated With Microorganisms And Enzymes (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)
CA002155379A 1994-10-14 1995-08-03 Circuit which includes cells with high fanout requirements which has a reduced rc delay Abandoned CA2155379A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US32314994A 1994-10-14 1994-10-14
US08/323,149 1994-10-14

Publications (1)

Publication Number Publication Date
CA2155379A1 true CA2155379A1 (en) 1996-04-15

Family

ID=23257917

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002155379A Abandoned CA2155379A1 (en) 1994-10-14 1995-08-03 Circuit which includes cells with high fanout requirements which has a reduced rc delay

Country Status (7)

Country Link
EP (1) EP0707262A1 (zh)
JP (1) JP3238052B2 (zh)
KR (1) KR960015198A (zh)
CN (1) CN1126859A (zh)
BR (1) BR9504270A (zh)
CA (1) CA2155379A1 (zh)
TW (1) TW269074B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2775531B1 (fr) * 1998-02-27 2001-10-12 Sgs Thomson Microelectronics Additionneur numerique rapide
GB9817899D0 (en) * 1998-08-17 1998-10-14 Sgs Thomson Microelectronics Designing addition circuits
US20030069914A1 (en) * 1998-09-03 2003-04-10 Agilent Technologies Carry lookahead adder having a reduced fanout architecture
TWI361306B (en) 2008-07-11 2012-04-01 Au Optronics Corp Multidomain-vertical-alignment transreflective lcd

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1989008294A1 (en) * 1988-02-29 1989-09-08 Chopp Computer Corporation Carry generation method and apparatus
IT1249833B (it) * 1990-11-13 1995-03-28 Tong Lung Metal Ind Co Ltd Serratura a codice meccanico
US5278783A (en) * 1992-10-30 1994-01-11 Digital Equipment Corporation Fast area-efficient multi-bit binary adder with low fan-out signals
US5396435A (en) * 1993-02-10 1995-03-07 Vlsi Technology, Inc. Automated circuit design system and method for reducing critical path delay times

Also Published As

Publication number Publication date
BR9504270A (pt) 1998-12-22
JP3238052B2 (ja) 2001-12-10
KR960015198A (ko) 1996-05-22
JPH08123666A (ja) 1996-05-17
CN1126859A (zh) 1996-07-17
TW269074B (en) 1996-01-21
EP0707262A1 (en) 1996-04-17

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Legal Events

Date Code Title Description
FZDE Dead