CA2058778C - Photoelectric converting device and image processing apparatus utilizing the same - Google Patents
Photoelectric converting device and image processing apparatus utilizing the sameInfo
- Publication number
- CA2058778C CA2058778C CA002058778A CA2058778A CA2058778C CA 2058778 C CA2058778 C CA 2058778C CA 002058778 A CA002058778 A CA 002058778A CA 2058778 A CA2058778 A CA 2058778A CA 2058778 C CA2058778 C CA 2058778C
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- Prior art keywords
- photoelectric converting
- converting device
- semiconductor layers
- processing apparatus
- image processing
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- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
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- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 5
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- 238000005530 etching Methods 0.000 description 5
- 239000012535 impurity Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 3
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- -1 nitrogen ions Chemical class 0.000 description 3
- 230000000737 periodic effect Effects 0.000 description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
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- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910014299 N-Si Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- YZCKVEUIGOORGS-IGMARMGPSA-N Protium Chemical compound [1H] YZCKVEUIGOORGS-IGMARMGPSA-N 0.000 description 1
- 238000001069 Raman spectroscopy Methods 0.000 description 1
- 229910004014 SiF4 Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
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- 238000002441 X-ray diffraction Methods 0.000 description 1
- 229910007667 ZnOx Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
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- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
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- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
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- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
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- VRIVJOXICYMTAG-IYEMJOQQSA-L iron(ii) gluconate Chemical compound [Fe+2].OC[C@@H](O)[C@@H](O)[C@H](O)[C@@H](O)C([O-])=O.OC[C@@H](O)[C@@H](O)[C@H](O)[C@@H](O)C([O-])=O VRIVJOXICYMTAG-IYEMJOQQSA-L 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
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- ABTOQLMXBSRXSM-UHFFFAOYSA-N silicon tetrafluoride Chemical compound F[Si](F)(F)F ABTOQLMXBSRXSM-UHFFFAOYSA-N 0.000 description 1
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- 229910052721 tungsten Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
- H10F39/10—Integrated devices
- H10F39/12—Image sensors
- H10F39/197—Bipolar transistor image sensors
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/548—Amorphous silicon PV cells
Landscapes
- Solid State Image Pick-Up Elements (AREA)
- Light Receiving Elements (AREA)
- Facsimile Heads (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Abstract
A photoelectric converting device has non-monocrystalline semiconductor layers of PIN structure laminated on mutually isolated plural pixel electrodes. P- or N-doped layer on the pixel electrode contains at least a microcrystalline structure. N- or P-doped layer on the area other than the pixel electrode is amorphous.
Description
-- 1 . , 1 Photoelectric Converting Device and Image Processing Apparatus Utilizing the Same BACKGROUND OF THE INVENTION
Field of the Invention The present invention relates to a photoelectric converting device and an image processing apparatus utilizing the same.
Related Background Art Among such photoelectric converting devices, there are well known those of PIN structure utilizing non-monocrystalline semiconductor. In particular, amorphous semiconductors, represented by amorphous silicon, are widely utilized in one-dimensional line sensors and laminate-structure solid-state image pickup devices, as they can be prepared at a low temperature and in a large area.
However, in such photoelectric converting devices of PIN structure, the P- or N-layer between the pixel electrodes is electrically insulated in order to prevent the lead of signal charge between the pixels, namely the crosstalk. This will be explained in more detail with reference to Figs. 1 and 2.
Fig. 1 is a schematic cross-sectional view of a photoelectric converting device, including a substrate 1301, pixel electrodes 1302, a ~ 2 - 2058778 1 photoconductive film 1303 composed for example of amorphous silicon, and a transparent electrode 1304.
Such device can be prepared, as disclosed for example in the Japanese Patent Laid-Open Patent No.
58-40985, by forming the pixel electrodes 1302 on the substrate 1301, then forming a photoconductive film 1303, photolithographically eliminating said photoconductive film on the pixel isolation areas, and forming the transparent electrodes 1304.
Fig. 2 is a schematic cross-sectional view of another photoelectric converting device, including a substrate 2401, pixel electrodes 2402, high-density impurity layer 2403, a pixel isolation area 2403', a photoconductive film 2404 for example of amorphous silicon, and a transparent electrode 2405.
The device shown in Fig.2 can be prepared by forming the pixel electrodes 2402 on the substrate 2401, then forming the high-concentration impurity layer (N- or P-layer) 2403, implanting oxygen or nitrogen ions only in the pixel isolation area 2403' by a photolithographic process, thereby electrically insulating the pixel electrodes, and thereafter forming the photoconductive film 2404 and the transparent electrode 2405. This method is disclosed for example in the Japanese Patent Laid-Open Application No. 60-47574. There is also known a method of eliminating only the pixel isolation area 1 2403' by etching, as disclosed in the Japanese Patent Laid-Open Patent No. 61-49569.
However, the above-mentioned methods are often associated with various drawbacks. For example, in the example shown~in Fig. 1, the etching of the photoconductive film on the pixel isolation area may form a defect in the cross section of the device, thereby causing deterioration of the characteristics, particularly an increase in the dark current. Also the step in the photoelectric converting fllm frequently results in defects in the transparent electrode, such as breakage.
Also in the example shown in Fig. 2, after the formation of N- or P-layer, the formation of the pixel isolation area by ion implantation or etching requires a photolithographic process, which inevitably deteriorates the surface of said N- or P-layer to generate defects in the N/I or P/I
interface, thereby causing deterioration of the device characteristics. Thus, in the above-explained structures, the prevention of deterioration of characteristics of PIN device cannot be often made compatible with the isolation of'devices.
SUMMARY OF THE INvENTION
In consideration of the foregoing, the present invention is to provide a photoelectric A
. .
1 converting device capable of satisfactorily achieve device isolation and preventing the deterioration of characteristics of PIN device.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a schematic cross-sectional view of an example of photoelectric converting device;
Fig. 2 is a schematic cross-sectional view of another example of photoelectric converting device;
Fig. 3 is a schematic cross-sectional view of an embodiment of the photoelectric converting device of the present invention;
Fig. 4A is a schematic cross-sectional view of a light-receiving area and related structures of another embodiment of the photoelectric converting device of the present lnvention;
Fig. 4B is an equivalent circuit diagram of a pixel of the photoelectric converting device shown in Fig 4A;
Fig. 4C is an equivalent circuit diagram and a block diagram of the entire photoelectric converting device; and Fig. 5 is a schematic block diagram of an image processing apparatus employing the photoelectric converting device of the present invention.
20~8778 l DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
The above-mentioned objects can be attained, according to the present invention, by a photoelectric converting device, having a non-monocrystalline semiconductor layer of PIN structureis laminated on mutually isolated plural pixel electrodes, wherein a P- or N-doped layer on said pixel electrodes includes a microcrystalline structure, and a P- or N-doped layer on the area other than said pixel electrodes is composed of amorphous semiconductor layer.
According to the present invention, the P-or N-layer only on the pixel electrode is selectively formed by non-monocrystalline layer including the microcrystalline structure, so that the PIN structure can be formed in continuous manner and the deterioration of the device characteristics in the patterning process can be prevented. The device isolation is also made possible by the difference in conductivity between the doped layer including the microcrystalline structure and the amorphous doped layer.
The microcrystalline structure used herein is defined by a structure in which small crystalline particles of a size of several ten to several hundred Angstroms are mixed in an amorphous material. The size of the crystalline particles can be determined, `~ 20S8778 1 for example, by X-ray diffractometry or by Raman spectroscopy.
Also in the present invention, the device isolation is possible by a ratio of conductivity, at least equal to 3.0 and preferably equal to or larger than 4.0, between the doped layer including the microcrystalline structure and the doped amorphous layer.
Also the present invention can realize an arbitrary structure by suitably selecting the materials for the pixel electrodes and for other areas, and the method and conditions of film formation, in such a manner that the N- or P-layer on the pixel electrode only has the microcrystalline structure in selective manner. It is already known that, in the preparation of N-silicon by ordinary RF
plasma CVD employing SiH4, H2 and PH3 gasses, a structural change from amorphous silicon to silicon including microcrystalline structure is possible by an increase in H2 flow rate. Also the present inventors have found, in the vicinity of the condition causing crystallization of the silicon film formed on a glass substrate, a condition inducing growth of silicon including microcrystalline structure on metals or polycrystalline silicon and growth of amorphous silicon on glass substrate or silicon dioxide. Thus the present invention can be 20~8778 1 effectively attained by suitable selection of such preparing conditions. In such film formation, there may be introduced fluorine- or chlorine-containing gas, and particularly the film formation with fluorine-containing gas provides satisfactory selectivity, and widens the freedom of designing, thus being advantageous for realizing the structure of the present invention. Examples of such film formation include HR-CVD (hydrogen radical enhanced chemical vapor deposition) employing SiF4, H2, and chemical vapor deposition employing SiH4, F2.
A preferred substance for the non-monocrystalline semiconductor layer to be employed in the present invention is silicon, but at least one of Ge, C, O, N etc. may be selectively added for adjusting the band gap, for obtaining desired characteristics.
In the present invention, the doped layer on the pixel electrode may be of N or P type.
In case of N type, the layers ar:e superposed in the order of pixel electrode/N/I/P, and, in case of P
type, the layers are superposed in the order of pixel electrode/P/I/N. In case the non-monocrystalline semiconductor is principally composed of elements of the group IV of the periodic table, such as Si, C
or Ge, the P-type impurity is composed of elements of the group IV of the periodic table, among which 20~8778 1 preferred are B and Ga. Also N-type impurity is composed of elements of the group III of the periodic table, among which preferred are P, As and Sb.
The pixel electrode in the present invention can be composed of a metal such as Al, Cr, Ni, W, Ti Mo, In, Pt or Au, an alloy containing such metal, a metal oxide such as ITO, ZnOx, IrOx or SnOx, or polycrystalline Si containing impurity at a high concentration, and the component other than the pixel electrode can be composed of an inorganic substance such as glass, SiO2, SiN or SioN, or an organic substance such as polyimide.
In the present invention, since the doped layer alone on the pixel electrode is selectively made to constitute microcrystalline line structure, the combination of the pixel electrode and the PIN
device may assume a structure of polycrystalline N -Si/N-Si/amorphous I-Si/microcrystalline P-SiC or Cr/N-SiC/amorphous I-SiGe/amorphous P-Si, for obtaining desired characteristics.
LExample]
In the following the present invention will be clarified further by embodiments thereof shown in the attached drawings.
Fig. 3 shows an embodiment of the photoelectric converting device of the present invention. Said device can be prepared by forming g 1 a Cr film of a thickness of 1000 A by sputtering on a glass substrate, then forming the pixel electrodes 102 by an ordinary photolithographic process, then continuously forming the microcrystalline N-silicon layer 103, and amorphous N-silicon layer 103' with a thickness 500 A under a selectively crystallizing condition, the amorphous I-silicon layer 104 with a thickness of 8000 A and the microcrystalline P-silicon layer 105 with a thickness of 200 A by RF
plasma CVD, and finally forming the transparent electrode 106 of ITO with a thickness 1000 A. An example of the depositing conditions of said N, I
and P layers is shown in Table 1.
Table 1 N-layer I-layerP-layer SiH4 (SCCM) 10 20 10 H2 (SCCM) 110 60 200 PH3/SiH4 (ppm)5000 B2H6/SiH (ppm) - - 3000 Reaction pressure 50 50 50 (mTorr) RF power density 0.06 n . 03 0.06 (W/cm ) Substrate temp.350 350 350 ( C) `- 2058778 l Also the photoelectric converting devices of the structures shown in Figs. 1 and 2 were prepared under similar conditions as those of the above-explained embodiment, and were subjected to the evaluation of the dark current. The dark current of the above-explained embodiment, under the application of an inverse bias voltage of 7V, was about 3 x 10 10 A/cm2, while that of the structures shown in Figs. 1 and 2 was about 1 x 10 9 A/cm , whereby the superiority of the method without the etching step could be confirmed. Also the structure of the present invention showed satisfactory device isolation characteristics.
In the following there will be explained an embodiment in which the photoelectric converting device of the foregoing embodiment is superposed on a scanning/readout circuit proposed by the present applicant in the U.S. Patent No. 4,962,412.
Referring to Fig. 4A, on an n-silicon substrate 201, there is epitaxially grown an n -layer 202 constituting a collector area, and a p-base area 203 and an n -emitter area 204 are formed therein to constitute a bipolar transistor.
Said p-base area is isolated from the adjacent pixel, and, on a space between the neighboring p-base areas, there is formed a gate electrode 206 across an oxide film 205. Thus a 1 p-channel MOS transistor is constructed, in which the neighboring p-base areas serve respectively as source and drain electrodes. The gate electrode 206 also serves as a capacitor for controlling the potential of the p-base area 203.
After the formation of an insulation layer 207, an emitter electrode 208 and a base electrode 208' are formed.
Then an SiO2 insulation layer 209 is formed, and an n polycrystalline silicon electrode 211 is formed by CVD to isolate the pixel. Said electrode 211 is electrically connected to the electrode 208'.
Subsequently RF plasma CVD is conducted to continuously form a microcrystalline N-silicon layer 212 and an amorphous N-silicon layer 212' of a thickness of 1000 A under a selectively crystallizing condition, an amorphous I-sllicon layer 213 of a thickness of 10000 A and a microcrystalline P-silicon layer 214 of a thickness of 1000 A. Finally an ITO
transparent electrode 215 of a thickness of 1000 A
is formed.
A collector electrode 217 is in ohmic contact with the rear face of the substrate 201.
Consequently the equivalent circuit of a pixel is represented by Fig. 4B. The base of a bipolar transistor 731 consisting of crystalline silicon is connected to a p-channel MOS transistor - 20S877~
1 732, a capacitor 733 and a photoelectric converting device 734 same as in the foregoing embodiment.
There are also shown a terminal 735 for giving a potential to the base, a terminal 736 for driving the p-channel MOS transistor 732 and the capacitor 733, a sensor electrode 737, an emitter electrode 738 and a collector electrode 739.
Fig. 4C is a circuit diagram in which the pixel cell 740 shown in Figs. 4A and 4B is arranged in a two-dimensional 3 x 3 matrix.
Referring to Fig. 4C, each of the unit pixel cells 740 is provided with a collector electrode 741 and a sensor electrode 742. The gate electrodes of the PMOS transistors and the capacitor electrodes are commonly connected in each row to driving lines 743, 743', 743", which are connected to a vertical shift register VSR 744. The emitter electrodes are commonly connected in each column to signal reading vertical lines 746, 746', 746", which are respectively connected to switches 747, 747', 747"
for resetting the charge in the vertical lines and signal reading switches 750, 750', 750". The gate electrodes of the resetting switches 747, 747', 747"
are commonly connected to a terminal 748 for applying a vertical line resetting pulse, and the source electrodes are commonly connected to a terminal 749 for applying a vertical line resetting voltage.
l The gate electrodes of the readout switches 750, 750', 750" are respectively connected, through lines 751, 751', 751", to a horizontal shift register (HSR) 752, and the drain electrodes are commonly connected, through a horizontal readout line 753, to an output amplifier 757. Said horizontal readout line 753 is also connected to a switch 754 for resetting the charge of said line.
Said resetting switch 754 is connected to a terminal 755 for applying a horizontal line resetting pulse, and a terminal 756 for applying a horizontal line resetting voltage.
The output of the amplifier 757 is obtained from a terminal 758.
In the following, the function of the above-explained circuit will be explained briefly with reference to Figs. 4A to 4C.
The light entering the light-absorbing layer 214, shown in Fig. 4A, is absorbed therein and generates carriers, which are accumulated in the base area 203.
When a drive pulse released from the vertical shift register appears on the drive line 743, the base potential is elevated through the capacitor, whereby the signal charges, corresponding to the amount of incident light, are obtained from the pixels of the first row to the vertical lines 746, 20~8778 . ..
746', 746".
Then the horizontal shift register 752 releases scanning pulses in succession to the lines 751, 751', 751" to effect on-off control of the switches 750, 750', 750" in succession, whereby the signals are supplied to the output terminal 758 through the amplifier 757. The reset switch 754 is turned on, between the successive on-states of the switches 750, 750', 750", thereby eliminating the remaining charge in the horizontal line 753. Then the vertical line resetting switches 747, 747', 747"
are turned on to eliminate the remaining charges in the vertical lines 746, 746', 746n. Then the vertical shift register applies a negative pulse to the driving line 743 to turn on the PMOS transistors of the pixels of the first row, thereby eliminating the remaining charges in said pixels and thus initializing said pixels.
Then a drive pulse from the vertical shift register 744 appears on the drive line 743', whereby the signal charges of the pixels of the second row are taken out in a similar manner.
Subseguently the signal charges of the pixels of the third row are taken out in a similar manner.
The present device functions by the repetition of the above-explained sequences.
Though the above-explained embodiment employs a circuit structure of the invention of the present inventors, but the device of the present invention may also be applied to the generally known circuits of photoelectric converting device.
Fig. 5 shows an example of the image processing apparatus employing the photoelectric converting device shown in Figs. 4A to 4C.
A photoelectric converting device 501 of the present invention, having photoelectric converting elements arranged in a two-dimensional matrix, effects photoelectric conversion on image information focused by an optical system 502. A driver 503 for driving said device 501 is connected thereto, and output signals bearing said image information are released in response to signals supplied from said driver 503. Said output signals are supplied to a controller 504 for signal processing, and then recorded in various memory (recording) means such as a magnetic tape, a magnetic disk, an optical disk or a semiconductor memory. Said controller 504 also controls the driver 503.
The image processing apparatus of such structure can achieve clear image recording over a prolonged period, without defects in pixels and also without time-dependent deterioration, by the use of the photoelectric converting device of the present invention.
1 The application of the photoelectric converting device of the present invention is naturally not limited to the image processing apparatus with memory means as shown in Fig. 5. For S example it is applicable to the image reader for a facsimile apparatus or a digital copying machine, or to the image pick-up device of a television camera.
As explained in the foregoing, the present invention, allowing to produce the photoelectric converting device of PIN structure in continuous manner without involving the photolithographic process, prevents the deterioration of device characteristics resulting from the defects conventionally generated at the N/I or P/I interface of the PIN device. Also since the device separation depends on the ratio of conductivity between the microcrystalline doped layer on the pixel electrode and the amorphous doped layer in other areas, it is no longer necessary, as in the conventional process, to etch the entire PIN device, and the device is therefore free from deterioration of characteristics resulting from such etching.
Thus the configuration of the present invention not only dispenses with the device isolation step which has been indispensable in the PIN structure but also allows to prevent the deterioration of device characteristics in the device isolation step, thereby allowing to obtain a photoelectric converting device with satisfactory device isolating ability and an image processing apparatus utilizing said photoelectric converting device.
Field of the Invention The present invention relates to a photoelectric converting device and an image processing apparatus utilizing the same.
Related Background Art Among such photoelectric converting devices, there are well known those of PIN structure utilizing non-monocrystalline semiconductor. In particular, amorphous semiconductors, represented by amorphous silicon, are widely utilized in one-dimensional line sensors and laminate-structure solid-state image pickup devices, as they can be prepared at a low temperature and in a large area.
However, in such photoelectric converting devices of PIN structure, the P- or N-layer between the pixel electrodes is electrically insulated in order to prevent the lead of signal charge between the pixels, namely the crosstalk. This will be explained in more detail with reference to Figs. 1 and 2.
Fig. 1 is a schematic cross-sectional view of a photoelectric converting device, including a substrate 1301, pixel electrodes 1302, a ~ 2 - 2058778 1 photoconductive film 1303 composed for example of amorphous silicon, and a transparent electrode 1304.
Such device can be prepared, as disclosed for example in the Japanese Patent Laid-Open Patent No.
58-40985, by forming the pixel electrodes 1302 on the substrate 1301, then forming a photoconductive film 1303, photolithographically eliminating said photoconductive film on the pixel isolation areas, and forming the transparent electrodes 1304.
Fig. 2 is a schematic cross-sectional view of another photoelectric converting device, including a substrate 2401, pixel electrodes 2402, high-density impurity layer 2403, a pixel isolation area 2403', a photoconductive film 2404 for example of amorphous silicon, and a transparent electrode 2405.
The device shown in Fig.2 can be prepared by forming the pixel electrodes 2402 on the substrate 2401, then forming the high-concentration impurity layer (N- or P-layer) 2403, implanting oxygen or nitrogen ions only in the pixel isolation area 2403' by a photolithographic process, thereby electrically insulating the pixel electrodes, and thereafter forming the photoconductive film 2404 and the transparent electrode 2405. This method is disclosed for example in the Japanese Patent Laid-Open Application No. 60-47574. There is also known a method of eliminating only the pixel isolation area 1 2403' by etching, as disclosed in the Japanese Patent Laid-Open Patent No. 61-49569.
However, the above-mentioned methods are often associated with various drawbacks. For example, in the example shown~in Fig. 1, the etching of the photoconductive film on the pixel isolation area may form a defect in the cross section of the device, thereby causing deterioration of the characteristics, particularly an increase in the dark current. Also the step in the photoelectric converting fllm frequently results in defects in the transparent electrode, such as breakage.
Also in the example shown in Fig. 2, after the formation of N- or P-layer, the formation of the pixel isolation area by ion implantation or etching requires a photolithographic process, which inevitably deteriorates the surface of said N- or P-layer to generate defects in the N/I or P/I
interface, thereby causing deterioration of the device characteristics. Thus, in the above-explained structures, the prevention of deterioration of characteristics of PIN device cannot be often made compatible with the isolation of'devices.
SUMMARY OF THE INvENTION
In consideration of the foregoing, the present invention is to provide a photoelectric A
. .
1 converting device capable of satisfactorily achieve device isolation and preventing the deterioration of characteristics of PIN device.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a schematic cross-sectional view of an example of photoelectric converting device;
Fig. 2 is a schematic cross-sectional view of another example of photoelectric converting device;
Fig. 3 is a schematic cross-sectional view of an embodiment of the photoelectric converting device of the present invention;
Fig. 4A is a schematic cross-sectional view of a light-receiving area and related structures of another embodiment of the photoelectric converting device of the present lnvention;
Fig. 4B is an equivalent circuit diagram of a pixel of the photoelectric converting device shown in Fig 4A;
Fig. 4C is an equivalent circuit diagram and a block diagram of the entire photoelectric converting device; and Fig. 5 is a schematic block diagram of an image processing apparatus employing the photoelectric converting device of the present invention.
20~8778 l DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
The above-mentioned objects can be attained, according to the present invention, by a photoelectric converting device, having a non-monocrystalline semiconductor layer of PIN structureis laminated on mutually isolated plural pixel electrodes, wherein a P- or N-doped layer on said pixel electrodes includes a microcrystalline structure, and a P- or N-doped layer on the area other than said pixel electrodes is composed of amorphous semiconductor layer.
According to the present invention, the P-or N-layer only on the pixel electrode is selectively formed by non-monocrystalline layer including the microcrystalline structure, so that the PIN structure can be formed in continuous manner and the deterioration of the device characteristics in the patterning process can be prevented. The device isolation is also made possible by the difference in conductivity between the doped layer including the microcrystalline structure and the amorphous doped layer.
The microcrystalline structure used herein is defined by a structure in which small crystalline particles of a size of several ten to several hundred Angstroms are mixed in an amorphous material. The size of the crystalline particles can be determined, `~ 20S8778 1 for example, by X-ray diffractometry or by Raman spectroscopy.
Also in the present invention, the device isolation is possible by a ratio of conductivity, at least equal to 3.0 and preferably equal to or larger than 4.0, between the doped layer including the microcrystalline structure and the doped amorphous layer.
Also the present invention can realize an arbitrary structure by suitably selecting the materials for the pixel electrodes and for other areas, and the method and conditions of film formation, in such a manner that the N- or P-layer on the pixel electrode only has the microcrystalline structure in selective manner. It is already known that, in the preparation of N-silicon by ordinary RF
plasma CVD employing SiH4, H2 and PH3 gasses, a structural change from amorphous silicon to silicon including microcrystalline structure is possible by an increase in H2 flow rate. Also the present inventors have found, in the vicinity of the condition causing crystallization of the silicon film formed on a glass substrate, a condition inducing growth of silicon including microcrystalline structure on metals or polycrystalline silicon and growth of amorphous silicon on glass substrate or silicon dioxide. Thus the present invention can be 20~8778 1 effectively attained by suitable selection of such preparing conditions. In such film formation, there may be introduced fluorine- or chlorine-containing gas, and particularly the film formation with fluorine-containing gas provides satisfactory selectivity, and widens the freedom of designing, thus being advantageous for realizing the structure of the present invention. Examples of such film formation include HR-CVD (hydrogen radical enhanced chemical vapor deposition) employing SiF4, H2, and chemical vapor deposition employing SiH4, F2.
A preferred substance for the non-monocrystalline semiconductor layer to be employed in the present invention is silicon, but at least one of Ge, C, O, N etc. may be selectively added for adjusting the band gap, for obtaining desired characteristics.
In the present invention, the doped layer on the pixel electrode may be of N or P type.
In case of N type, the layers ar:e superposed in the order of pixel electrode/N/I/P, and, in case of P
type, the layers are superposed in the order of pixel electrode/P/I/N. In case the non-monocrystalline semiconductor is principally composed of elements of the group IV of the periodic table, such as Si, C
or Ge, the P-type impurity is composed of elements of the group IV of the periodic table, among which 20~8778 1 preferred are B and Ga. Also N-type impurity is composed of elements of the group III of the periodic table, among which preferred are P, As and Sb.
The pixel electrode in the present invention can be composed of a metal such as Al, Cr, Ni, W, Ti Mo, In, Pt or Au, an alloy containing such metal, a metal oxide such as ITO, ZnOx, IrOx or SnOx, or polycrystalline Si containing impurity at a high concentration, and the component other than the pixel electrode can be composed of an inorganic substance such as glass, SiO2, SiN or SioN, or an organic substance such as polyimide.
In the present invention, since the doped layer alone on the pixel electrode is selectively made to constitute microcrystalline line structure, the combination of the pixel electrode and the PIN
device may assume a structure of polycrystalline N -Si/N-Si/amorphous I-Si/microcrystalline P-SiC or Cr/N-SiC/amorphous I-SiGe/amorphous P-Si, for obtaining desired characteristics.
LExample]
In the following the present invention will be clarified further by embodiments thereof shown in the attached drawings.
Fig. 3 shows an embodiment of the photoelectric converting device of the present invention. Said device can be prepared by forming g 1 a Cr film of a thickness of 1000 A by sputtering on a glass substrate, then forming the pixel electrodes 102 by an ordinary photolithographic process, then continuously forming the microcrystalline N-silicon layer 103, and amorphous N-silicon layer 103' with a thickness 500 A under a selectively crystallizing condition, the amorphous I-silicon layer 104 with a thickness of 8000 A and the microcrystalline P-silicon layer 105 with a thickness of 200 A by RF
plasma CVD, and finally forming the transparent electrode 106 of ITO with a thickness 1000 A. An example of the depositing conditions of said N, I
and P layers is shown in Table 1.
Table 1 N-layer I-layerP-layer SiH4 (SCCM) 10 20 10 H2 (SCCM) 110 60 200 PH3/SiH4 (ppm)5000 B2H6/SiH (ppm) - - 3000 Reaction pressure 50 50 50 (mTorr) RF power density 0.06 n . 03 0.06 (W/cm ) Substrate temp.350 350 350 ( C) `- 2058778 l Also the photoelectric converting devices of the structures shown in Figs. 1 and 2 were prepared under similar conditions as those of the above-explained embodiment, and were subjected to the evaluation of the dark current. The dark current of the above-explained embodiment, under the application of an inverse bias voltage of 7V, was about 3 x 10 10 A/cm2, while that of the structures shown in Figs. 1 and 2 was about 1 x 10 9 A/cm , whereby the superiority of the method without the etching step could be confirmed. Also the structure of the present invention showed satisfactory device isolation characteristics.
In the following there will be explained an embodiment in which the photoelectric converting device of the foregoing embodiment is superposed on a scanning/readout circuit proposed by the present applicant in the U.S. Patent No. 4,962,412.
Referring to Fig. 4A, on an n-silicon substrate 201, there is epitaxially grown an n -layer 202 constituting a collector area, and a p-base area 203 and an n -emitter area 204 are formed therein to constitute a bipolar transistor.
Said p-base area is isolated from the adjacent pixel, and, on a space between the neighboring p-base areas, there is formed a gate electrode 206 across an oxide film 205. Thus a 1 p-channel MOS transistor is constructed, in which the neighboring p-base areas serve respectively as source and drain electrodes. The gate electrode 206 also serves as a capacitor for controlling the potential of the p-base area 203.
After the formation of an insulation layer 207, an emitter electrode 208 and a base electrode 208' are formed.
Then an SiO2 insulation layer 209 is formed, and an n polycrystalline silicon electrode 211 is formed by CVD to isolate the pixel. Said electrode 211 is electrically connected to the electrode 208'.
Subsequently RF plasma CVD is conducted to continuously form a microcrystalline N-silicon layer 212 and an amorphous N-silicon layer 212' of a thickness of 1000 A under a selectively crystallizing condition, an amorphous I-sllicon layer 213 of a thickness of 10000 A and a microcrystalline P-silicon layer 214 of a thickness of 1000 A. Finally an ITO
transparent electrode 215 of a thickness of 1000 A
is formed.
A collector electrode 217 is in ohmic contact with the rear face of the substrate 201.
Consequently the equivalent circuit of a pixel is represented by Fig. 4B. The base of a bipolar transistor 731 consisting of crystalline silicon is connected to a p-channel MOS transistor - 20S877~
1 732, a capacitor 733 and a photoelectric converting device 734 same as in the foregoing embodiment.
There are also shown a terminal 735 for giving a potential to the base, a terminal 736 for driving the p-channel MOS transistor 732 and the capacitor 733, a sensor electrode 737, an emitter electrode 738 and a collector electrode 739.
Fig. 4C is a circuit diagram in which the pixel cell 740 shown in Figs. 4A and 4B is arranged in a two-dimensional 3 x 3 matrix.
Referring to Fig. 4C, each of the unit pixel cells 740 is provided with a collector electrode 741 and a sensor electrode 742. The gate electrodes of the PMOS transistors and the capacitor electrodes are commonly connected in each row to driving lines 743, 743', 743", which are connected to a vertical shift register VSR 744. The emitter electrodes are commonly connected in each column to signal reading vertical lines 746, 746', 746", which are respectively connected to switches 747, 747', 747"
for resetting the charge in the vertical lines and signal reading switches 750, 750', 750". The gate electrodes of the resetting switches 747, 747', 747"
are commonly connected to a terminal 748 for applying a vertical line resetting pulse, and the source electrodes are commonly connected to a terminal 749 for applying a vertical line resetting voltage.
l The gate electrodes of the readout switches 750, 750', 750" are respectively connected, through lines 751, 751', 751", to a horizontal shift register (HSR) 752, and the drain electrodes are commonly connected, through a horizontal readout line 753, to an output amplifier 757. Said horizontal readout line 753 is also connected to a switch 754 for resetting the charge of said line.
Said resetting switch 754 is connected to a terminal 755 for applying a horizontal line resetting pulse, and a terminal 756 for applying a horizontal line resetting voltage.
The output of the amplifier 757 is obtained from a terminal 758.
In the following, the function of the above-explained circuit will be explained briefly with reference to Figs. 4A to 4C.
The light entering the light-absorbing layer 214, shown in Fig. 4A, is absorbed therein and generates carriers, which are accumulated in the base area 203.
When a drive pulse released from the vertical shift register appears on the drive line 743, the base potential is elevated through the capacitor, whereby the signal charges, corresponding to the amount of incident light, are obtained from the pixels of the first row to the vertical lines 746, 20~8778 . ..
746', 746".
Then the horizontal shift register 752 releases scanning pulses in succession to the lines 751, 751', 751" to effect on-off control of the switches 750, 750', 750" in succession, whereby the signals are supplied to the output terminal 758 through the amplifier 757. The reset switch 754 is turned on, between the successive on-states of the switches 750, 750', 750", thereby eliminating the remaining charge in the horizontal line 753. Then the vertical line resetting switches 747, 747', 747"
are turned on to eliminate the remaining charges in the vertical lines 746, 746', 746n. Then the vertical shift register applies a negative pulse to the driving line 743 to turn on the PMOS transistors of the pixels of the first row, thereby eliminating the remaining charges in said pixels and thus initializing said pixels.
Then a drive pulse from the vertical shift register 744 appears on the drive line 743', whereby the signal charges of the pixels of the second row are taken out in a similar manner.
Subseguently the signal charges of the pixels of the third row are taken out in a similar manner.
The present device functions by the repetition of the above-explained sequences.
Though the above-explained embodiment employs a circuit structure of the invention of the present inventors, but the device of the present invention may also be applied to the generally known circuits of photoelectric converting device.
Fig. 5 shows an example of the image processing apparatus employing the photoelectric converting device shown in Figs. 4A to 4C.
A photoelectric converting device 501 of the present invention, having photoelectric converting elements arranged in a two-dimensional matrix, effects photoelectric conversion on image information focused by an optical system 502. A driver 503 for driving said device 501 is connected thereto, and output signals bearing said image information are released in response to signals supplied from said driver 503. Said output signals are supplied to a controller 504 for signal processing, and then recorded in various memory (recording) means such as a magnetic tape, a magnetic disk, an optical disk or a semiconductor memory. Said controller 504 also controls the driver 503.
The image processing apparatus of such structure can achieve clear image recording over a prolonged period, without defects in pixels and also without time-dependent deterioration, by the use of the photoelectric converting device of the present invention.
1 The application of the photoelectric converting device of the present invention is naturally not limited to the image processing apparatus with memory means as shown in Fig. 5. For S example it is applicable to the image reader for a facsimile apparatus or a digital copying machine, or to the image pick-up device of a television camera.
As explained in the foregoing, the present invention, allowing to produce the photoelectric converting device of PIN structure in continuous manner without involving the photolithographic process, prevents the deterioration of device characteristics resulting from the defects conventionally generated at the N/I or P/I interface of the PIN device. Also since the device separation depends on the ratio of conductivity between the microcrystalline doped layer on the pixel electrode and the amorphous doped layer in other areas, it is no longer necessary, as in the conventional process, to etch the entire PIN device, and the device is therefore free from deterioration of characteristics resulting from such etching.
Thus the configuration of the present invention not only dispenses with the device isolation step which has been indispensable in the PIN structure but also allows to prevent the deterioration of device characteristics in the device isolation step, thereby allowing to obtain a photoelectric converting device with satisfactory device isolating ability and an image processing apparatus utilizing said photoelectric converting device.
Claims (8)
1. A photoelectric converting device having non-monocrystalline semiconductor layers of PIN
structure laminated on mutually isolated plural pixel electrodes, wherein P- or N-doped layer on said pixel electrode contains at least a microcrystalline structure, and N- or P-doped layer on the area other than said pixel electrode is amorphous.
structure laminated on mutually isolated plural pixel electrodes, wherein P- or N-doped layer on said pixel electrode contains at least a microcrystalline structure, and N- or P-doped layer on the area other than said pixel electrode is amorphous.
2. A photoelectric converting device according to claim 1, wherein said non-mono-crystalline semiconductor layers contain at least silicon.
3. A photoelectric converting device according to claim 1, wherein said non-monocrystalline semiconductor layers are laminated on a substrate on which at least one of a charge accumulating unit, a driving circuit, a scanning circuit and a readout circuit is formed.
4. A photoelectric converting device according to claim 1, wherein said non-monocrystalline semiconductor layers contain at least an element selected from a group consisting of Ge, C, O and N.
5. An image processing apparatus comprising at least:
a photoelectric converting device having non-monocrystalline semiconductor layers of PIN structure laminated on mutually isolated plural pixel electrodes, wherein P- or N-doped layer on said pixel electrode contains at least a microcrystalline structure, and N- or P-doped layer on the area other than said pixel electrode is amorphous;
an optical system for entering image information into said photoelectric converting device;
a driver for driving said photoelectric converting device; and a controller for processing a signal, bearing said image information, released from said photoelectric converting device.
a photoelectric converting device having non-monocrystalline semiconductor layers of PIN structure laminated on mutually isolated plural pixel electrodes, wherein P- or N-doped layer on said pixel electrode contains at least a microcrystalline structure, and N- or P-doped layer on the area other than said pixel electrode is amorphous;
an optical system for entering image information into said photoelectric converting device;
a driver for driving said photoelectric converting device; and a controller for processing a signal, bearing said image information, released from said photoelectric converting device.
6. An image processing apparatus according to claim 5, wherein said non-monocrystalline semiconductor layers contain at least silicon.
7. An image processing apparatus according to claim 5, wherein said non-monocrystalline semiconductor layers are laminated on a substrate on which at least one of a charge accumulating unit, a driving circuit, a scanning circuit and a readout circuit is formed.
8. An image processing apparatus according to claim 6, wherein said non-monocrystalline semiconductor layers contain at least an element selected from a group consisting of Ge, C, O and N.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3012596A JP2765635B2 (en) | 1991-01-11 | 1991-01-11 | Photoelectric conversion device |
| JP3-12596 | 1991-01-11 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2058778A1 CA2058778A1 (en) | 1992-07-12 |
| CA2058778C true CA2058778C (en) | 1996-07-16 |
Family
ID=11809733
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002058778A Expired - Fee Related CA2058778C (en) | 1991-01-11 | 1992-01-06 | Photoelectric converting device and image processing apparatus utilizing the same |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US5245201A (en) |
| EP (1) | EP0494694B1 (en) |
| JP (1) | JP2765635B2 (en) |
| CA (1) | CA2058778C (en) |
| DE (1) | DE69227602T2 (en) |
Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7253437B2 (en) | 1990-12-25 | 2007-08-07 | Semiconductor Energy Laboratory Co., Ltd. | Display device having a thin film transistor |
| US5821563A (en) | 1990-12-25 | 1998-10-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device free from reverse leakage and throw leakage |
| CA2113499C (en) * | 1993-01-19 | 1999-10-19 | Yoshio Uchikata | Ink jet recording apparatus provided with means for calculating waste ink amount, and information processing system provided with such an ink jet recording apparatus |
| KR100294026B1 (en) * | 1993-06-24 | 2001-09-17 | 야마자끼 순페이 | Electro-optical device |
| US5818052A (en) * | 1996-04-18 | 1998-10-06 | Loral Fairchild Corp. | Low light level solid state image sensor |
| US5844265A (en) * | 1996-07-11 | 1998-12-01 | Synaptics, Incorporated | Sense amplifier for high-density imaging array |
| US5838176A (en) * | 1996-07-11 | 1998-11-17 | Foveonics, Inc. | Correlated double sampling circuit |
| JP4027465B2 (en) * | 1997-07-01 | 2007-12-26 | 株式会社半導体エネルギー研究所 | Active matrix display device and manufacturing method thereof |
| DE19737561C1 (en) * | 1997-08-28 | 1999-04-15 | Forschungszentrum Juelich Gmbh | Multi-color sensor |
| US5952686A (en) * | 1997-12-03 | 1999-09-14 | Hewlett-Packard Company | Salient integration mode active pixel sensor |
| JPH11274454A (en) * | 1998-03-19 | 1999-10-08 | Canon Inc | Solid-state imaging device and method of forming the same |
| US6018187A (en) * | 1998-10-19 | 2000-01-25 | Hewlett-Packard Cmpany | Elevated pin diode active pixel sensor including a unique interconnection structure |
| US6114739A (en) * | 1998-10-19 | 2000-09-05 | Agilent Technologies | Elevated pin diode active pixel sensor which includes a patterned doped semiconductor electrode |
| US6586812B1 (en) * | 1999-04-13 | 2003-07-01 | Agilent Technologies, Inc. | Isolation of alpha silicon diode sensors through ion implantation |
| US6713796B1 (en) | 2001-01-19 | 2004-03-30 | Dalsa, Inc. | Isolated photodiode |
| JP4667030B2 (en) * | 2004-12-10 | 2011-04-06 | キヤノン株式会社 | Semiconductor substrate for solid-state imaging device and manufacturing method thereof |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4523214A (en) * | 1981-07-03 | 1985-06-11 | Fuji Photo Film Co., Ltd. | Solid state image pickup device utilizing microcrystalline and amorphous silicon |
| JPS5840985A (en) * | 1981-09-04 | 1983-03-10 | Hitachi Ltd | solid-state image sensor |
| JPS6047574A (en) * | 1983-08-26 | 1985-03-14 | Toshiba Corp | Solid-state image pickup device |
| JPS60161664A (en) * | 1984-02-01 | 1985-08-23 | Sharp Corp | Tightly adhered two-dimensional image readout device |
| US4878097A (en) * | 1984-05-15 | 1989-10-31 | Eastman Kodak Company | Semiconductor photoelectric conversion device and method for making same |
| JPS6149569A (en) * | 1984-08-17 | 1986-03-11 | Matsushita Electronics Corp | solid-state imaging device |
| JPS61216358A (en) * | 1985-03-20 | 1986-09-26 | Fuji Electric Co Ltd | visual sensor |
| DE3856165T2 (en) * | 1987-01-29 | 1998-08-27 | Canon Kk | Photovoltaic converter |
| DE68927845T2 (en) * | 1988-09-30 | 1997-08-07 | Kanegafuchi Chemical Ind | Solar cell with a transparent electrode |
| JPH02275670A (en) * | 1989-01-18 | 1990-11-09 | Canon Inc | Photoelectric converter and image reader |
-
1991
- 1991-01-11 JP JP3012596A patent/JP2765635B2/en not_active Expired - Fee Related
- 1991-12-31 US US07/815,029 patent/US5245201A/en not_active Expired - Fee Related
-
1992
- 1992-01-06 CA CA002058778A patent/CA2058778C/en not_active Expired - Fee Related
- 1992-01-10 EP EP92100365A patent/EP0494694B1/en not_active Expired - Lifetime
- 1992-01-10 DE DE69227602T patent/DE69227602T2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| EP0494694A2 (en) | 1992-07-15 |
| JPH04271174A (en) | 1992-09-28 |
| EP0494694A3 (en) | 1992-07-29 |
| EP0494694B1 (en) | 1998-11-18 |
| US5245201A (en) | 1993-09-14 |
| JP2765635B2 (en) | 1998-06-18 |
| DE69227602D1 (en) | 1998-12-24 |
| DE69227602T2 (en) | 1999-06-17 |
| CA2058778A1 (en) | 1992-07-12 |
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