JPH04261070A - Photoelectric converter - Google Patents

Abstract

PURPOSE:To enhance the low afterimage property by a method wherein one of the charge implantation preventive layers is formed of a P type semiconductor layer in specific thickness containing at least a fine crystal structure. CONSTITUTION:One of the charge implantation preventive layers is formed of a P type semiconductor layer containing at least a fine crystal structure whose thickness is specified to exceed 150Angstrom . Firstly, an N type charge implantation preventive layer 13 and a photoabsorption layer 15 are completed by specific process. Next, the substrate temperature is set up at 300 deg.C by a capacity coupled type CVD device so as to lead-in 6 SCCM of SiH4, 12 SCCM of 10% diluted B2H6 and 30 SCCM of H2. Next the P type charge preventive layer 15 is completed by discharging at gas pressure of 0.3Torr and high-frequency 0.2W/cm<2> for 75min to deposit the P type amorphous semiconductor layer about 500Angstrom thick containing the fine crystal. Finally, a transparent electrode 16 is formed by specific step.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photoelectric conversion device composed of a semiconductor light receiving element such as a photodiode, and particularly to a semiconductor light receiving element used in equipment requiring high-speed reading.

0002

[Prior Art] In video information systems, optical communications, other industries, and consumer fields that use light as a medium for information signals, semiconductor photodetectors, which convert optical signals into electrical signals, are one of the most important and fundamental components. Many configurations have already been put into practical use.

[0003]The photoelectric conversion characteristics of this light-receiving element are generally required to have a high signal-to-noise ratio (high S/N ratio), be able to realize highly sensitive reading, and have a high response speed. ing. In addition, as the above-mentioned light receiving element is used as an input element for image processing apparatuses such as high-speed facsimile machines, image scanners, and copying machines, a close-contact type is desired as the apparatus becomes smaller, and the formation of a large-area element array is required. requested. In addition, as area sensors such as CCDs used in industrial surveillance and consumer video cameras, the above-mentioned light-receiving elements are designed to keep the pixel area as large as possible, as the output decreases as the pixel density increases. There is a need. Under these circumstances, technological development is progressing in photoelectric conversion devices in the direction of forming the signal processing circuit section and the light receiving element in a laminated structure to effectively use the area.

As a photoelectric conversion device that satisfies these requirements, a PIN-structured photodiode made of amorphous silicon is promising.

[0005]

[Problem to be solved by the invention] However, this P
The simplest form of an IN structure photodiode is to form each layer with amorphous silicon, but the function of the impurity layer called P layer or N layer is to reduce dark current by blocking important minority carriers. It is difficult to achieve both , and low afterimage property.

This point will be specifically explained based on the conventional example shown in FIG. That is, in FIG. 3, 51 is a glass substrate, 52 is an electrode such as Cr, 53 is N-type amorphous silicon carbide, 54 is I-type amorphous silicon, 55 is P-type amorphous silicon carbide, 56 is a transparent electrode. In this conventional example, since the P-type and N-type semiconductor layers are made of a material with a wider gap than the I-type semiconductor layer, minority carriers injected from the electrodes can be effectively blocked and dark current can be reduced. However, at the interface between the P-type semiconductor layer and the I-type semiconductor layer, energy band discontinuities and interface trap levels due to the junction of different materials occur, and carriers are trapped at these interfaces, which causes afterimages. It becomes the cause. For example, commonly PIN
To apply type photodiodes to line sensors, area sensors, etc., the optical sensor is exposed to light for a certain period of time and used in a so-called accumulation operation mode, in which photocarriers are accumulated. Then, the cause of afterimages is the acquisition and release of carriers by trap levels in the depletion layer edge (area where the depletion layer exists or does not exist) where the depletion layer expands and contracts when photocarriers are accumulated or reset to the initial state. Become.

[0007] Therefore, when emphasis is placed on low image retention, it is desirable that the interface be free of energy band discontinuities and trap levels. Therefore, both the P-type and N-type semiconductor layers are
Attempts have also been made to create a layer based on amorphous silicon, which is the same material as the layer. According to this, the energy band discontinuity and trap level at the interface are eliminated, but in this case, the doping efficiency does not increase much and the injection current increases, leading to an increase in dark current. There is.

[0008]

OBJECTS OF THE INVENTION The present invention has been made based on the above-mentioned circumstances, and it is possible to realize low afterimage properties by eliminating energy band discontinuities and trap levels at the interface with the I layer. It is an object of the present invention to provide a photoelectric conversion device that can increase ping efficiency and effectively block injection current from electrodes.

The present inventor used a conventional capacitively coupled CVD apparatus to form a P-type amorphous silicon layer containing a microcrystalline structure on an I-type amorphous silicon layer using SiH4, H2, and B2H6 as raw material gases. It has been found that when formed, a region of about 50 to 100 Å thick on the I layer side of the P layer contains almost no microcrystalline structure and remains in an amorphous state. In addition, in this P-type region that remains amorphous, B(
It was discovered that the doping efficiency of boron (boron) is not very high, and that most of the boron other than electrically activated forms trap levels that cause afterimages such as B-B bonds. There is.

0010

[Means for solving the problem] Therefore, in the present invention,
In a photoelectric conversion device having a PIN structure including an I layer made of an amorphous semiconductor and a charge injection blocking layer provided to sandwich the I layer, one of the charge injection blocking layers has at least a microcrystalline structure. The P-type semiconductor layer has a thickness of 150 Å or more.

Note that the amorphous semiconductor layer is preferably made of amorphous silicon containing hydrogen, since it is possible to form a large-area, low-temperature thin film as a photoelectric conversion element.

Further, as impurities added to the charge injection blocking layer, atoms of group III of the periodic table are used for P-type control, and atoms of group V of the periodic table are used for N-type control. Specifically, group III atoms include B (boron), A
I (aluminum), Ga (gallium), In (indium), Tl (thallium), etc. can be mentioned, and B and Ga are particularly preferred. In addition, Group V atoms include P (phosphorus), As (arsenic), Sb (antimony),
Examples include Bi (bismuth), but P and Sb are particularly preferred.

[0013] Note that the above-mentioned "
The term "microcrystalline structure" is defined as a structure in which minute crystal grains having a grain size of several tens of angstroms to several hundreds of angstroms are mixed in an amorphous state. Note that the grain size of the crystal grains can be determined by X-ray diffraction, Raman spectroscopy, or the like.

[0014]

[Function] In this way, in a PIN photodiode in which the P layer is made of amorphous silicon containing a microcrystalline structure, there are relatively few trap levels at the P layer/I layer interface, so carrier generation Since the dark current is suppressed to a low level and the doping efficiency of the region having a microcrystalline structure in the P layer is high, the dark current due to electron injection from the electrodes is also suppressed to a low level.

In other words, in order to suppress the afterimage and dark current as low as desired, first, the edge of the depletion layer should not touch the 50 to 100 Å region on the I layer side of the P layer, and the photodiode should be reverse biased. It is only necessary that the region having a microcrystalline structure in the P layer remains properly as a neutral region without being depleted even in the state where is applied.

Note that in the above PIN diode, if the depletion layer extending toward the doped layer is ΔW, then ΔW={ε・(
VR + φBI)}/q・N・WI The thickness that satisfies the above formula is the required minimum film thickness.In other words, it is the optimal film thickness, which is calculated by considering the maximum value of the sensor drive voltage. Just set it.

Here, WI: I layer thickness N: doping concentration (activated) ε: dielectric constant VR: applied voltage φBI: built-in potential of PIN junction q: unit charge For example, WI = 1 μm, N =1018cm-3, VR
=5V, the minimum required film thickness ΔW is approximately 40 Å.

As described above, in the present invention, if the thickness of the P layer is greater than the sum of this 40 Å and the above-mentioned 50 to 100 Å, that is, if the thickness of the P layer is greater than about 150 Å, Since the edge of the depletion layer can be prevented from touching the region in the P layer where there is almost no microcrystalline structure, afterimages can be suppressed to a low level.
Moreover, since the microcrystalline region in the P layer remains properly, dark current can also be suppressed to a low level.

In this case, the light may be incident from either side of the P layer or the N layer, but it is preferable that the light be incident on the P layer side, where electrons generated by light travel longer in the photodiode than holes. It's good. Further, the upper limit of the thickness of the P layer may be determined so as to obtain a desired spectral sensitivity. In particular, when used as a visible light sensor, the sensitivity in the blue region should be as high as possible. For this purpose, the thickness of the P layer is preferably 2000 Å or less, preferably 1000 Å or less.

[0020] The material used for the transparent electrode here includes ITO, SnO2, ZnO2, etc., and the lower electrode may be any commonly used metal electrode such as Cr, Al, Ti, etc. Alternatively, an N-type or P-type polysilicon film doped with high-concentration impurities may be used. In addition, when a semiconductor substrate is used as the substrate, a contact hole can be made in an insulating layer formed in the semiconductor substrate and coated with a high concentration impurity layer, and a lower electrode can be used through this. .

[0021]

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an example of the photoelectric conversion device of the present invention. Here, first, #70 manufactured by Corning
A Cr film having a thickness of 2000 Å is deposited on the glass substrate 11 of No. 59 by sputtering, and then etched into a desired shape using ordinary photolithography to form the lower electrode 12 of the photodiode. Next, using a capacitively coupled CVD device, the substrate temperature was set at 300 O C, and Si H4 was diluted to 12 SCCM and H2 was diluted to 1.
6SCCM of 0% PH3, 300SCCM of H2
, and a high frequency of 0.2 Torr at a gas pressure of 1.2 Torr.
Discharge is carried out at 0.3 W/cm2 for 5 minutes to deposit a type amorphous silicon layer of about 500 Å, thereby completing the N-type charge injection blocking layer 13. Next, the substrate temperature was increased to 30°C using the same capacitively coupled CVD equipment.
Set to 0O C, add 30SCCM of Si H4,
30SCCM of H2 was introduced, and the gas pressure was set to 0.3 Torr.
Discharge at high frequency 0.2W/cm2 for 75 minutes under r conditions,
An I-type amorphous silicon layer 14 is deposited to a thickness of about 8000 Å to complete the light absorption layer 15.

Next, using the same capacitively coupled CVD equipment, the substrate temperature was set at 300°C, and Si H4 was heated to 6SC.
CM, H2 diluted 10% B2 H6 to 12 SCCM
, 450SCCM of H2 was introduced, and the gas pressure was set to 2.0T.
A discharge is performed for 30 minutes at a high frequency of 0.5 W/cm 2 under the condition of 0.03 orr, and a P-type amorphous semiconductor layer containing microcrystals is deposited to a thickness of about 500 Å, thereby completing the P-type charge blocking layer 15.

[0024] After that, ITO was deposited by sputtering method.
A thickness of 700 Å is deposited and then etched into a desired shape using conventional photolithography to form the upper transparent electrode 16.

When the characteristics of the photodiode fabricated as described above were measured, the dark current was suppressed to a low level of approximately 3×10-11 A/cm2 when a reverse bias of 5 V was applied, and the accumulation When I measured the afterimage in operation mode with a reset time of 1 μs, it was about 0.0 in the first field.
We were able to confirm that it could be kept as low as 5%.

[0026] Next, a mode in which the photoelectric conversion device shown in the above embodiment is laminated on the scanning circuit and readout circuit proposed by the present inventors in Japanese Unexamined Patent Publication No. 63-278269 will be specifically explained. .

In FIG. 2(a), an n- layer 702 serving as a collector region is formed by epitaxial growth on an n-type silicon substrate 701, and a p-base region 7 is formed in the n- layer 702, which becomes a collector region.
03, and an n+ emitter region 704 is further formed to constitute a bipolar transistor.

The p base region 703 is separated from adjacent pixels, and a gate electrode 706 is formed between the horizontally adjacent p base regions with an oxide film 705 in between. Therefore, a p-channel MOS transistor is constructed using adjacent p base regions 703 as source and drain regions, respectively. Gate electrode 706 also functions as a capacitor for controlling the potential of p base region 703.

Furthermore, after forming the insulating layer 707, an emitter electrode 708 and a base electrode 708' are formed.

Thereafter, an insulating layer 709 is formed, followed by electrodes 711, and each pixel is separated. Here electrode 7
11 is electrically connected to the electrode 708'. Furthermore, an N-type amorphous silicon layer 712 containing microcrystals is formed to a thickness of 500 Å.
The N-type charge injection blocking layer is then formed. Subsequently, an I-type amorphous silicon layer 713 with a thickness of 8000 Å is formed to constitute a light absorption layer, and a P-type amorphous silicon layer 714 containing microcrystals is formed to form a P-type charge injection blocking layer. Configure. And finally, the transparent electrode 715
form. Further, a collector electrode 716 is ohmically connected to the back surface of the substrate 701.

Therefore, the equivalent circuit of one pixel is shown in FIG.
), a p-channel MOS transistor 732, a capacitor 733, and a photoelectric conversion device 734 similar to Embodiment 1 are connected to the base of a bipolar transistor 731 made of crystalline silicon, and a terminal 735 for applying a potential to the base is connected. , a terminal 736 for driving the p-channel MOS transistor 732 and the capacitor 733, a sensor electrode 737, an emitter electrode 738,
collector electrode 739.

FIG. 2(c) is similar to FIG. 2(a) and FIG. 2(b).
It is a circuit configuration diagram in which one pixel cell 740 shown in is arranged in a 3×3 two-dimensional matrix.

In the figure, a collector electrode 741 of one pixel cell 740 is provided for each pixel, and a sensor electrode 742 is also provided for each pixel. Also, PM
The gate electrodes and capacitor electrodes of the OS transistors are connected to drive wiring lines 743, 743', 743'' for each row, and vertical shift transistors (V.S.R.) 744
is connected to. Further, the emitter electrodes are connected to vertical wirings 746, 746', and 746'' for signal readout for each column. Vertical wiring 746, 746', 746
'' are connected to switches 747, 747', 747'' and read switches 750, 750', 750'' for resetting the charges of the vertical wiring, respectively. The gate electrodes of the reset switches 747, 747', and 747'' are commonly connected to a terminal 748 for applying a vertical line reset pulse, and the source electrodes are commonly connected to a terminal 749 for applying a vertical line reset voltage. ing. Readout switch 750, 750', 75
0'' gate electrodes are wires 751 and 751', respectively.
, 751'' through the horizontal shift register (H.S.R.
) 752, and its drain electrode is connected to an output amplifier 757 via a horizontal readout wiring 753. The horizontal readout line 753 is connected to a switch 754 for resetting the charge of the horizontal readout line.

The reset switch 754 is connected to a terminal 755 for applying a horizontal wiring reset pulse and a terminal 756 for applying a horizontal wiring reset voltage.

Finally, the output of amplifier 757 is taken out from terminal 758.

The operation will be briefly explained below using FIGS. 2(a) to 2(c).

The incident light is absorbed by the light absorption layer 713 in FIG. 2(a), and the generated carriers are absorbed into the base region 703.
accumulated within.

When the drive pulse output from the vertical shift register in FIG. 2(c) appears on the drive wiring 743, the base potential rises via the capacitor, and signal charges corresponding to the amount of light are vertically transferred from the pixels in the first row. Wiring 746, 746'
, 746'', respectively.

Next, when the horizontal shift register 752 outputs the scanning pulses to the switches 751, 751', and 751'' in sequence, the switches 750, 750', and 750'' are sequentially turned on and off, and the signals are sent to the amplifier 757. It is taken out to an output terminal 758 through. At this time, the reset switch 754 is turned on while the switches 750, 750', and 750'' are turned on in order, and the horizontal wiring 75
3 residual charges are removed.

Next, the vertical line reset switch 747,
747' and 747'' are in the ON state, and the vertical wiring 7
The residual charges of 46,746' and 746'' are removed. Then, from the vertical shift register 744 to the drive wiring 743
When a negative pulse is applied to the PM of each pixel in the first row,
The OS transistor is turned on, the base residual charge of each pixel is removed, and the pixel is initialized.

Next, a drive pulse output from the vertical shift register 744 appears on the drive wiring 743', and the signal charges of the pixels in the second row are similarly taken out.

Next, the signal charges of the pixels in the third row are taken out in the same manner.

The apparatus operates by repeating the above operations.

In the embodiments described above, examples of the circuit according to the invention of the present inventors have been shown, but the present device may be applied to the circuit of a generally known photoelectric conversion device.

[0045]

As described above, the present invention can simultaneously improve both the dark current characteristics and the afterimage characteristics of a photodiode using an amorphous semiconductor.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional structural diagram showing an embodiment of a photoelectric conversion device of the present invention.

FIG. 2(a) is a schematic cross-sectional view of the vicinity of the light receiving section of another embodiment of the photoelectric conversion device of the present invention.

FIG. 2(b) is an equivalent circuit of one pixel.

FIG. 2(c) is an equivalent circuit and block diagram of the entire photoelectric conversion device.

FIG. 3 is a schematic cross-sectional view showing a conventional example.

[Explanation of symbols]

11 Glass substrate 12 Lower electrode 13 N-type charge injection blocking layer 14 I-type amorphous silicon layer 15
P-type charge injection blocking layer 16 Transparent electrode 701 N-type silicon substrate 702 N- layer 703 P base region 704 N+ emitter region 705
Oxide film 706 Gate electrode 707 Insulating layer 708 Emitter electrode 708' Base electrode 709 Insulating layer 711 Pixel electrode 712 N-type amorphous silicon 713
I-type amorphous silicon 714 P-type amorphous silicon 715 Transparent electrode 716 Collector electrode 731 Bipolar transistor 732
p-channel MOS transistor 733
Capacitor 734 Photoelectric conversion device 735, 736 Terminal 737 Sensor electrode 738 Emitter electrode 739 Collector electrode 740 One pixel cell 741 Collector electrode 742 Sensor electrode 743, 743', 743'' Drive wiring 74
4 Vertical shift register (VSR) 746,
746', 746'' Vertical wiring 747, 74
7′, 747″ Reset switch 750,
750', 750'' readout switch 751
, 751', 751'' Wiring 752
Horizontal shift register (HSR) 753
Horizontal readout wiring 754 Reset switch 755 Terminal 756 Terminal 757 Amplifier 758 Terminal

Claims (2)

[Claims] 1. A photoelectric conversion device having a PIN structure including an I layer made of an amorphous semiconductor and a charge injection blocking layer sandwiching the I layer, wherein one of the charge injection blocking layers is provided. 1. A photoelectric conversion device comprising a P-type semiconductor layer including at least a microcrystalline structure, and wherein the P-type semiconductor layer has a thickness of 150 Å or more. 2. The photoelectric conversion device according to claim 1, wherein the amorphous semiconductor layer is amorphous silicon containing hydrogen.