CA2057389A1 - Antememoire historique predictive - Google Patents

Antememoire historique predictive

Info

Publication number
CA2057389A1
CA2057389A1 CA2057389A CA2057389A CA2057389A1 CA 2057389 A1 CA2057389 A1 CA 2057389A1 CA 2057389 A CA2057389 A CA 2057389A CA 2057389 A CA2057389 A CA 2057389A CA 2057389 A1 CA2057389 A1 CA 2057389A1
Authority
CA
Canada
Prior art keywords
cache memory
predictive
value corresponding
historical cache
contains data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2057389A
Other languages
English (en)
Other versions
CA2057389C (fr
Inventor
William R. Crick
Walter Johann Jager
Michael Lewis Takefman
Randal Keith Mullin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nortel Networks Ltd
Original Assignee
Northern Telecom Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US07/619,588 priority Critical patent/US5285527A/en
Application filed by Northern Telecom Ltd filed Critical Northern Telecom Ltd
Priority to CA002057389A priority patent/CA2057389C/fr
Publication of CA2057389A1 publication Critical patent/CA2057389A1/fr
Application granted granted Critical
Publication of CA2057389C publication Critical patent/CA2057389C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
CA002057389A 1991-12-11 1991-12-11 Antememoire historique predictive Expired - Fee Related CA2057389C (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US07/619,588 US5285527A (en) 1991-12-11 1990-11-29 Predictive historical cache memory
CA002057389A CA2057389C (fr) 1991-12-11 1991-12-11 Antememoire historique predictive

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CA002057389A CA2057389C (fr) 1991-12-11 1991-12-11 Antememoire historique predictive

Publications (2)

Publication Number Publication Date
CA2057389A1 true CA2057389A1 (fr) 1993-06-12
CA2057389C CA2057389C (fr) 1995-12-12

Family

ID=4148907

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002057389A Expired - Fee Related CA2057389C (fr) 1991-12-11 1991-12-11 Antememoire historique predictive

Country Status (2)

Country Link
US (1) US5285527A (fr)
CA (1) CA2057389C (fr)

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US5493687A (en) 1991-07-08 1996-02-20 Seiko Epson Corporation RISC microprocessor architecture implementing multiple typed register sets
US5539911A (en) * 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
JPH0735163Y2 (ja) * 1992-01-24 1995-08-09 石川ガスケット株式会社 スチールラミネートガスケット
JPH05241827A (ja) * 1992-02-27 1993-09-21 Nec Ibaraki Ltd 命令バッファ制御装置
US5367656A (en) * 1992-03-13 1994-11-22 Bull Hn Information Systems Inc. Controlling cache predictive prefetching based on cache hit ratio trend
DE69311330T2 (de) * 1992-03-31 1997-09-25 Seiko Epson Corp., Tokio/Tokyo Befehlsablauffolgeplanung von einem risc-superskalarprozessor
EP0638183B1 (fr) * 1992-05-01 1997-03-05 Seiko Epson Corporation Systeme et procede permettant d'annuler des instructions dans un microprocesseur superscalaire
US5448706A (en) * 1992-05-13 1995-09-05 Sharp Microelectronics Technology, Inc. Address generator for multi-channel circular-buffer style processing
US5628021A (en) 1992-12-31 1997-05-06 Seiko Epson Corporation System and method for assigning tags to control instruction processing in a superscalar processor
US5604912A (en) * 1992-12-31 1997-02-18 Seiko Epson Corporation System and method for assigning tags to instructions to control instruction execution
WO1994016384A1 (fr) * 1992-12-31 1994-07-21 Seiko Epson Corporation Systeme et procede permettant de changer le nom d'un registre
JPH06314241A (ja) * 1993-03-04 1994-11-08 Sharp Corp 高速半導体記憶装置及び高速連想記憶装置
WO1995001600A1 (fr) * 1993-07-02 1995-01-12 Oakleigh Systems, Inc. Systeme d'antememoire a disque predictif
US5426764A (en) * 1993-08-24 1995-06-20 Ryan; Charles P. Cache miss prediction apparatus with priority encoder for multiple prediction matches and method therefor
US5537635A (en) * 1994-04-04 1996-07-16 International Business Machines Corporation Method and system for assignment of reclaim vectors in a partitioned cache with a virtual minimum partition size
US5619675A (en) * 1994-06-14 1997-04-08 Storage Technology Corporation Method and apparatus for cache memory management using a two level scheme including a bit mapped cache buffer history table and circular cache buffer list
DE69535330T2 (de) * 1994-09-14 2007-05-31 Intel Corporation, Santa Clara Caching-System mit Explitzer Folgeliste
US5623608A (en) * 1994-11-14 1997-04-22 International Business Machines Corporation Method and apparatus for adaptive circular predictive buffer management
US5603045A (en) * 1994-12-16 1997-02-11 Vlsi Technology, Inc. Microprocessor system having instruction cache with reserved branch target section
US5640526A (en) * 1994-12-21 1997-06-17 International Business Machines Corporation Superscaler instruction pipeline having boundary indentification logic for variable length instructions
JPH08185271A (ja) * 1994-12-27 1996-07-16 Internatl Business Mach Corp <Ibm> ディスク装置用データ処理方法及びディスク装置
US5694568A (en) * 1995-07-27 1997-12-02 Board Of Trustees Of The University Of Illinois Prefetch system applicable to complex memory access schemes
US6098150A (en) * 1995-11-17 2000-08-01 Sun Microsystems, Inc. Method and apparatus for fetching information from a cache memory
US5822790A (en) * 1997-02-07 1998-10-13 Sun Microsystems, Inc. Voting data prefetch engine
US5819308A (en) * 1997-02-27 1998-10-06 Industrial Technology Research Institute Method for buffering and issuing instructions for use in high-performance superscalar microprocessors
US6163773A (en) * 1998-05-05 2000-12-19 International Business Machines Corporation Data storage system with trained predictive cache management engine
US6862635B1 (en) * 1998-11-13 2005-03-01 Cray Inc. Synchronization techniques in a multithreaded environment
US6801982B2 (en) * 2002-01-24 2004-10-05 International Business Machines Corporation Read prediction algorithm to provide low latency reads with SDRAM cache
US7096321B2 (en) * 2003-10-21 2006-08-22 International Business Machines Corporation Method and system for a cache replacement technique with adaptive skipping
EP1731998A1 (fr) * 2004-03-29 2006-12-13 Kyoto University Dispositif de traitement de donnees, programme de traitement de donnees, et moyen d enregistrement contenant le programme de traitement de donnees
KR101360221B1 (ko) * 2007-09-13 2014-02-10 삼성전자주식회사 인스트럭션 캐시 관리 방법 및 그 방법을 이용하는프로세서
US9721495B2 (en) * 2013-02-27 2017-08-01 E Ink Corporation Methods for driving electro-optic displays
GB2540221B (en) 2015-07-08 2020-01-01 Mips Tech Llc Check pointing a shift register

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US4189768A (en) * 1978-03-16 1980-02-19 International Business Machines Corporation Operand fetch control improvement
US5043870A (en) * 1982-02-24 1991-08-27 At&T Bell Laboratories Computer with automatic mapping of memory contents into machine registers during program execution
US4594659A (en) * 1982-10-13 1986-06-10 Honeywell Information Systems Inc. Method and apparatus for prefetching instructions for a central execution pipeline unit
US4626988A (en) * 1983-03-07 1986-12-02 International Business Machines Corporation Instruction fetch look-aside buffer with loop mode control
US4884197A (en) * 1985-02-22 1989-11-28 Intergraph Corporation Method and apparatus for addressing a cache memory
JPS62152043A (ja) * 1985-12-26 1987-07-07 Nec Corp 命令コ−ドアクセス制御方式
EP0258453B1 (fr) * 1986-02-28 1993-05-19 Nec Corporation Appareil de commande pour la preextraction d'instructions
US4722050A (en) * 1986-03-27 1988-01-26 Hewlett-Packard Company Method and apparatus for facilitating instruction processing of a digital computer
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US4942520A (en) * 1987-07-31 1990-07-17 Prime Computer, Inc. Method and apparatus for indexing, accessing and updating a memory
US4894772A (en) * 1987-07-31 1990-01-16 Prime Computer, Inc. Method and apparatus for qualifying branch cache entries

Also Published As

Publication number Publication date
CA2057389C (fr) 1995-12-12
US5285527A (en) 1994-02-08

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