CA2024745C - Beamformer for matrix display - Google Patents

Beamformer for matrix display Download PDF

Info

Publication number
CA2024745C
CA2024745C CA002024745A CA2024745A CA2024745C CA 2024745 C CA2024745 C CA 2024745C CA 002024745 A CA002024745 A CA 002024745A CA 2024745 A CA2024745 A CA 2024745A CA 2024745 C CA2024745 C CA 2024745C
Authority
CA
Canada
Prior art keywords
pixel
output
display
sub
image memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CA002024745A
Other languages
English (en)
French (fr)
Other versions
CA2024745A1 (en
Inventor
William Ray Hancock
Michael John Johnson
Brent Hans Larson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Honeywell Inc
Original Assignee
Honeywell Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Inc filed Critical Honeywell Inc
Publication of CA2024745A1 publication Critical patent/CA2024745A1/en
Application granted granted Critical
Publication of CA2024745C publication Critical patent/CA2024745C/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/22—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of characters or indicia using display control signals derived from coded signals representing the characters or indicia, e.g. with a character-code memory
    • G09G5/24—Generation of individual character patterns
    • G09G5/28—Generation of individual character patterns for enhancement of character form, e.g. smoothing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/399—Control of the bit-mapped memory using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Image Generation (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Digital Computer Display Output (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
CA002024745A 1989-11-06 1990-09-06 Beamformer for matrix display Expired - Lifetime CA2024745C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US43210589A 1989-11-06 1989-11-06
US07/432,105 1989-11-06

Publications (2)

Publication Number Publication Date
CA2024745A1 CA2024745A1 (en) 1991-05-07
CA2024745C true CA2024745C (en) 2002-08-06

Family

ID=23714799

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002024745A Expired - Lifetime CA2024745C (en) 1989-11-06 1990-09-06 Beamformer for matrix display

Country Status (8)

Country Link
EP (1) EP0427147B1 (fi)
JP (1) JP3089356B2 (fi)
KR (1) KR910010374A (fi)
CA (1) CA2024745C (fi)
DE (1) DE69016354T2 (fi)
DK (1) DK0427147T3 (fi)
FI (1) FI99215C (fi)
NO (1) NO303199B1 (fi)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2678462B1 (fr) * 1991-06-25 1993-12-24 Sextant Avionique Dispositif temps reel de presentation d'images de type television sur un ecran de visualisation.
US5264838A (en) * 1991-08-29 1993-11-23 Honeywell Inc. Apparatus for generating an anti-aliased display image halo
FR2793588B1 (fr) * 1999-05-11 2002-03-15 Sextant Avionique Systeme de traitement de donnees pour affichage sur un ecran matriciel
FR3119262B1 (fr) * 2021-01-25 2023-06-30 Thales Sa Système et procédé de traitement de données d'affichage de tracés en mode cavalier fournies par un boîtier générateur de symboles.

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4843380A (en) * 1987-07-13 1989-06-27 Megatek Corporation Anti-aliasing raster scan display system
US4939671A (en) * 1987-09-08 1990-07-03 Auto-Trol Technology Corporation Method and system for line drawing with next matrix feature

Also Published As

Publication number Publication date
EP0427147A2 (en) 1991-05-15
DE69016354D1 (de) 1995-03-09
EP0427147A3 (en) 1992-03-25
KR910010374A (ko) 1991-06-29
JP3089356B2 (ja) 2000-09-18
FI99215C (fi) 1997-10-27
FI905463A0 (fi) 1990-11-05
DE69016354T2 (de) 1995-06-22
NO904299D0 (no) 1990-10-03
NO904299L (no) 1991-05-07
DK0427147T3 (da) 1995-06-26
FI99215B (fi) 1997-07-15
JPH03220597A (ja) 1991-09-27
EP0427147B1 (en) 1995-01-25
NO303199B1 (no) 1998-06-08
CA2024745A1 (en) 1991-05-07

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Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed
MKEC Expiry (correction)

Effective date: 20121202