CA2021348A1 - Circuit de stockage elastique - Google Patents

Circuit de stockage elastique

Info

Publication number
CA2021348A1
CA2021348A1 CA2021348A CA2021348A CA2021348A1 CA 2021348 A1 CA2021348 A1 CA 2021348A1 CA 2021348 A CA2021348 A CA 2021348A CA 2021348 A CA2021348 A CA 2021348A CA 2021348 A1 CA2021348 A1 CA 2021348A1
Authority
CA
Canada
Prior art keywords
elastic store
timing
store memory
reset
memory circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2021348A
Other languages
English (en)
Other versions
CA2021348C (fr
Inventor
Naoyuki Izawa
Yasuhiro Aso
Yoshihiro Uchida
Satoshi Kakuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of CA2021348A1 publication Critical patent/CA2021348A1/fr
Application granted granted Critical
Publication of CA2021348C publication Critical patent/CA2021348C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0626—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Time-Division Multiplex Systems (AREA)
CA002021348A 1989-07-18 1990-07-17 Circuit de stockage elastique Expired - Fee Related CA2021348C (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP184991/1989 1989-07-18
JP1184991A JP2669697B2 (ja) 1989-07-18 1989-07-18 エラスティックストアメモリの読出し制御方式

Publications (2)

Publication Number Publication Date
CA2021348A1 true CA2021348A1 (fr) 1991-01-19
CA2021348C CA2021348C (fr) 1994-05-24

Family

ID=16162882

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002021348A Expired - Fee Related CA2021348C (fr) 1989-07-18 1990-07-17 Circuit de stockage elastique

Country Status (5)

Country Link
US (1) US5444658A (fr)
EP (1) EP0409168B1 (fr)
JP (1) JP2669697B2 (fr)
CA (1) CA2021348C (fr)
DE (1) DE69025101T2 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2874375B2 (ja) * 1991-04-11 1999-03-24 日本電気株式会社 ダブルバッファ形エラスティック・ストア
US6266385B1 (en) * 1997-12-23 2001-07-24 Wireless Facilities, Inc. Elastic store for wireless communication systems
US6243770B1 (en) * 1998-07-21 2001-06-05 Micron Technology, Inc. Method for determining status of multiple interlocking FIFO buffer structures based on the position of at least one pointer of each of the multiple FIFO buffers
GB2426084A (en) * 2005-05-13 2006-11-15 Agilent Technologies Inc Updating data in a dual port memory
JP5736962B2 (ja) 2011-05-26 2015-06-17 富士通株式会社 伝送装置および周波数ゆらぎ補償方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3867579A (en) * 1973-12-21 1975-02-18 Bell Telephone Labor Inc Synchronization apparatus for a time division switching system
US3928726A (en) * 1974-11-22 1975-12-23 Bell Telephone Labor Inc Common control variable shift reframe circuit
US4171538A (en) * 1978-01-23 1979-10-16 Rockwell International Corporation Elastic store slip circuit apparatus for preventing read and write operations interference
IT1160041B (it) * 1978-11-06 1987-03-04 Sits Soc It Telecom Siemens Memoria elastica per demultiplatore sincrono di particolare applicazione nei sistemi di trasmissione a divisione di tempo
US4287577A (en) * 1979-09-27 1981-09-01 Communications Satellite Corporation Interleaved TDMA terrestrial interface buffer
US4327411A (en) * 1980-03-04 1982-04-27 Bell Telephone Laboratories, Incorporated High capacity elastic store having continuously variable delay
DE3124516A1 (de) * 1981-06-23 1983-05-26 AEG-Telefunken Nachrichtentechnik GmbH, 7150 Backnang Anordnung zur verminderung von phasenschwankungen im ausgangstakt von elastischen speichern
JPS60254938A (ja) * 1984-05-31 1985-12-16 Nec Corp 位相整列回路
JPS6190542A (ja) * 1984-10-09 1986-05-08 Nec Corp フレ−ムアライナ
JPS62260444A (ja) * 1986-05-06 1987-11-12 Mitsubishi Electric Corp 双方向エラステイツクストア回路
JP2613257B2 (ja) * 1988-05-24 1997-05-21 株式会社日立製作所 多ポートｒａｍ

Also Published As

Publication number Publication date
DE69025101D1 (de) 1996-03-14
US5444658A (en) 1995-08-22
EP0409168B1 (fr) 1996-01-31
JP2669697B2 (ja) 1997-10-29
EP0409168A2 (fr) 1991-01-23
DE69025101T2 (de) 1996-07-11
JPH0349439A (ja) 1991-03-04
CA2021348C (fr) 1994-05-24
EP0409168A3 (en) 1991-11-13

Similar Documents

Publication Publication Date Title
EP0902433A3 (fr) Mémoire synchrone dynamique à accès aléatoire
EP0623931A3 (fr) Dispositif de mémoire à semiconducteurs synchrone ayant un circuit d'entrée pour engendrer un signal de commande majeur permettant un générateur d'horloge de verouiller des signaux de commande
EP0389202A3 (fr) Mémoire dynamique à accès oléatoire ayant une commande de ligne de mot modifiée
KR910005308A (ko) 반도체 메모리
EP0122114A3 (fr) Dispositif de mémoire à accès sélectif dynamique
EP0334357A3 (fr) Dispositif pour l'insertion d'impulsion
CA2021348A1 (fr) Circuit de stockage elastique
CA2070668A1 (fr) Processeur d'adresses pour processeur de signaux
US6070248A (en) Generation of a stable reference clock frequency from a base clock frequency that may vary depending on source
CA2022586A1 (fr) Circuit de commande de convertisseur de balayage ayant deux memoires et un generateur de signaux d'adresse transmis aux memoires
EP0261650A3 (fr) Système pour caisses enregistreuses électroniques à accès plus rapide au fichier des prix
AU4891490A (en) Data reproducing circuit for memory system
CA2148033A1 (fr) Systeme de conversion de bases de temps
WO1995028674A3 (fr) Methode et dispositif de commande d'une memoire
CA2034638A1 (fr) Systeme de conversion de donnees avec reduction de largeur de ligne
EP0397414A3 (fr) Dispositif de commande pour modification d'une microcommande
CA2116287A1 (fr) Generateur de signaux d'horloge
TW360832B (en) Data communication interface including an integrated data processor and serial memory device
KR880005762A (ko) 데이타 전송 시스템
KR910006852A (ko) 메모리 제어 시스템 및 방법
RU2001101930A (ru) Способ и устройство для запоминания различных последовательностей элементарных сигналов и доступа к ним
CA2163580A1 (fr) Memoire synchrone
US5012493A (en) Phase difference-adjusting circuit
EP0352806A3 (fr) Antémémoire et dispositif de commande d'accès utilisant une telle mémoire
EP0317963A3 (fr) Dispositif de mémoire à semi-conducteur avec des cellules DRAM

Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed