CA2015401A1 - Multi-length packet format including check sequence(s) - Google Patents
Multi-length packet format including check sequence(s)Info
- Publication number
- CA2015401A1 CA2015401A1 CA2015401A CA2015401A CA2015401A1 CA 2015401 A1 CA2015401 A1 CA 2015401A1 CA 2015401 A CA2015401 A CA 2015401A CA 2015401 A CA2015401 A CA 2015401A CA 2015401 A1 CA2015401 A1 CA 2015401A1
- Authority
- CA
- Canada
- Prior art keywords
- bits
- bit positions
- parity check
- parity
- transport word
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
MULTI-LENGTH PACKET FORMAT INCLUDING
CHECK SEQUENCE(S) Abstract A unique packet transport word, i.e., header, format is disclosed which is advantageously employed to delimit the corresponding packet and to verify data fields in the transport word. An at least first parity check is employed in conjunction with a packet length indicator to delimit the corresponding packet. The at least first parity check is formed by computing a predetermined number of parity check bits from bits in predetermined bit positions of the transport word. These parity check bits are inserted into predetermined bit positions in the transport word.
Similarly, bits representing the packet length indicator are also inserted into predetermined bit positions of the transport word. In a specific embodiment, a plurality of parity checks is employed to achieve increased robustness. The plurality of parity checks is formed such that each of the bits in predetermined bit positions of the transport word is used in computing at least two different parity check bits. In one embodiment, a first prescribed parity check is formed by computing parity over bits from predetermined bit positions in one or more groups of bit positions in the transport word and a second prescribed parity check is formed by computing parity over bits from predetermined similar bit positions in the groups of bit positions in the transport word. In one example, the transport word includes a plurality of bytes, each of which includes a predetermined number of bit positions forming columns and rows. Parity check bits forming the first prescribed parity check are obtained by computing parity from bits in predetermined bit positions in the transport word columns and parity check bits forming the second prescribed parity check are obtained by computing parity from bits in predetermined bit positions in the transport word rows. In this example, the first and second parity checks are obtained by so-called "group" processing and are adequate to both delimit the packets and verify the transport word data fields. These verified fields include, among others, the packet length and necessary information for delivery and "billing" of the packet. (FIG. 5).
CHECK SEQUENCE(S) Abstract A unique packet transport word, i.e., header, format is disclosed which is advantageously employed to delimit the corresponding packet and to verify data fields in the transport word. An at least first parity check is employed in conjunction with a packet length indicator to delimit the corresponding packet. The at least first parity check is formed by computing a predetermined number of parity check bits from bits in predetermined bit positions of the transport word. These parity check bits are inserted into predetermined bit positions in the transport word.
Similarly, bits representing the packet length indicator are also inserted into predetermined bit positions of the transport word. In a specific embodiment, a plurality of parity checks is employed to achieve increased robustness. The plurality of parity checks is formed such that each of the bits in predetermined bit positions of the transport word is used in computing at least two different parity check bits. In one embodiment, a first prescribed parity check is formed by computing parity over bits from predetermined bit positions in one or more groups of bit positions in the transport word and a second prescribed parity check is formed by computing parity over bits from predetermined similar bit positions in the groups of bit positions in the transport word. In one example, the transport word includes a plurality of bytes, each of which includes a predetermined number of bit positions forming columns and rows. Parity check bits forming the first prescribed parity check are obtained by computing parity from bits in predetermined bit positions in the transport word columns and parity check bits forming the second prescribed parity check are obtained by computing parity from bits in predetermined bit positions in the transport word rows. In this example, the first and second parity checks are obtained by so-called "group" processing and are adequate to both delimit the packets and verify the transport word data fields. These verified fields include, among others, the packet length and necessary information for delivery and "billing" of the packet. (FIG. 5).
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US371,236 | 1989-06-23 | ||
| US371,229 | 1989-06-23 | ||
| US07/371,236 US4962498A (en) | 1989-06-23 | 1989-06-23 | Multi-length packet format including check sequence(s) |
| US07/371,229 US5020054A (en) | 1989-06-23 | 1989-06-23 | Packet format including unique network identity |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2015401A1 true CA2015401A1 (en) | 1990-12-23 |
| CA2015401C CA2015401C (en) | 1993-11-09 |
Family
ID=27005292
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002015401A Expired - Fee Related CA2015401C (en) | 1989-06-23 | 1990-04-25 | Multi-length packet format including check sequence(s) |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH0336846A (en) |
| CA (1) | CA2015401C (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51123505A (en) * | 1975-04-21 | 1976-10-28 | Hitachi Ltd | Data transmission system |
| JPS5720049A (en) * | 1980-07-11 | 1982-02-02 | Fujitsu Ltd | Data transmission system |
| JPS5824253A (en) * | 1981-08-04 | 1983-02-14 | Nippon Telegr & Teleph Corp <Ntt> | Packet synthesizing system |
| JPS63224443A (en) * | 1987-03-13 | 1988-09-19 | Kokusai Denshin Denwa Co Ltd <Kdd> | Semi-storing type packet switching system |
-
1990
- 1990-04-25 CA CA002015401A patent/CA2015401C/en not_active Expired - Fee Related
- 1990-06-22 JP JP2163040A patent/JPH0336846A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0336846A (en) | 1991-02-18 |
| CA2015401C (en) | 1993-11-09 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| MKLA | Lapsed |