JPS567153A - Parity check circuit - Google Patents

Parity check circuit

Info

Publication number
JPS567153A
JPS567153A JP8222679A JP8222679A JPS567153A JP S567153 A JPS567153 A JP S567153A JP 8222679 A JP8222679 A JP 8222679A JP 8222679 A JP8222679 A JP 8222679A JP S567153 A JPS567153 A JP S567153A
Authority
JP
Japan
Prior art keywords
gates
logic
signal
input bits
parity check
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8222679A
Other languages
Japanese (ja)
Other versions
JPS592939B2 (en
Inventor
Yasunori Hiraoka
Kozo Aoyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP54082226A priority Critical patent/JPS592939B2/en
Publication of JPS567153A publication Critical patent/JPS567153A/en
Publication of JPS592939B2 publication Critical patent/JPS592939B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Detection And Correction Of Errors (AREA)
  • Error Detection And Correction (AREA)

Abstract

PURPOSE: To realize the self-check for the parity check circuit by installing independent two sets of gates through which the input bits are divided into plural groups and "1" is delivered when the input bits of logic "1" show the even number and the odd number each and with every group.
CONSTITUTION: The bits 1W7 and P in one byte are divided into plural groups and then supplied to AND gates A35WA38 plus A39WA42 via AND gates A11W A34 each. Gates A35WA38 deliver signal PEO of logic "1" when the input bits of logic "1" show the odd number; while gates A39WA42 deliver signal PEE of logic "1" when the input bits of logic "1" show the even number each. Signal PEE is supplied to OR gate OR via inverse gate NOT along with signal PEO. Then parity error signal PE is delivered from gate OR. As a result, the error of the parity check circuit itself can be detected along with the error of the input data, thus increasing the reliability of the information processor.
COPYRIGHT: (C)1981,JPO&Japio
JP54082226A 1979-06-29 1979-06-29 Parity check circuit Expired JPS592939B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54082226A JPS592939B2 (en) 1979-06-29 1979-06-29 Parity check circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54082226A JPS592939B2 (en) 1979-06-29 1979-06-29 Parity check circuit

Publications (2)

Publication Number Publication Date
JPS567153A true JPS567153A (en) 1981-01-24
JPS592939B2 JPS592939B2 (en) 1984-01-21

Family

ID=13768487

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54082226A Expired JPS592939B2 (en) 1979-06-29 1979-06-29 Parity check circuit

Country Status (1)

Country Link
JP (1) JPS592939B2 (en)

Also Published As

Publication number Publication date
JPS592939B2 (en) 1984-01-21

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